3339-11_技术文档

PRODUCT SPECIFICATION

PE3339

3.0 GHz Integer-N PLL for Low

Phase Noise Applications

Product Description

Peregrine’s PE3339 is a high performance integer-N PLL

capable of frequency synthesis up to 3.0 GHz. The

superior phase noise performance of the PE3339 makes

it ideal for applications such as wireless local loop

basestations, LMDS systems and other demanding

terrestrial systems.

Features

• 3.0 GHz operation

• ÷10/11 dual modulus prescaler

• Internal phase detector with

charge pump

• Serial programmable

• Low power ⎯ 23 mA at 3 V

• Ultra-low phase noise

The PE3339 features a 10/11 dual modulus prescaler,

counters, phase detector and a charge pump as shown

in Figure 1. Counter values are programmable through a

three wire serial interface.

• Available in 20-lead TSSOP

Fabricated in Peregrine’s patented UTSi® (Ultra Thin

Silicon) CMOS technology, the PE3339 offers excellent

RF performance with the economy and integration of

conventional CMOS.

Figure 1. Block Diagram

F_in

Prescaler

10/11

Main

Counter

13

Primary

20-bit

Latch

Secon-

dary

20-bit

Latch

PD_U

Charge

Pump

Phase

Detector

20

CP

Sdata

PD_D

6

f_r

R Counter

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Page 1 of 12

PE3339

Advance Information

Figure 2. Pin Configuration

1

20

19

18

17

16

15

14

13

12

11

V_DD

f_r

2

Enh

GND

N/C

CP

3

S_WR

4

Sdata

5

Sclk

V_DD

Dout

LD

6

GND

7

FSELS

8

E_WR

Cext

GND

9

V_DD

10

F_in

Table 1. Pin Descriptions

Pin No.

Pin Name

Type

Description

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.

1

V_DD

(Note 1)

Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-up

resistor.

2

Enh

Input

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are

transferred to the secondary register on S_WR rising edge.

3

4

5

6

7

S_WR

Sdata

Sclk

Input

Binary serial data input. Input data entered MSB first.

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit

enhancement register (E_WR “high”) on the rising edge of Sclk.

GND

Ground.

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal

counters. Internal 70 kΩ pull-down resistor.

FSELS

Input

Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement

register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.

8

E_WR

9

V_DD

F_in

(Note 1)

Input

Same as pin 1.

10

Prescaler input from the VCO. Max frequency input is 3.0 GHz.

Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be

connected in series with a 50 Ω resistor to the ground plane.

11

12

13

F_in

Input

GND

Cext

Ground.

Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an

external capacitor will low pass filter the input to the inverting amplifier used for driving LD.

Output

Output,

OD

Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,

otherwise LD is a logic low (“0”).

14

LD

15

16

Dout

V_DD

Output

Data out function, Dout, enabled in enhancement mode.

Same as pin 1.

(Note 1)

File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS

Page 2 of 12

PE3339

Advance Information

Pin No.

Pin Name

Type

Output

Description

17

18

19

20

CP

NC

GND

f_r

Charge pump current is sourced when f_cleads f_pand sinked when f_clags f_p.

No connection.

Ground.

Input

Reference frequency input.

Note 1: V_DDpins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level.

Table 2. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this UTSi device, observe the same

precautions that you would use with other ESD-

sensitive devices. Although this device contains

circuitry to protect it from damage due to ESD,

precautions should be taken to avoid exceeding the

rating specified in Table 4.

Symbol

Parameter/Conditions Min Max Units

V_DD

V_I

Supply voltage

-0.3

4.0

V

Voltage on any input

V_DD

+ 0.3

I_I

DC into any input

DC into any output

-10

-65

+10

150

mA

°C

I_O

T_stg

Storage temperature

range

Latch-Up Avoidance

Unlike conventional CMOS devices, UTSi CMOS

devices are immune to latch-up.

Table 3. Operating Ratings

Symbol

Parameter/Conditions Min Max Units

V_DD

T_A

Supply voltage

2.85

-40

3.15

85

V

Operating ambient

temperature range

°C

Table 4. ESD Ratings

Symbol

Parameter/Conditions

Level Units

1000

V_ESD

ESD voltage human body

model (Note 1)

V

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

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Page 3 of 12

PE3339

Advance Information

Table 5. DC Characteristics

V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Operational supply current;

Prescaler enabled

Digital Inputs: S_WR, Sdata, Sclk

Conditions

Min

Typ

Max

Units

I_DD

V_DD= 2.85 to 3.15 V

23

35

mA

V_IH

V_IL

I_IH

High level input voltage

V_DD= 2.85 to 3.15 V

V_IH= V_DD= 3.15 V

V_IL= 0, V_DD= 3.15 V

0.7 x V_DD

V

Low level input voltage

High level input current

Low level input current

0.3 x V_DD

+1

µA

I_IL

-1

Digital Inputs: Enh (contains a 70 kΩ pull-up resistor)

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

V_DD= 2.85 to 3.15 V

V_IH= V_DD= 3.15 V

V_IL= 0, V_DD= 3.15 V

0.7 x V_DD

V

0.3 x V_DD

+1

µA

I_IL

-100

Digital Inputs: FSELS, E_WR (contains a 70 kΩ pull-down resistor)

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

V_DD= 2.85 to 3.15 V

V_IH= V_DD= 3.15 V

V_IL= 0, V_DD= 3.15 V

0.7 x V_DD

V

0.3 x V_DD

+100

µA

I_IL

-1

Reference Divider input: f_r

I_IHRHigh level input current

I_ILRLow level input current

Counter output: Dout

V_IH= V_DD= 3.15 V

+100

0.4

µA

V_IL= 0, V_DD= 3.15 V

-100

V_OLD

V_OHD

Output voltage LOW

Output voltage HIGH

I_out= 6 mA

I_out= -3 mA

V

V_DD- 0.4

Lock detect outputs: (Cext, LD)

V_OLC

V_OHC

V_OLLD

Output voltage LOW, Cext

I_out= 0.1 mA

I_out= -0.1 mA

I_out= 1 mA

0.4

V

Output voltage HIGH, Cext

Output voltage LOW, LD

Charge Pump output: CP

I_CP– Source

I_CP– Sink

I_CPL

Drive current

V_CP= V_DD/ 2

-2.6

1.4

-1

-2

2

-1.4

2.6

1

mA

µA

%

Drive current

V_CP= V_DD/ 2

Leakage current

1.0 V < V_CP< V_DD– 1.0 V

I_CP– Source

VS. I_CPSink

Sink vs. source mismatch

15

V_CP= V_DD/ 2, T_A= 25° C

I_CPVS. V_CP

Output current magnitude variation vs. voltage

1.0 V < V_CP< V_DD– 1.0 V T_A

15

%

= 25° C

File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS

Page 4 of 12

PE3339

Advance Information

Table 6. AC Characteristics

V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 3, 4, 5)

f_Clk

t_ClkH

t_ClkL

t_DSU

t_DHLD

t_PW

Serial data clock frequency

(Note 1)

10

MHz

ns

Serial clock HIGH time

30

10

30

Serial clock LOW time

Sdata set-up time to Sclk rising edge

Sdata hold time after Sclk rising edge

S_WR pulse width

t_CWR

t_CE

t_WRC

t_EC

Sclk rising edge to S_WR rising edge

Sclk falling edge to E_WR transition

S_WR falling edge to Sclk rising edge

E_WR transition to Sclk rising edge

Main Divider (Including Prescaler)

F_in

Operating frequency

Input level range

500

-5

3000

5

MHz

dBm

P_Fin

External AC coupling

Main Divider (Prescaler Bypassed)

F_in

Operating frequency

Input level range

50

-5

300

5

MHz

dBm

P_Fin

Reference Divider

f_r

Operating frequency

(Note 3)

100

20

MHz

dBm

P_fr

Reference input power (Note 2)

Single ended input

-2

Phase Detector

f_c

Comparison frequency

(Note 3)

MHz

SSB Phase Noise (F_in= 1.3 GHz, f_r= 10 MHz, f_c= 1.25 MHz, LBW = 70 kHz, V_DD= 3.0 V, Temp = -40° C)

100 Hz Offset

1 kHz Offset

-75

-85

dBc/Hz

Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk

specification.

Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase

noise performance, the reference input falling edge rate should be faster than 80mV/ns.

Note 3: Parameter is guaranteed through characterization only and is not tested.

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Page 5 of 12

PE3339

Advance Information

Functional Description

The PE3339 consists of a prescaler, counters, a

phase detector, charge pump and control logic .

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the

value of the modulus select. Counters “R” and “M”

divide the reference and prescaler output,

respectively, by integer values stored in a 20-bit

register. An additional counter (“A”) is used in the

modulus select logic.

The phase-frequency detector generates up and

down frequency control signals which direct the

charge pump operation. The control logic includes a

selectable chip interface. Data is written into the

internal registers via the three wire serial bus.

There are also various operational and test modes

and a lock detect output.

Figure 3. Functional Block Diagram

R Counter

(6-bit)

f_r

f_c

PD_U

R(5:0)

M(8:0)

A(3:0)

Sdata

Phase

Detector

Control

Logic

Charge

Pump

CP

PD_D

Control

Pins

LD

Cext

Modulus

Select

F_in

10/11

Prescaler

M Counter

(9-bit)

f_p

File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS

Page 6 of 12

PE3339

Advance Information

Main Counter Chain

Note that programming R with “0” will pass the

reference frequency (f_r) directly to the phase

detector.

Normal Operating Mode

Setting the Pre_en control bit “low” enables the

÷10/11 prescaler. The main counter chain then

divides the RF input frequency (F_in) by an integer

derived from the values in the “M” and “A” counters.

Register Programming

Serial Interface Mode

In this mode, the output from the main counter

chain (f_p) is related to the VCO frequency (F_in) by

the following equation:

While the E_WR input is “low” and the S_WR input

is “low”, serial input data (Sdata input), B₀to B₁₉,

are clocked serially into the primary register on the

rising edge of Sclk, MSB (B₀) first. The contents

from the primary register are transferred into the

secondary register on the rising edge of either

S_WR according to the timing diagrams shown in

Figure 4. Data are transferred to the counters as

shown in Table 7 on page 9.

f_p= F_in/ [10 x (M + 1) + A]

(1)

where A ≤ M + 1, 1 ≤ M ≤ 511

When the loop is locked, F_inis related to the

reference frequency (f_r) by the following equation:

F_in= [10 x (M + 1) + A] x (f_r/ (R+1))

(2)

where A ≤ M + 1, 1 ≤ M ≤ 511

The double buffering provided by the primary and

secondary registers allows for “ping-pong” counter

control using the FSELS input. When FSELS is

“high”, the primary register contents set the counter

inputs. When FSELS is “low”, the secondary

register contents are utilized.

A consequence of the upper limit on A is that F_in

must be greater than or equal to 90 x (f_r/ (R+1)) to

obtain contiguous channels. The A counter can

accept values as high as 15, but in typical operation

it will cycle from 0 to 9 between increments in M.

While the E_WR input is “high” and the S_WR input

is “low”, serial input data (Sdata input), B₀to B₇, are

clocked serially into the enhancement register on

the rising edge of Sclk, MSB (B₀) first. The

enhancement register is double buffered to prevent

inadvertent control changes during serial loading,

with buffer capture of the serially entered data

performed on the falling edge of E_WR according to

the timing diagram shown in Figure 4. After the

falling edge of E_WR, the data provide control bits

as shown in Table 8 on page 9 will have their bit

functionality enabled by asserting the Enh input

“low”.

Programming the M counter with the minimum

allowed value of “1” will result in a minimum M

counter divide ratio of “2”.

Prescaler Bypass Mode

Setting the frequency control register bit Pre_en

“high” allows F_into bypass the ÷10/11 prescaler. In

this mode, the prescaler and A counter are powered

down, and the input VCO frequency is divided by

the M counter directly. The following equation

relates F_into the reference frequency f_r:

F_in= (M + 1) x (f_r/ (R+1))

(3)

where 1 ≤ M ≤ 511

Reference Counter

The reference counter chain divides the reference

frequency f_rdown to the phase detector comparison

frequency f_c.

The output frequency of the 6-bit R Counter is

related to the reference frequency by the following

equation:

f_c= f_r/ (R + 1)

(4)

where 0 ≤ R ≤ 63

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Page 7 of 12

PE3339

Advance Information

Table 7. Primary Register Programming

Interface Mode

Enh

R₅

R₄

M₈

M₇Pre_en M₆

B₃B₄B₅

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

Serial*

1

B₀

B₁

B₂

B₆

B₇

B₈

B₉

B₁₀

B₁₁

B₁₂

B₁₃

B₁₄

B₁₅

B₁₆

B₁₇

B₁₈

B₁₉

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Power

down

Counter

load

MSEL

output

f_coutput

Enh

Reserved

f_pOutput

Reserved

Serial*

0

B₀

B₁

B₂

B₃

B₄

B₅

B₆

B₇

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

Figure 4. Serial Interface Mode Timing Diagram

Sdata

E_WR

t_EC

t_CE

Sclk

S_WR

t_DSU

t_DHLD

t_ClkH

t_ClkL

t_CWR

t_PW

t_WRC

File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS

Page 8 of 12

PE3339

Advance Information

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

Bit Function

Reserved**

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Reserved**

f_poutput

Drives the M counter output onto the Dout output.

Power down

Counter load

MSEL output

f_coutput

Power down of all functions except programming interface.

Immediate and continuous load of counter programming.

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Drives the reference counter output onto the Dout output

Reserved**

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

from the main Counter (f_p) and the reference

counter (f_c). It has two outputs, namely PD_U, and

PD_D. If the divided VCO leads the divided

reference in phase or frequency (f_pleads f_c), PD_D

pulses “low”. If the divided reference leads the

divided VCO in phase or frequency (f_cleads f_p),

PD_U pulses “low”. The width of either pulse is

directly proportional to phase offset between the

two input signals, f_pand f_c.

current pulses from pin CP are low pass filtered

externally and then connected to the VCO tune

voltage. PD_U pulses result in a current source,

which increases the VCO frequency and PD_D

results in a current sink, which decreases VCO

frequency when using a positive Kv VCO.

A lock detect output, LD is also provided, via the pin

Cext. Cext is the logical “NAND” of PD_U and

PD_D waveforms, which is driven through a series

2 kohm resistor. Connecting Cext to an external

shunt capacitor provides low pass filtering of this

signal. Cext also drives the input of an internal

inverting comparator with an open drain output.

Thus LD is an “AND” function of PD_U and PD_D.

The signals from the phase detector couple directly

to a charge pump. PD_U controls a current source

at pin CP with constant amplitude and pulse

duration approximately the same as PD_U. PD_D

similarly drives a current sink at pin CP. The

Figure 5. Typical PE3339 Loop Filter Application Example

Charge

Pump

R

To VCO

Tune

C2

C1

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Page 9 of 12

PE3339

Advance Information

Figure 6. Package Drawing

20-lead TSSOP (JEDEC MO-153-AC)

TOP VIEW

0.65BSC

20 19

18 17 16 15 14 13 12 11

12^oREF

3.20

2X

0.20

R 0.90 MIN

4.40±0.10

Ø1.00±0.10

R 0.90 MIN

GAGE

PLANE

0^o

8^o

1.00

12^oREF

0.25

- B -

+.15

-.10

1.0 REF

0.60

.20 C B A

1

2

3

4

5

6

7

8

9

10

1.00

0.325

- A -

6.50±0.10

0.90±0.05

1.10 MAX

- C -

0.10

C

0.30 MAX

C B A

0.10±0.05

6.40

0.10

FRONT VIEW

SIDE VIEW

File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS

Page 10 of 12

PE3339

Advance Information

Table 10. Ordering Information

Order

Shipping

Method

Part Marking

Code

Description

PE3339-20TSSOP-74A

Package

3339-11

3339-12

3339-00

PE3339

20-lead TSSOP

74 units / Tube

2000 units / T&R

1 / Box

PE3339

PE3339-20TSSOP-200C

PE3339EK

PE3339-20TSSOP-EVAL KIT

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Page 11 of 12

PE3339

Advance Information

Sales Offices

United States

Japan

Peregrine Semiconductor Corp.

9450 Carroll Park Drive

San Diego, CA 92121

Peregrine Semiconductor K.K.

5A-5, 5F Imperial Tower

1-1-1 Uchisaiwaicho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel 1-858-731-9400

Fax 1-858-731-9499

Tel: (+81)-03-3507-5755

Fax: (+81)-03-3507-5601

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F- 92380 Garches France

Tel (+33)-1-47-41-91-73

Fax (+33)-1-47-41-91-73

For a list of representatives in your area, please refer to our Web site at: http://www.psemi.com

Data Sheet Identification

Advance Information

The information in this data sheet is believed to be

reliable. However, Peregrine assumes no liability for the

use of this information. Use shall be entirely at the

user’s own risk.

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change

in any manner without notice.

No patent rights or licenses to any circuits described in

this data sheet are implied or granted to any third party.

Preliminary Specification

The data sheet contains preliminary data. Additional

data may be added at a later date. Peregrine reserves

the right to change specifications at any time without

notice in order to supply the best possible product.

Peregrine’s products are not designed or intended for

use in devices or systems intended for surgical implant,

or in other applications intended to support or sustain

life, or in any application in which the failure of the

Peregrine product could create a situation in which

personal injury or death might occur. Peregrine

assumes no liability for damages, including

Product Specification

The data sheet contains final data. In the event

Peregrine decides to change the specifications,

Peregrine will notify customers of the intended changes

by issuing a DCN (Document Change Notice).

consequential or incidental damages, arising out of the

use of its products in such applications.

Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp.,

and UTSi are registered trademarks of Peregrine Semiconductor Corporation.

File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS

Page 12 of 12


型号：	3339-11
厂家：	Peregrine Semiconductor
描述：	3.0 GHz Integer-N PLL for Low Phase Noise Applications 3.0 GHz的整数N分频PLL的低相位噪声应用
文件：	总12页 (文件大小：143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

3339-11 [PSEMI]

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