42671-99 [PSEMI]
SP7T UltraCMOS 2.75 V Switch 100 - 3000 MHz, +68 dBm IIP3; SP7T的UltraCMOS 2.75 V开关100 - 3000兆赫， 68 dBm的IIP3
| 型号： | 42671-99 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | SP7T UltraCMOS 2.75 V Switch 100 - 3000 MHz, +68 dBm IIP3 |
| 文件： | 总4页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Specification
PE42671 DIE
SP7T UltraCMOS™ 2.75 V Switch
100 – 3000 MHz, +68 dBm IIP3
Figure 1. Functional Diagram
Features
• 2 TX, 2 TRX, 3 RX ports
• Three pin CMOS logic control with
integral decoder/driver
• Exceptional harmonic performance:
RX1
RX2
RX3
2fo = -83 dBc and 3fo = -78 dBc
• Low TX insertion loss: 0.65 dB at
TRX1 (WCDMA, RX)
900 MHz, 0.75 dB at 1900 MHz
• TX – RX Isolation of 47 dB at 900 MHz,
TX1 (GSM/PCS)
40 dB at 1900 MHz
TRX2 (WCDMA, RX)
TX2 (GSM/PCS)
• 1500 V HBM ESD tolerance all ports
• +68 dBm IIP3 @ 50 Ω
CMOS
Control/Driver
and ESD
• -111 dBm IMD3
• No blocking capacitors required
V1
V2
V3
Product Description
Figure 2. Die Top View*
The PE42671 is a HaRP™-enhanced SP7T
RF Switch developed on the UltraCMOS™
process technology. It addresses the specific
design needs of the Quad-Band GSM Handset
Antenna Switch Module Market for use in
GSM/PCS/EDGE/WCDMA handsets. The
switch is comprised of two transmit ports that
can be used for GSM/PCS/EDGE, two
RX1
ANT
RX2
GND
TRX1
GND
RX3
GND
TRX2
transmit/receive ports (TRX1 and TRX2) that
can be used for either WCDMA or as receive
ports, and three symmetric receive ports. On-
chip CMOS decode logic facilitates three-pin
low voltage CMOS control, while high ESD
tolerance of 1500 V at all ports, no blocking
capacitor requirements, and on-chip SAW filter
over-voltage protection devices make this the
ultimate in integration and ruggedness.
GND
ANT
GND
GND
TX2
TX1
GND
GND
GNDVDD
V1 GND V2V3 GND
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
process, providing performance superior to
GaAs with the economy and integration of
conventional CMOS.
1156 µm
* Dimensions shown are drawn die size.
Document No. 70-0196-03 │ www.psemi.com
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Page 1 of 4
PE42671
Preliminary Specification
Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V
Parameter
Condition
Typ
Units
TX - ANT (850 / 900)
0.65
0.75
0.6
0.75
0.95
1.0
dB
dB
dB
dB
dB
dB
TX - ANT (1800 / 1900)
TRX - ANT ( 850 WCDMA )
TRX - ANT ( 2100 WCDMA )
RX - ANT (850 / 900)
Insertion loss1
RX - ANT (1800 / 1900)
Port under test in on state (850 / 900)
(1800 / 1900 / 2100)
20
15
dB
dB
Return Loss
Isolation
TX - RX (850 / 900)
TX - RX (1800 / 1900)
TX - TX (850 / 900)
TX - TX (1800 / 1900)
TX - TRX (850 / 900)
TX - TRX (1800 / 1900)
TRX - RX ( 850 WCDMA)
TRX - RX (2100 WCDMA)
47
40
33
27
36
29
40
31
dB
dB
dB
dB
dB
dB
dB
dB
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
-83
-82
dBc
dBc
2nd Harmonic
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
-78
-78
dBc
dBc
3rd Harmonic
TRX1 / TRX2: Measured at 2.14 GHz at ANT port, input +20 dBm CW
signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
WCDMA 2100 IMD3
WCDMA 2100 IIP3
-111
+68
dBm
dBm
TRX1 / TRX2: Measured at 2.14 GHz at ANT port, input +20 dBm CW
signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
Note: 1. Insertion loss specified with optimal impedance matching.
Table 2. Operating Ranges
Table 3. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Power supply voltage
Min Max Units
Parameter
Symbol Min Typ Max Units
VDD
VI
-0.3
4.0
V
V
Temperature range
TOP
VDD
-40
+85
°C
V
Voltage on any input
-0.3 VDD+ 0.3
VDD Supply Voltage
2.65 2.75 2.85
TST
Storage temperature range
-65
+150
+38
°C
3,4
TX input power (50 Ω)
IDD Power Supply Current
(VDD = 2.75 V)
IDD
µA
824-915 MHz
13
50
3,4
TX input power (50 Ω)
1710-1910 MHz
+36
TX input power2 (VSWR ≤ 3:1)
PIN(50 Ω)
dBm
+35
+33
824-915 MHz
TRX input power (50 Ω)
+34
+23
+35
824 - 2170 MHz
TX input power2 (VSWR ≤ 3:1)
PIN
dBm
3,4
1710-1910 MHz
RX input power (50 Ω)
3,4
TX input power (VSWR = (∞:1)
TRX input power (VSWR ≤ 3:1)
+31
+20
824-915 MHz
824 - 2170 MHz
3,4
TX input power (VSWR = (∞:1)
RX input power2
(VSWR =1:1)
+33
+31
P
IN (∞:1)
dBm
1710-1910 MHz
PIN
VIH
VIL
dBm
V
TRX input power (VSWR = (∞:1)
824 - 2170 MHz
Control Voltage High
Control Voltage Low
1.4
ESD Voltage (HBM, MIL_STD 883
Method 3015.7)
1500
V
VESD
V
0.4
Note: 3. Assumes RF input period of 4620 µs and duty cycle of 50%.
Note: 2. Assumes RF input period of 4620 µs and duty cycle of 50%.
4. VDD within operating range specified in Table 2.
Part performance is not guaranteed under these
conditions. Exposure to absolute maximum conditions
for extended periods of time may adversely affect
reliability. Stresses in excess of absolute maximum
ratings may cause permanent damage.
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0196-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 4
Contact sales@psemi.com for full version of datasheet
PE42671
Preliminary Specification
Table 4. Pin Descriptions
Figure 3. Pad Configuration (Top View)
Pin No.
Pin Name
Description
RF Common – Antenna
2
1
24
RX1
RX2
1
ANT
Redundant ANT pins for flexible bonding
23
22
GND
RX3
GND
3
4
GND
TRX1
2
3
4
5
RX16
RF I/O – RX1
Ground
GND5
TRX16
GND5
21
20
TRX2
RF I/O – TRX1
Ground
5
GND
ANT
GND
6
7
PE42671
Die
19
18
GND
TX2
RF Common – Antenna
Redundant ANT pins for flexible bonding
6
ANT
7
GND5
TX16
GND5
GND5
VDD
Ground
8
9
TX1
17
16
GND
8
RF I/O - TX1
GND
9
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
Ground
10
GND
11
12
13
14 15
Supply
V1
Switch control input, CMOS logic level
GND5
Ground
Table 5. Truth Table
V2
Switch control input, CMOS logic level
Path
TX1 - ANT
TX2 - ANT
V3
V2
0
V1
0
V3
Switch control input, CMOS logic level
GND5
GND5
TX26
GND5
TRX26
GND5
RX36
Ground
0
0
0
1
Ground
TRX1 - ANT
TRX2 - ANT
RX1 - ANT
RX2 - ANT
RX3 - ANT
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
RF I/O – TX2
Ground
RF I/O – TRX2
Ground
RF I/O – RX3
23
24
GND5
RX26
Ground
Electrostatic Discharge (ESD) Precautions
RF I/O – RX2
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Notes: 5. Bond wires should be physically short and connected to
ground plane for best performance.
6. Blocking capacitors needed only when non-zero DC
voltage present.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 6. Ordering Information
Order Code
Description
PE42671-DIE-D
Package
Film Frame
Shipping Method
42671-90
42671-99
Wafer (Gross Die / Wafer Quantity)
400 Dice / Waffle Pack
PE42671-DIE-400G
PE42671-DIE-1H
Waffle Pack
42671-00
Evaluation Kit
1/ box
Document No. 70-0196-03 │ www.psemi.com
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Page 3 of 4
PE42671
Preliminary Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Fax: 858-731-9499
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Fax: +82-31-728-4305
South Asia Pacific
Space and Defense Products
Americas:
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Tel: 858-731-9453
Fax: +86-21-5836-7652
Europe, Asia Pacific:
180 Rue Jean de Guiramand
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Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0196-03 │ UltraCMOS™ RFIC Solutions
Page 4 of 4
Contact sales@psemi.com for full version of datasheet
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