4307-02 [PSEMI]
75 ヘ RF Digital Attenuator 5-bit, 15.5 dB, DC - 2.0 GHz; 75ヘ射频数字衰减器5位为15.5分贝， DC - 2.0 GHz的
| 型号： | 4307-02 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 75 ヘ RF Digital Attenuator 5-bit, 15.5 dB, DC - 2.0 GHz |
| 文件： | 总11页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE4307
75 Ω RF Digital Attenuator
5-bit, 15.5 dB, DC – 2.0 GHz
Product Description
Features
The PE4307 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering a 15.5 dB attenuation range in 0.5 dB steps.
The device is pin compatible with the PE430x series. This 75-
ohm RF DSA provides both parallel (latched or direct mode)
and serial CMOS control interface, operates on a single 3-volt
supply and maintains high attenuation accuracy over frequency
and temperature. It also has a unique control interface that
allows the user to select an initial attenuation state at power-
up. The PE4307 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
• Attenuation: 0.5 dB steps to 15.5 dB
• Flexible parallel and serial programming
interfaces
• Latched or direct mode
• Unique power-up state selection
• Positive CMOS control logic
• High attenuation accuracy and linearity
over temperature and frequency
• Very low power consumption
• Single-supply operation
The PE4307 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• 75 Ω impedance
• Pin compatible with PE430x series
• Packaged in a 20 Lead 4x4 mm QFN
Figure 2. Package Type
Figure 1. Functional Schematic Diagram
20 Lead 4x4 mm QFN
Switched Attenuator Array
RF Input
RF Output
5
3
1
Parallel Control
Serial Control
Control Logic Interface
Power-Up Control
Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V
Parameter
Operation Frequency
Insertion Loss1
Test Conditions
Frequency
Minimum
Typical
Maximum
2000
Units
MHz
dB
DC
-
DC ≤ 1.2 GHz
DC ≤ 1.2 GHz
1.4
-
1.95
±(0.15 + 4% of atten setting)
Not to exceed +0.25dB
dB
dB
Any Bit or Bit
Combination
Attenuation Accuracy
1 dB Compression3,4
Input IP31,2,4
-
30
-
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
DC ≤ 1.2 GHz
34
52
13
-
-
-
dBm
dBm
dB
Two-tone inputs up to
+18 dBm
Return Loss
Zo = 75 ohms
10
-
-
50% control to 0.5 dB
of final value
Switching Speed
1
µs
Notes: 1. Device Linearity will begin to degrade below 1MHz
2. Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50 Ω system.
Document No. 70-0161-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4307
Product Specification
Figure 15. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
VDD
Parameter/Conditions
Power supply voltage
Min Max Units
-0.3
-0.3
-65
-40
4.0
V
V
VDD
+
VI
Voltage on any input
0.3
1
N/C
RF1
15 C8
14
TST
Storage temperature range
150
85
°C
20-lead
QFN
Operating temperature
range
2
3
4
5
RF2
TOP
°C
13
12
11
Data
Clock
LE
P/S
4x4mm
PIN
Input power (50ꢀ)
ESD voltage (Human Body
Model)
24
dBm
V
Exposed Solder Pad
Vss/GND
GND
VESD
500
Table 4. DC Electrical Specifications
Parameter
Min
Typ
Max
Units
VDD Power Supply
Voltage
2.7
3.0
3.3
V
Table 2. Pin Descriptions
IDD Power Supply Current
Digital Input High
Digital Input Low
Input Leakage
100
µA
V
0.7xVDD
Pin
No.
Pin
Name
Description
0.3xVDD
1
V
1
2
N/C
RF1
No connect
µA
RF port (Note 1).
3
Data
Clock
LE
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Exposed Solder Pad Connection
4
5
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
6
VDD
7
N/C
No connect
8
PUP2
VDD
Power-up selection bit.
Power supply pin.
Electrostatic Discharge (ESD) Precautions
9
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
10
11
12
GND
GND
Vss/GND
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
13
14
P/S
RF2
C8
Parallel/Serial mode select.
RF port (Note 1).
15
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Latch-Up Avoidance
16
C4
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
17
C2
18
GND
C1
19
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Switching Frequency
20
C0.5
GND
The PE4307 has a maximum 25 kHz switching
rate.
Paddle
Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
Resistor on Pin 3
2: Latch Enable (LE) has an internal 100 kꢀresistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
A 10 kꢀ resistor on the input to Pin 3 (see Figure
5) will eliminate package resonance between the
RF input pin and the digital input. Specified
attenuation error versus frequency performance is
dependent upon this condition.
4. Place a 10 kꢀresistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on 3”
paragraph
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 11
PE4307
Product Specification
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
Evaluation Kit
The Digital Attenuator Evaluation Kit was designed to
ease customer evaluation of the PE4307 DSA.
J9 is used in conjunction with the supplied DC cable to
supply VDD, GND, and –VDD. If use of the internal
negative voltage generator is desired, then connect –
VDD (black banana plug) to ground. If an external –VDD
is desired, then apply -3V.
J1 should be connected to the LPT1 port of a PC with
the supplied control cable. The evaluation software is
written to operate the DSA in serial mode, so switch 7
(P/S) on the DIP switch SW1 should be ON with all
other switches off. Using the software, enable or
disable each attenuation setting to the desired
combined attenuation. The software automatically
programs the DSA each time an attenuation state is
enabled or disabled.
Note: Jumper J6 supplies power to the evaluation
board support circuits.
To evaluate the Power Up options, first disconnect the
control cable from the evaluation board. The control
cable must be removed to prevent the PC port from
biasing the control pins.
During power up with P/S=1 high and LE=1, the default
power-up signal attenuation is set to the value present
on the five control bits on the five parallel data inputs
(C0.5 to C8). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the control
bits are automatically set to one of two possible values
presented through the PUP interface. These two
values are selected by the power-up control bit, PUP2,
as shown in Table 6.
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
Pins 1 and 7 are open and may be connected to any
bias.
Note: Resistor on pin 3 is required and
should be placed as close to the part
as possible to avoid package
resonance and meet error
specifications over frequency.
Document No. 70-0161-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4307
Product Specification
Typical Performance Data (25°C, VDD=3.0 V)
Figure 6. Insertion Loss (Zo=75 ohms)
Figure 7. Attenuation at Major steps
0
16
14
12
10
8
15.5dB
-0.5
-40C
-1
25C
85C
-1.5
8dB
-2
-2.5
-3
1dB
6
0.5dB
4dB
2dB
4
-3.5
-4
2
0
0
500
1000
1500
2000
0
500
1000
RF Frequency (MHz)
1500
2000
RF Frequency (MHz)
Figure 8. Input Return Loss at Major
Figure 9. Output Return Loss at Major
Attenuation Steps (Zo=75 ohms)
Attenuation Steps (Zo=75 ohms)
0
-5
0
-10
-20
-30
-40
-50
-10
-15
-20
-25
-30
4dB
8dB
15.5dB
0
500
1000
1500
2000
0
500
1000
1500
2000
RF Frequency (MHz)
RF Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
Page 4 of 11
PE4307
Product Specification
Typical Performance Data (25°C, VDD=3.0 V)
Figure 10. Attenuation Error Vs. Frequency
Figure 11. Attenuation Error Vs. Attenuation
Setting
0.5
0
1
10Mhz
250Mhz
500Mhz
750Mhz
0.5
1010Mhz
1210Mhz
-0.5
8dB
0
15.5dB
-1
-0.5
-1
-1.5
-2
0
500
1000
1500
2000
0
2
4
6
8
10
12
14
16
RF Frequency (MHz)
Attenuation Setting (dB)
Figure 12. Input IP3 vs. Frequency (Zo=50 ohms)
Figure 13. Input 1 dB Compression (Zo=50 ohms)
60
55
50
45
40
35
30
25
20
40
35
30
25
20
15
10
5
0
0
500
1000
1500
2000
0
500
1000
1500
2000
RF Frequency (MHz)
RF Frequency (MHz)
Document No. 70-0161-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
PE4307
Product Specification
Typical Performance Data (25°C, VDD=3.0 V)
Figure 14. Attenuation Error Vs. Attenuation
Setting
Figure 15. Attenuation Error Vs. Attenuation
Setting
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
-0.1
-0.1
10MHz, -40C
10MHz, 25C
500MHz, -40C
-0.2
-0.2
10MHz, 85C
500MHz, 25C
-0.3
-0.4
-0.3
500MHz, 85C
-0.4
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Attenuation Setting (dB)
Attenuation Setting (dB)
Figure 16. Attenuation Error Vs. Attenuation
Setting
Figure 17. Attenuation Error Vs. Attenuation
Setting
0.4
0.3
0.2
0.4
0.3
0.2
0.1
0
1000MHz, -40C
0.1
0
1000MHz, 25C
1200MHz, -40C
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
1200MHz, 85C
1200MHz, 25C
1000MHz, 85C
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Attenuation Setting (dB)
Attenuation Setting (dB)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
Page 6 of 11
PE4307
Product Specification
Programming Options
serially entered into the shift register, a process that
is independent of the state of the LE input.
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4307. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The start bit (B5) of the data should
always be low to prevent an unknown state in the
device. The timing for this operation is defined by
Figure 18 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
Parallel / Direct Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 19 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
Power-up Control Settings
For latched parallel programming, the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 19) to latch new attenuation state into
device.
The PE4307 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
When the attenuator powers up in Serial mode (P/
S=1), the five control bits are set to whatever data is
present on the five parallel data inputs (C0.5 to C8).
This allows any one of the 32 attenuation settings to
be specified as the power-up state.
Table 5. Truth Table
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of two possible values. These two values are
selected by the power-up control bit, PUP2, as
shown in Table 6 (Power-Up Truth Table, Parallel
Mode).
Attenuation
P/S C8
C4
C2
C1 C0.5
State
Reference Loss
0.5 dB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1 dB
2 dB
4 dB
Table 6. Power-Up Truth Table, Parallel
Interface Mode
8 dB
15.5 dB
P/S
0
LE
0
PUP2
Attenuation State
Reference Loss
8 dB
Note: Not all 32 possible combinations of C0.5-C8 are shown in table
0
1
Serial Interface
0
0
The PE4307’s serial interface is a 6-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The latch is controlled by three CMOS-
compatible signals: Data, Clock, and Latch Enable
(LE). The Data and Clock inputs allow data to be
0
1
Defined by C0.5-C8
X
Note:
Power up with LE=1 provides normal parallel operation
with C0.5-C8, and PUP2 is not active.
Document No. 70-0161-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE4307
Product Specification
Figure 18. Serial Interface Timing Diagram
Table 7. 5-Bit Attenuator Serial Programming
Register Map
LE
B5
B4
B3
B2
B1
B0
Clock
0
C8
C4
C2
C1
C0.5
↑
↑
Data
MSB
LSB
MSB (first in)
LSB (last in
Note: The start bit (B5) must always be low to prevent an unknown
state in the device .
tLESUP
tLEPW
tSDSUP
tSDHLD
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C8:C0.5
tLEPW
tPDSUP
tPDHLD
Table 8. Serial Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
Symbol
tLEPW
Parameter
Min
10
Max
--
Unit
ns
Serial data clock
frequency (Note 1)
10
MHz
LE minimum pulse width
fClk
Data set-up time before
rising edge of LE
10
--
ns
tPDSUP
Serial clock HIGH time
Serial clock LOW time
30
30
10
ns
ns
ns
tClkH
tClkL
Data hold time after
falling edge of LE
10
--
ns
tPDHLD
LE set-up time after last
clock falling edge
tLESUP
tLEPW
LE minimum pulse width
30
10
ns
ns
Serial data set-up time
before clock rising edge
tSDSUP
Serial data hold time
after clock falling edge
10
ns
tSDHLD
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
Page 8 of 11
PE4307
Product Specification
Figure 20. Package Drawing
20 Lead 4x4 mm QFN
4.00
2.00
INDEX AREA
2.00 X 2.00
- B -
0.25
C
- A -
0.10
0.08
C
C
SEATING
PLANE
- C -
EXPOSED PAD &
TERMINAL PADS
2.00
1.00
0.435
6
10
5
1
11
0.18
15
20
16
EXPOSED PAD
2
DETAIL A
DETAIL A
0.23
0.10
C A B
1
1. Dimension applies to metallized terminal and is measured
between 0.25 and 0.30 from terminal tip.
2. Coplanarity applies to the exposed heat sink slug as well as
the terminals.
3. Dimensions are in millimeters.
Document No. 70-0161-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE4307
Product Specification
Figure 21. Marking Specifications
4307
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of PSC Lot Number
Figure 22. Tape and Reel Drawing
Table 10. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
75 units / Tube
3000 units / T&R
1 / Box
4307-01
4307-02
4307-00
4307-51
4307-52
4307
4307
PE4307-20MLP 4x4mm-75A
PE4307-20MLP 4x4mm-3000C
PE4307-20MLP 4x4mm-EK
20-lead 4x4 mm QFN
20-lead 4x4 mm QFN
Evaluation Kit
PE4307-EK
4307
PE4307G-20MLP 4x4mm-75A
PE4307G-20MLP 4x4mm-3000C
Green 20-lead 4x4 mm QFN
Green 20-lead 4x4 mm QFN
75 units / Tube
3000 units / T&R
4307
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-03 │ UltraCMOS™ RFIC Solutions
Page 10 of 11
PE4307
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel 858-731-9400
Fax 858-731-9499
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
South Asia Pacific
Peregrine Semiconductor Europe
Commercial Products:
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Fax : +33-1-47-41-91-73
Space and Defense Products:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
Document No. 70-0161-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
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