9601-00_技术文档

Product Specification

PE9601

2200 MHz UltraCMOS™ Integer-N PLL

for Rad Hard Applications

Product Description

Features

• 2200 MHz operation

Peregrine’s PE9601 is a high performance integer-N PLL

capable of frequency synthesis up to 2200 MHz. The device

is designed for superior phase noise performance while

providing an order of magnitude reduction in current

consumption, when compared with existing commercial

space PLLs.

• 10/11 prescaler

• Internal phase detector with charge

pump

• Serial, parallel or hardwired

The PE9601 features a 10/11 dual modulus prescaler,

counters and a phase comparator as shown in Figure 1.

Counter values are programmable through either a serial or

parallel interface and can also be directly hard wired.

programmable

• Low power – 25 mA at 3 V

• Targeted at Q3236 PLL replacement

• 100 Krad total dose

The PE9601 is optimized for commercial space applications.

Single Event Latch up (SEL) is physically impossible and

Single Event Upset (SEU) is better than 10^-9errors per bit/

day. Fabricated in Peregrine’s UltraCMOS™ process

technology, the PE9601 offers excellent RF performance and

intrinsic radiation tolerance.

• 44-lead CQFJ

Figure 2. Package Type

44-lead CQFJ

Figure 1. Block Diagram

F_in

Prescaler

10/11

Main

f_p

Counter

13

D(7:0)

8

Sdata

Primary

20-bit

Secon-

dary

PD_U

Charge

Pump

Phase

20

Latch

CP

20-bit

Latch

20

16

Detector

PD_D

Pre_en

M(6:0)

A(3:0)

R(3:0)

6

f_r

R Counter

f_c

Document No. 70-0025-05 │ www.psemi.com

Page 1 of 14

PE9601

Product Specification

Figure 3. Pin Configuration

6

5

4

3

2

1

44 43 42 41 40

D₀, M₀

D₁, M₁

f_c

V

7

8

39

38

37

36

35

34

33

32

31

30

29

_DD_f_c

D₂, M₂

N/C

CP

9

D₃, M₃

10

11

12

13

14

15

16

17

V_DD

C_ext

V_DD

D_out

V_DD_f_p

f_p

V_DD

S_WR, D₄, M₄

Sdata, D₅, M₅

Sclk, D₆, M₆

FSELS, D₇, Pre_en

GND

18 19 20 21 22 23 24 25 26 27 28

Table 1. Pin Descriptions

Pin No.

Pin Name

Interface Mode

ALL

Type

Description

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing

recommended.

1

V_DD

(Note 1)

2

3

4

5

6

R₀

Direct

ALL

Input

R Counter bit0 (LSB).

R Counter bit1.

R₁

Input

R₂

Input

R Counter bit2.

R₃

Input

R Counter bit3.

GND

D₀

(Note 1)

Input

Ground.

Parallel

Direct

Parallel

Direct

Parallel

Direct

Parallel

Direct

ALL

Parallel data bus bit0 (LSB).

M Counter bit0 (LSB).

Parallel data bus bit1.

M Counter bit1.

7

8

M₀

D₁

Input

M₁

D₂

Input

9

Input

Parallel data bus bit2.

M Counter bit2.

M₂

D₃

Input

10

Input

Parallel data bus bit3.

M Counter bit3.

M₃

V_DD

Input

11

12

(Note 1)

Same as pin 1.

ALL

Same as pin 1.

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 2 of 14

PE9601

Product Specification

Table 1. Pin Descriptions (continued)

Pin No.

Pin Name

Interface Mode

Type

Description

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.

Primary register data are transferred to the secondary register on S_WR or

Hop_WR rising edge.

S_WR

Serial

Input

13

D₄

Parallel

Direct

Input

Parallel data bus bit4

M Counter bit4

M₄

Sdata

D₅

Serial

Input

Binary serial data input. Input data entered MSB first.

Parallel data bus bit5.

14

15

Parallel

Direct

M₅

M Counter bit5.

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR

“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.

Sclk

Serial

Input

D₆

Parallel

Direct

Input

Parallel data bus bit6.

M Counter bit6.

M₆

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0)

for programming of internal counters while in Serial Interface Mode.

FSELS

Serial

Input

16

D₇

Parallel

Direct

ALL

Input

Parallel data bus bit7 (MSB).

Pre_en

GND

Prescaler enable, active “low”. When “high”, F_inbypasses the prescaler.

Ground.

17

18

Selects contents of primary register (FSELP=1) or secondary register (FSELP=0)

for programming of internal counters while in Parallel Interface Mode.

FSELP

A₀

Parallel

Direct

Serial

Input

A Counter bit0 (LSB).

Enhancement register write enable. While E_WR is “high”, Sdata can be serially

clocked into the enhancement register on the rising edge of Sclk.

E_WR

Enhancement register write. D[7:0] are latched into the enhancement register on

the rising edge of E_WR.

19

Parallel

Direct

Input

A₁

A Counter bit1.

M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising

edge of M2_WR.

M2_WR

A₂

Parallel

Direct

20

21

A Counter bit2.

Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode

(Bmode=0, Smode=0).

Smode

Serial, Parallel

A₃

Direct

ALL

Input

A Counter bit3 (MSB).

22

23

Bmode

V_DD

Input

Selects direct interface mode (Bmode=1).

Same as pin 1.

ALL

(Note 1)

M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising

24

25

26

27

M1_WR

A_WR

Hop_WR

F_in

Parallel

Input

edge of M1_WR.

A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising

edge of A_WR.

Parallel

Hop write. The contents of the primary register are latched into the secondary

register on the rising edge of Hop_WR.

Serial, Parallel

ALL

Prescaler input from the VCO. Input voltage = 223 mV RMS for guaranteed

operation.

Prescaler complementary input. A bypass capacitor should be placed as close as

possible to this pin and be connected directly to the ground plane.

28

29

F_in

ALL

GND

Ground.

Document No. 70-0025-05 │ www.psemi.com

Page 3 of 14

PE9601

Product Specification

Table 1. Pin Descriptions (continued)

Pin No.

Pin Name

f_p

Interface Mode

ALL

Type

Output

Description

Monitor pin for main divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding V_DDpin 31.

30

31

32

33

V_DD-f_p

Dout

V_DD

ALL

(Note 2)

Output

V_DDfor f_p.

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

Serial, Parallel

ALL

(Note 1)

Same as pin 1.

Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kW series

resistor. Connecting Cext to an external capacitor will low pass filter the input to the

inverting amplifier used for driving LD.

34

Cext

ALL

Output

35

36

V_DD

CP

ALL

(Note 1)

Output

Same as pin 1.

Charge pump current is sourced for “up” when f_cleads f_pand sinked for “down”

when f_clags f_p.

37

38

NC

ALL

No connection.

V_DDfor f_c

V_DD-f_c

(Note 2)

Output

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding V_DDpin 38.

39

f_c

ALL

40

41

42

GND

f_r

ALL

Ground.

Input

Reference frequency input. See Figure 4.

Output,

OD

Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD

is high impedance, otherwise LD is a logic low (“0”).

43

44

LD

ALL

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

Enh

Serial, Parallel

Input

Note 1: V_DDpins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level.

Note 2: V_DDpins 31 and 38 are used to enable test modes and should be left floating.

Note 3: All digital input pins have 70k ohm pull-down resistors to ground.

Figure 4. Looking into the device PIN 42 - fr

PIN 42

2.8pF

125K

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 4 of 14

PE9601

Product Specification

Table 2. Absolute Maximum Ratings

Table 4. ESD Ratings

Symbol

Parameter/Conditions

Level

Units

Symbol

Parameter/Conditions Min Max Units

V_ESD

ESD voltage (Human Body

Model) – Note 1

1000

V

V_DD

Supply voltage

-0.3

4.0

V

V_I

Voltage on any input

-0.3

V_DD

0.3

+

V

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

I_I

DC into any input

-10

-65

+10

150

mA

°C

Electrostatic Discharge (ESD) Precautions

I_O

DC into any output

When handling this UTSi device, observe the

same precautions that you would use with other

ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rating specified in Table 4.

T_stg

Storage temperature range

Absolute Maximum Ratings are those values

listed in the above table. Exceeding these values

may cause permanent device damage.

Functional operation should be restricted to the

limits in the DC Electrical Specifications table.

Exposure to absolute maximum ratings for

extended periods may affect device reliability.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Table 3. Operating Ratings

Symbol

Parameter/Conditions

Min Max Units

V_DD

Supply voltage

2.85

3.15

V

T_A

Operating ambient

temperature range

-40

85

°C

Document No. 70-0025-05 │ www.psemi.com

Page 5 of 14

PE9601

Product Specification

Table 5. DC Characteristics

V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Test Program Name

Conditions

Min

Typ

Max

Units

I_DD

Operational supply current;

IDD_T_oper_at_2 GHz

V_DD= 2.85 to 3.15 V

Prescaler enabled 2 GHz

center frequency with 10

MHz reference input.

24

mA

Digital Inputs: All except f_r, R₀, F_in, F_in

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

LEVELS_”xxx”_VIH(V)

where “xxx” is name of pin

being tested

V_DD= 2.85 to 3.15 V

0.7 x V_DD

V

LEVELS_”xxx”_VIL(V)

where “xxx” is name of pin

being tested

V

_DD= 2.85 to 3.15 V

0.3 x V_DD

+100

IIH_”xxx”_(A) where “xxx”

is name of pin being

tested

V_IH= V_DD= 3.15 V

µA

(Pull-down resistor on

input)

I_IL

Low level input current

IIL_”xxx”_(A) where “xxx”

is name of pin being

tested

V_IL= 0, V_DD= 3.15 V

-1

µA

Reference Divider input: f_r

I_IHRHigh level input current

I_ILRLow level input current

R0 Input (Pull-up Resistor): R₀

I_IHRHigh level input current

IIH_FR_(A)

IIL_FR_(A)

V_IH= V_DD= 3.15 V

+50

µA

V_IL= 0, V_DD= 3.15 V

-50

IIH_R0_(A)

IIL_R0_(A)

V_IH= V_DD= 3.15 V

+100

µA

(Pull-down resistor on

input)

I_ILR

Low level input current

V_IL= 0, V_DD= 3.15 V

I_out= 6 mA

-3

Counter and phase detector outputs: f_c, f_p.

V_OLD

Output voltage LOW

LEVELS_”xxx”_VOL(V)

where “xxx” is name of pin

being tested

0.4

V

V_OHD

Output voltage HIGH

LEVELS_”xxx”_VOH(V)

where “xxx” is name of pin

being tested

I

_out= -3 mA

V_DD- 0.4

Lock detect outputs: Cext, LD

V_OLC

V_OHC

V_OLLD

Output voltage LOW, Cext

LEVELS_CEXT_VOL(V)

LEVELS_CEXT_VOH(V)

LEVELS_ LD_VOL(V)

I_out= 0.1 mA

I_out= -0.1 mA

I_out= 6 mA

0.4

V

Output voltage HIGH, Cext

Output voltage LOW, LD

V_DD- 0.4

Charge Pump output: CP

I

_CP- Source

Drive current

Leakage current

CP_src_at_0.5 VDD (A)

CP_snk_at_0.5 VDD (A)

CP_lkg_PD_DX (A)

V_CP= V_DD/ 2

-2.6

1.4

-1

-2

2

-1.4

2.6

1

mA

µA

I

_CP– Sink

I_CPL

1.0 V < V_CP< V_DD

1.0 V

–

I_CP– Source

vs. I_CPSink

Sink vs. source mismatch

CP_srcvsnk_at_0.5 VDD

V

_CP= V_DD/ 2,

25

%

T_A= 25° C

I_CPvs. V_CP

Output current magnitude

variation vs. voltage

CP_snk_var,

CP_src_var

1.0V < V_CP< V_DD–

1.0 V T_A= 25° C

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 6 of 14

PE9601

Product Specification

Table 6. AC Characteristics

V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Test Program Name

Conditions

Min

Max

Units

Control Interface and Latches (see Figure 5 and Figure 6)

f_Clk

t_ClkH

t_ClkL

t_DSU

Serial data clock frequency

Serial clock HIGH time

Serial clock LOW time

(Note 1)

10

MHz

ns

t_clk_H (s)

t_clk_L (s)

30

10

ns

Sdata set-up time after Sclk rising

edge, D[7:0] set-up time to

M1_WR, M2_WR, A_WR, E_WR

rising edge

t_dsu_”xxx” (s) where

“xxx” is name of pin being

tested

ns

t_DHLD

Sdata hold time after Sclk rising

edge, D[7:0] hold time to M1_WR,

M2_WR, A_WR rising edge

t_dhid_”xxx” (s) where

“xxx” is name of pin being

tested

10

30

ns

t_PW

S_WR, M1_WR, M2_WR, A_WR,

E_WR pulse width

t_pw_”xxx” (s) where “xxx”

is name of pin being

tested

t_CWR

Sclk rising edge to S_WR rising

edge. S_WR, M1_WR, M2_WR,

A_WR falling edge to Hop_WR

rising edge

t_cwr_”xxx” (s) where

“xxx” is name of pin being

tested

t_CE

Sclk falling edge to E_WR

transition

t_ce (s)

30

ns

t_WRC

S_WR falling edge to Sclk rising

edge. Hop_WR falling edge to

S_WR, M1_WR, M2_WR, A_WR

rising edge

t_wrc_”xxx” (s) where

“xxx” is name of pin being

tested

t_EC

E_WR transition to Sclk rising

edge

t_ec (s)

30

ns

Main Divider (Including Prescaler)

F_in

Operating frequency

Input level range

RF_sens

200

0

2200

5

MHz

dBm

P_Fin

External AC coupling

Main Divider (Prescaler Bypassed)

F_in

Operating frequency

Input level range

20

-5

220

5

MHz

dBm

P_Fin

Reference Divider

f_r

Operating frequency

Fc_sens

(Note 3)

100

MHz

dBm

P_fr

Reference input power (Note 2)

Single ended input

-2

Phase Detector

f_c

Comparison frequency

(Note 3)

20

MHz

Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk

specification.

Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5V_p-p

.

Note 3: Parameter is guaranteed through characterization only and is not tested.

Document No. 70-0025-05 │ www.psemi.com

Page 7 of 14

PE9601

Product Specification

Functional Description

The PE9601 consists of a prescaler, counters, a

phase detector, a charge pump and control logic.

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the

value of the modulus select. Counters “R” and “M”

divide the reference and prescaler output,

respectively, by integer values stored in a 20-bit

register. An additional counter (“A”) is used in the

modulus select logic. The phase-frequency

detector generates up and down frequency control

signals, which are implemented as a pulse width

modulated current by the charge pump. The

control logic includes a selectable chip interface.

Data can be written via serial bus, parallel bus, or

hardwired direct to the pins. There are also

various operational and test modes and lock

detect.

Figure 5. Functional Block Diagram

R Counter

(6-bit)

f_r

f_c

PD_U

D(7:0)

Sdata

R(5:0)

M(8:0)

A(3:0)

Phase

Detector

Control

Logic

Charge

Pump

PD_D

C

Control

Pins

LD

Cext

2 k

Modulus

Select

F_in

10/11

Prescaler

M Counter

(9-bit)

f_p

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 8 of 14

PE9601

Product Specification

Main Counter Chain

Parallel input data, D[7:0], are latched in a parallel

fashion into one of three, 8-bit primary register

sections on the rising edge of M1_WR, M2_WR, or

A_WR per the mapping shown in Table 7 on page

10. The contents of the primary register are

transferred into a secondary register on the rising

edge of Hop_WR according to the timing diagram

shown in Figure 6. Data are transferred to the

counters as shown in Table 7 on page 10.

The main counter chain divides the RF input

frequency, F_in, by an integer derived from the user

defined values in the “M” and “A” counters. It is

composed of the 10/11 dual modulus prescaler,

modulus select logic, and 9 bit M counter. Setting

Pre_en “low” enables the 10/11 prescaler. Setting

Pre_en “high” allows F_into bypass the prescaler and

powers down the prescaler.

The secondary register acts as a buffer to allow

rapid changes to the VCO frequency. This double

buffering for “ping-pong” counter control is

programmed via the FSELP input. When FSELP is

“high”, the primary register contents set the counter

inputs. When FSELP is “low”, the secondary register

contents are utilized.

The output from the main counter chain, f_p, is related

to the VCO frequency, F_in, by the following equation:

f_p= F_in/ [10 x (M + 1) + A]

(1)

where A ≤ M + 1, M ¹ 0

When the loop is locked, F_inis related to the

reference frequency, f_r, by the following equation:

The FSELP input is synchronized with the loading of

the counters in order to minimize glitches in the

“ping-pong” case. Due to this attribute, applications

using a single register should use the secondary

register (i.e. tie FSELP “low”) to avoid problems with

the prescaler powering up in the disabled state.

Fin = [10 x (M + 1) + A] x (fr / (R+1))

(2)

where A ≤ M + 1, M ¹ 0

A consequence of the upper limit on A is that F_in

must be greater than or equal to 90 x (f_r/ (R+1)) to

obtain contiguous channels. Programming the M

Counter with the minimum value of “1” will result in a

minimum M Counter divide ratio of “2”.

Parallel input data, D[7:0], are latched into the

enhancement register on the rising edge of E_WR

according to the timing diagram shown in Figure 6.

This data provides control bits as shown in Table 8

on page 10 with bit functionality enabled by

asserting the Enh input “low”.

In Direct Interface Mode, main counter inputs M₇and

M₈are internally forced low.

Reference Counter

Direct Interface Mode

The reference counter chain divides the reference

frequency, f_r, down to the phase detector

comparison frequency, f_c.

Direct Interface Mode is selected by setting the

Bmode input “high”.

The output frequency of the 6 bit R Counter is

related to the reference frequency by the following

equation:

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M₇and M₈, and R Counter inputs R₄

and R₅are internally forced low (“0”)

f_c= f_r/ (R + 1)

where R > 0

(3)

Serial Interface Mode

Serial Interface Mode is selected by setting the

Bmode input “low” and the Smode input “high”.

Note that programming R equal to “0” will pass the

reference frequency, f_r, directly to the phase

detector.

While the E_WR input is “low” and the S_WR input

is “low”, serial input data (Sdata input), B₀to B₁₉, are

clocked serially into the primary register on the rising

edge of Sclk, MSB (B₀) first. The contents from the

primary register are transferred into the secondary

register on the rising edge of either S_WR or

Hop_WR according to the timing diagram shown in

Figure 6 and Figure 7. Data are transferred to the

counters as shown in Table 7 on page 10.

In Direct Interface Mode, R Counter inputs R₄and R₅

are internally forced low (“0”).

Register Programming

Parallel Interface Mode

Parallel Interface Mode is selected by setting the

Bmode input “low” and the Smode input “low”.

Document No. 70-0025-05 │ www.psemi.com

Page 9 of 14

PE9601

Product Specification

The double buffering provided by the primary and

secondary registers allows for “ping-pong” counter

control using the FSELS input. When FSELS is

“high”, the primary register contents set the

counter inputs. When FSELS is “low”, the

secondary register contents are utilized.

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

7. After the falling edge of E_WR, the data

provide control bits as shown in Table 8 with bit

functionality enabled by asserting the Enh input

“low”.

While the E_WR input is “high” and the S_WR

input is “low”, serial input data (Sdata input), B₀to

B₇, are clocked serially into the enhancement

register on the rising edge of Sclk, MSB (B₀) first.

Table 7. Primary Register Programming

Interface

Mode

Enh

Bmode Smode

R₅

R₄

M₈

M₇Pre_en M₆

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

Parallel

1

0

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

D₃

B₀

0

D₂

B₁

0

D₁

B₂

0

D₀

B₃

0

D₇

B₄

D₆

B₅

D₅

B₆

M₅

D₄

B₇

M₄

D₃

B₈

M₃

D₂

B₉

M₂

D₁

B₁₀

M₁

D₀

B₁₁

M₀

D₇

B₁₂

R₃

D₆

B₁₃

R₂

D₅

B₁₄

R₁

D₄

B₁₅

R₀

D₃

B₁₆

A₃

D₂

B₁₇

A₂

D₁

D₀

Serial*

Direct

1

0

1

B₁₈B₁₉

A₁A₀

X

Pre_en M₆

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Power

down

Counter

load

MSEL

output

Prescaler

output

Enh

Bmode Smode

Reserved

f_c, f_pOE

E_WR rising edge load

Parallel

Serial*

0

X

0

1

D₇

B₀

D₆

B₁

D₅

B₂

D₄

D₃

D₂

B₅

D₁

B₆

D₀

B₇

B₃

B₄

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 10 of 14

PE9601

Product Specification

Figure 6. Parallel Interface Mode Timing Diagram

t_DSU

t_DHLD

D 7 : 0

[ ]

t_PW

t_CWR

t_WRC

M1_WR

M2_WR

A_WR

t_PW

E_WR

Hop_WR

Figure 7. Serial Interface Mode Timing Diagram

Sdata

E_WR

t_EC

t_CE

Sclk

S_WR

t_DSU

t_DHLD

t_ClkH

t_ClkL

t_CWR

t_PW

t_WRC

Document No. 70-0025-05 │ www.psemi.com

Page 11 of 14

PE9601

Product Specification

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

Bit Function

Reserved**

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Reserved**

Power down

Counter load

Power down of all functions except programming interface.

Immediate and continuous load of counter programming as directed by the Bmode and

Bit 5

Bit 6

Bit 7

MSEL output

Prescaler output

f_p, f_cOE

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Drives the raw internal prescaler output (fmain) onto the Dout output.

f_p, f_coutputs disabled.

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

from the main Counter (f_p) and the reference

counter (f_c). It has two outputs, namely PD_U,

and PD_D. If the divided VCO leads the divided

reference in phase or frequency (f_pleads f_c),

PD_D pulses “high”. If the divided reference leads

the divided VCO in phase or frequency (f_rleads

f_p), PD_U pulses “high”. The width of either pulse

is directly proportional to phase offset between the

two input signals, f_pand f_c.

The current pulses from pin CP are low pass fil-

tered externally and then connected to the VCO

tune voltage. PD_U pulses result in a current

source, which increases the VCO frequency and

PD_D results in a current sink, which decreases

VCO frequency.

A lock detect output, LD is also provided, via the

pin Cext. Cext is the logical “OR” of PD_U and

PD_D waveforms, which is driven through a series

2 k ohm resistor. Connecting Cext to an external

shunt capacitor provides integration. Cext also

drives the input of an internal inverting comparator

with an open drain output. Thus LD is an “NOR”

function of PD_U and PD_D.

The signals from the phase detector couple di-

rectly to a charge pump. PD_U controls a current

source at pin CP with constant amplitude and

pulse duration approximately the same as PD_U.

PD_D similarly drives a current sink at pin CP.

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 12 of 14

PE9601

Product Specification

Figure 8. Package Drawing

44-lead CQFJ

All dimensions are in mils

Table 10. Ordering Information

Order Code

9601-01

Part Marking

PE9601

Description

Engineering Samples

Package

44-pin CQFJ

Shipping Method

40 units / Tray

1 / Box

9601-11

PE9601

Flight Units

44-pin CQFJ

9601-00

PE9601EK

Evaluation Board

Document No. 70-0025-05 │ www.psemi.com

Page 13 of 14

PE9601

Product Specification

Sales Offices

The Americas

North Asia Pacific

Peregrine Semiconductor Corp.

9450 Carroll Park Drive

San Diego, CA 92121

Peregrine Semiconductor K.K.

5A-5, 5F Imperial Tower

1-1-1 Uchisaiwaicho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel 858-731-9400

Fax 858-731-9499

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

Europe

South Asia Pacific

Peregrine Semiconductor Europe

Commercial Products:

Bâtiment Maine

13-15 rue des Quatre Vents

F- 92380 Garches, France

Tel: +33-1-47-41-91-73

Peregrine Semiconductor

28G, Times Square,

No. 500 Zhangyang Road,

Shanghai, 200122, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Fax : +33-1-47-41-91-73

Space and Defense Products:

180 Rue Jean de Guiramand

13852 Aix-En-Provence cedex 3, France

Tel: +33(0) 4 4239 3361

Fax: +33(0) 4 4239 7227

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The information in this data sheet is believed to be reliable.

However, Peregrine assumes no liability for the use of this

information. Use shall be entirely at the user’s own risk.

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Preliminary Specification

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS is a trademark of Peregrine Semiconductor

Corp.

Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions

Page 14 of 14


型号：	9601-00
厂家：	Peregrine Semiconductor
描述：	2200 MHz UltraCMOS? Integer-N PLL for Rad Hard Applications 2200兆赫UltraCMOS⑩整数N分频PLL，抗辐射应用
文件：	总14页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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