PE3336 [PSEMI]
3000 MHz UltraCMOS? Integer-N PLL for Low Phase Noise Applications; 3000兆赫UltraCMOS⑩整数N分频PLL的低相位噪声应用
| 型号： | PE3336 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 3000 MHz UltraCMOS? Integer-N PLL for Low Phase Noise Applications |
| 文件： | 总15页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE3336
3000 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Product Description
Features
Peregrine’s PE3336 is a high performance integer-N PLL
capable of frequency synthesis up to 3000 MHz. The
superior phase noise performance of the PE3336 makes it
ideal for applications such as LMDS / MMDS / WLL
basestations and demanding terrestrial systems.
• 3000 MHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial, parallel or hardwired
The PE3336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
programmable
• Pin compatible with PE3236
• Ultra-low phase noise
The PE3336 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
• Available in 44-lead PLCC and
7x7 mm 48-lead QFN package
Figure 1. Block Diagram
Fin
Fin
Prescaler
10 / 11
Main
Counter
fp
13
D(7:0)
8
Sdata
Primary
20-bit
Latch
Secon-
dary
20-bit
Latch
PD_U
Phase
Detector
PD_D
20
20
20
20
16
Pre_en
M(6:0)
A(3:0)
R(3:0)
6
6
fr
R Counter
fc
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
Pin
Name
Interface
Mode
Type
Description
(44-lead PLCC)
(48-lead QFN)
Serial load enable input. While S_WR is “low”, Sdata can be
serially clocked. Primary register data are transferred to the
secondary register on S_WR or Hop_WR rising edge.
S_WR
Serial
Input
13
14
7
8
D4
Parallel
Direct
Serial
Input
Input
Input
Parallel data bus bit4
M4
M Counter bit4
Sdata
Binary serial data input. Input data entered MSB first.
D5
M5
Parallel
Direct
Input
Input
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit
primary register (E_WR “low”) or the 8-bit enhancement
register (E_WR “high”) on the rising edge of Sclk.
Sclk
Serial
Input
15
16
9
D6
M6
Parallel
Direct
Input
Input
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary
register (FSELS=0) for programming of internal counters while
in Serial Interface Mode.
FSELS
Serial
Input
10
D7
Parallel
Direct
ALL
Input
Input
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, Fin bypasses the
prescaler.
Pre_en
GND
17
18
11
12
Ground.
Selects contents of primary register (FSELP=1) or secondary
register (FSELP=0) for programming of internal counters while
in Parallel Interface Mode.
FSELP
A0
Parallel
Direct
Serial
Input
Input
Input
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”,
Sdata can be serially clocked into the enhancement register
on the rising edge of Sclk.
E_WR
19
13
Enhancement register write. D[7:0] are latched into the
enhancement register on the rising edge of E_WR.
Parallel
Direct
Input
Input
Input
Input
Input
A1
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M
[8:7]) on the rising edge of M2_WR.
M2_WR
A2
Parallel
Direct
20
21
14
15
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or
Parallel Interface Mode (Bmode=0, Smode=0).
Serial,
Parallel
Smode
A3
Direct
ALL
Input
A Counter bit3 (MSB).
16
Bmode
VDD
Selects direct interface mode (Bmode=1).
Same as pin 1.
22
23
Input
17,18
ALL
(Note 1)
M1 write. D[7:0] are latched into the primary register (Pre_en,
24
25
19
20
M1_WR
A_WR
Parallel
Parallel
Input
Input
M[6:0]) on the rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A
[3:0]) on the rising edge of A_WR.
Serial,
Parallel
Hop write. The contents of the primary register are latched
into the secondary register on the rising edge of Hop_WR.
26
27
21
22
Hop_WR
Fin
Input
Input
ALL
Prescaler input from the VCO. 3.0 GHz max frequency.
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
PE3336
Product Specification
Figure 2. Pin Configurations (Top View)
48 47 46 45 44 43 42 41 40 39 38 37
6
5
4
3
2
1
44 43 42 41 40
D0, M0
D1, M1
fc
7
8
39
38
37
36
35
34
33
32
31
30
29
fc
VDD_fc
PD_U
PD_D
VDD
D0, M0
D1, M1
D2, M2
1
2
3
4
5
6
7
8
9
36
35
VDD_fc
D2, M2
9
34 NC
D3, M3
10
11
12
13
14
15
16
17
D3, M3
VDD
PD_U
33
32
31
30
29
28
27
26
25
VDD
PD_D
VDD
Cext
VDD
GND
VDD
S_WR, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
VDD
S_WR, D4, M4
Cext
Sdata, D5, M5
Sclk, D6, M6
Dout
VDDE
Dout
VDD_fp
fp
VDD_fp
fp
FSELS, D7, Pre_en 10
GND
11
GND
FSELP, A0
12
18 19 20 21 22 23 24 25 26 27 28
13 14 15 16 17 18 19 20 21 22 23 24
44-lead PLCC
48-lead QFN
Table 1. Pin Descriptions
Pin No.
Pin No.
Pin
Name
Interface
Mode
Type
Description
(44-lead PLCC)
(48-lead QFN)
Power supply input. Input may range from 2.85 V to 3.15 V.
Bypassing recommended.
1
43
VDD
ALL
(Note 1)
2
3
4
5
6
44
45
46
47
48
R0
Direct
Direct
Direct
Direct
ALL
Input
R Counter bit0 (LSB).
R Counter bit1.
R1
Input
R2
Input
R Counter bit2.
R3
Input
R Counter bit3.
GND
D0
(Note 1)
Input
Ground.
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
7
8
1
2
3
4
M0
D1
Input
Input
M1
D2
Input
Input
Parallel data bus bit2.
M Counter bit2.
9
M2
D3
Input
Input
Parallel data bus bit3.
M Counter bit3.
10
M3
VDD
VDD
Input
11
12
5
6
(Note 1)
(Note 1)
Same as pin 1.
ALL
Same as pin 1.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
Page 3 of 15
PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
Pin
Name
Interface
Mode
Type
Description
(44-lead PLCC)
(48-lead QFN)
Prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected in
series with a 50 Ω resistor directly to the ground plane.
23
24
25
Fin
28
29
30
ALL
ALL
ALL
Input
GND
fp
Ground.
Monitor pin for main divider output. Switching activity can be
disabled through enhancement register programming or by
floating or grounding VDD pin 31.
Output
VDD for fp. Can be left floating or connected to GND to disable
the fp output.
31
26
VDD-fp
ALL
(Note 1)
Data Out. The MSEL signal and the raw prescaler output are
available on Dout through enhancement register
programming.
Serial,
Parallel
32
33
27
28
Dout
VDD
Output
ALL
ALL
(Note 1)
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on
chip, 2 kΩ series resistor. Connecting Cext to an external
capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
34
29
Cext
Output
35
36
37
30
32
33
VDD
ALL
ALL
ALL
(Note 1)
Output
Same as pin 1.
PD_D
PD_U
PD_D is pulse down when fp leads fc.
PD_U is pulse down when fc leads fp.
VDD for fc can be left floating or connected to GND to disable
the fc output.
38
39
35
36
VDD-fc
ALL
ALL
(Note 1)
Output
Monitor pin for reference divider output. Switching activity can
be disabled through enhancement register programming or by
floating or grounding VDD pin 38.
fc
40
41
42
31,37
38,39
40
GND
GND
fr
ALL
ALL
ALL
Ground.
Ground.
Input
Reference frequency input.
Lock detect and open drain logical inversion of CEXT. When
the loop is in lock, LD is high impedance, otherwise LD is a
logic low (“0”).
43
41
LD
ALL
Output
Serial,
Parallel
Enhancement mode. When asserted low (“0”), enhancement
register bits are functional.
42
34
Enh
44
Input
N/A
NC
ALL
No connection.
Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc
outputs.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
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Page 4 of 15
PE3336
Product Specification
Table 2. Absolute Maximum Ratings
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level
Units
Symbol
Parameter/Conditions Min Max Units
VDD
VI
Supply voltage
-0.3
-0.3
4.0
V
V
VESD
ESD voltage (Human Body
1000
V
Voltage on any input
VDD
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
II
DC into any input
DC into any output
Storage temperature
-10
-10
-65
+10
+10
150
mA
mA
°C
STD-883, M3015 C2
IO
Electrostatic Discharge (ESD) Precautions
Tstg
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Table 3. Operating Ratings
Symbol
Parameter/Conditions Min Max Units
VDD
TA
Supply voltage
2.85
-40
3.15
85
V
Operating ambient
°C
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDD
Operational supply current;
VDD = 2.85 to 3.15 V
Prescaler disabled
Prescaler enabled
10
19
mA
mA
26
Digital Inputs: All except fr, R0, Fin, Fin
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
0.7 x VDD
V
V
0.3 x VDD
+70
µA
µA
IIL
VIL = 0, VDD = 3.15 V
-1
Reference Divider input: fr
IIHR High level input current
IILR Low level input current
R0 Input (Pull-up Resistor): R0
IIHRO High level input current
IILRO Low level input current
Counter and phase detector outputs: fc, fp, PD_D, PD_U
VIH = VDD = 3.15 V
+100
+5
µA
µA
VIL = 0, VDD = 3.15 V
-100
VIH = VDD = 3.15 V
µA
µA
VIL = 0, VDD = 3.15 V
-5
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
0.4
V
V
VDD - 0.4
VDD - 0.4
Lock detect outputs: Cext, LD
VOLC
VOHC
VOLLD
Output voltage LOW, Cext
Iout = 100 mA
Iout = -100 mA
Iout = 6 mA
0.4
0.4
V
V
V
Output voltage HIGH, Cext
Output voltage LOW, LD
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Page 5 of 15
PE3336
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 3, 4, 5)
fClk
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
10
MHz
ns
tClkH
tClkL
tDSU
30
30
10
ns
Sdata set-up time after Sclk rising edge, D[7:0] set-up time
to M1_WR, M2_WR, A_WR, E_WR rising edge
ns
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
tPW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
30
30
ns
ns
tCWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
tCE
Sclk falling edge to E_WR transition
30
30
ns
ns
tWRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
tEC
E_WR transition to Sclk rising edge
30
ns
ns
tMDO
MSEL data out delay after Fin rising edge
CL = 12 pf
8
Main Divider (Including Prescaler)
Fin
Operating frequency
Input level range
500
-5
3000
5
MHz
dBm
PFin
External AC coupling
External AC coupling
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
Input level range
50
-5
300
5
MHz
dBm
PFin
Reference Divider
fr
Operating frequency
Reference input power
Input sensitivity
(Note 1)
(Note 2)
-2
100
10
MHz
dBm
VP-P
Pfr
Vfr
Single ended input
External AC coupling
(Note 3)
0.5
Phase Detector
fc
Comparison frequency
(Note 1)
20
MHz
Note 1: Parameter is guaranteed through characterization only and is not tested.
Note 2: Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
Note 3: CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
Page 6 of 15
PE3336
Product Specification
Functional Description
The PE3336 consists of a prescaler, counters, a
phase detector and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired direct to the pins. There
are also various operational and test modes and
lock detect.
Figure 3. Functional Block Diagram
R Counter
(6-bit)
fr
fc
D(7:0)
R(5:0)
M(8:0)
A(3:0)
PD_U
PD_D
Phase
Detector
Control
Logic
Sdata
Control
Pins
Cext
2k
Ω
Modulus
Select
Fin
Fin
10/11
Prescaler
M Counter
(9-bit)
fp
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Page 7 of 15
PE3336
Product Specification
Main Counter Chain
Register Programming
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
Parallel Interface Mode
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three, 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 10. The contents of the primary
register are transferred into a secondary register
on the rising edge of Hop_WR according to the
timing diagram shown in Figure 4. Data are
transferred to the counters as shown in Table 7
on page 10.
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
fp = Fin / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”, the
secondary register contents are utilized.
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
where A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 4. This data provides control bits as
shown in Table 8 on page 10 with bit
functionality enabled by asserting the Enh input
“low”.
When the prescaler is bypassed, the equation
becomes:
Fin = (M + 1) x (fr / (R+1))
(3)
where 1 ≤ M ≤ 511
Serial Interface Mode
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low.
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B19, are clocked serially into the primary
register on the rising edge of Sclk, MSB (B0)
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR or Hop_WR
according to the timing diagram shown in
Figures 4-5. Data are transferred to the counters
as shown in Table 7 on page 10.
Reference Counter
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
(4)
where 0 ≤ R ≤ 63
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
Note that programming R equal to “0” will pass the
reference frequency, fr, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R4 and
R5 are internally forced low (“0”).
While the E_WR input is “high” and the S_WR
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
Page 8 of 15
PE3336
Product Specification
input is “low”, serial input data (Sdata input), B0 to
B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
5. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 with bit
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs
R4 and R5 are internally forced low (“0”).
functionality enabled by asserting the Enh input
“low”.
Table 7. Primary Register Programming
Interface
Mode
Smode
R5
R4
M8
M7
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Enh
Bmode
Pre_en
Parallel
1
0
0
M2_WR rising edge load
M1_WR rising edge load
A_WR rising edge load
D3
B0
D2
B1
D1
B2
D0
B3
D7
B4
D6
B5
D5
B6
D4
B7
D3
B8
D2
B9
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Serial*
Direct
1
1
0
1
1
B10
B11
B12
B13
B14
B15
B16
B17
B18 B19
A1 A0
X
0
0
0
0
Pre_en
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Power
down
Counter
load
MSEL
output
Prescaler
output
Smode
Reserved
Reserved
Reserved
fc, fp OE
Enh
0
Bmode
E_WR rising edge load
Parallel
Serial*
X
X
0
1
D7
B0
D6
B1
D5
B2
D4
D3
D2
B5
D1
B6
D0
B7
0
B3
B4
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
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Page 9 of 15
PE3336
Product Specification
Figure 4. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
[
]
7 : 0
D
tPW
tCWR
tWRC
M1_WR
M2_WR
A_WR
tPW
E_WR
Hop_WR
Figure 5. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
Page 10 of 15
PE3336
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Reserved**
Reserved**
Reserved**
Power down
Counter load
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Bit 5
Bit 6
Bit 7
MSEL output
Prescaler output
fp, fc OE
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“low”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “low”. The width of either pulse is directly
proportional to phase offset between the two input
signals, fp and fc.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency; PD_D
pulses result in a decrease in VCO frequency (for
a positive Kv VCO).
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
The phase detector gain is equal to 2.7 V / 2 π,
which numerically yields 0.43 V / radian.
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
PE3336
Product Specification
Handling Requirements
All surface mount products which do not meet
Level 1 moisture sensitivity requirements are
processed through dry bake and pack procedure.
The necessary data is recorded on the caution
label of each shipment. Both packages for the
PE3335 are moisture sensitivity Level 3.
Level 3 Caution Label
Level and Body temperature defined by:
IPC/JEDEC-J-STD-020
The caution label should contain the following
information for Level 3 devices:
1. Calculated shelf life in sealed bag: 12 months
at <40 °C and <90% relative humidity (RH)
For Dry Bake Procedures, see:
IPC/JEDEC-J-STD-033
2. Peak package body temperature is 225 °C.
Operator must observe ESD precautions per
ESD Control Procedure and Parts Handling and
shipping Procedure.
3. After bag is opened, devices that will be
subjected to reflow solder or other high
temperature process must
a) Be mounted within 168 hours of factory
conditions <30 °C/60% RH, or
b) Be stored at <10% RH
4. Devices require bake, before mounting, if:
a) Humidity Indicator Card is > 10% when
read at 23 ± 5 °C
b) 3a or 3b are not met
5. If baking is required, devices may be baked for
48 hours at 125 +5/-0 °C
Note: If device containers cannot be subjected to
high temperature or shorter bake times are
desired, reference IPC/JEDEC-J-STD-033 for
bake procedure.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
Page 12 of 15
PE3336
Product Specification
Figure 6. Package Drawing
48-lead QFN
7.00
- B -
3.50
INDEX AREA
3.50 X 3.50
0.25
C
- A -
0.10
0.08
C
C
2
SEATING
PLANE
- C -
EXPOSED PAD &
TERMINAL PADS
5.00
5.25
2.50
2.63
13
24
12
25
0.23
0.18
1
48
36
37
EXPOSED PAD
2
DETAIL
A
0.50 TYP
0.23
0.10
C A B
1
1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP.
2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL
AS THE TERMINALS.
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 15
PE3336
Product Specification
Figure 7. Package Drawing
44-lead PLCC
0.690±0.005
0.653±0.003
0.045 X 45°
0.010 X 45°
1*
4*
0.020 MIN.
R0.025
PIN 1
SURFACE
MOUNT
POINT
0.610 ±0.020
2*
3*
A
DETAIL
BOTTOM VIEW
0.027 (WIDTH OF LEAD SLOT)
*EJECT PIN POSITION
0.070
Ø0.040
DIMENSIONS ARE IN INCHES
TOLERANCES ARE ± 0.004
50X 45°
0.180 MAX.
0.070
0.004
0.010
SEE DETAIL A
Table 10. Ordering Information
Order Code
3336-21
Part Marking
PE3336
Description
Package
Shipping Method
PE3336-44PLCC-27A
44-lead PLCC
44-lead PLCC
48-lead QFN
48-lead QFN
Evaluation Kit
Evaluation Kit
27 units / Tube
500 units / T&R
52 units / Tube
2000 units / T&R
1 / Box
3336-22
PE3336
PE3336-44PLCC-500C
3336-23
PE3336
PE3336-48QFN 7x7 mm-52A
PE3336-48QFN 7x7 mm-2000C
PE3336-44PLCC-EVAL KIT
3336-24
PE3336
3336-00
PE3336EK
PE3336EK
3336-01
PE3336-48QFN 7x7 mm-EK
1 / Box
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-02 │ UltraCMOS™ RFIC Solutions
Page 14 of 15
PE3336
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax 858-731-9499
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si,
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Fax: +82-31-728-4305
South Asia Pacific
Space and Defense Products
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Americas:
Tel: 505-881-0438
Fax: 505-881-0443
Fax: +86-21-5836-7652
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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