PE4304 [PSEMI]
75 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC - 2.0 GHz; 75欧姆RF数字衰减器6位， 31.5分贝， DC - 2.0 GHz的
| 型号： | PE4304 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 75 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC - 2.0 GHz |
| 文件： | 总11页 (文件大小：543K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE4304
75 Ω RF Digital Attenuator
6-bit, 31.5 dB, DC – 2.0 GHz
Product Description
Features
• 75 Ω impedance
The PE4304 is a 75-ohm high-linearity, 6-bit RF Digital Step
Attenuator (DSA) covering a 31.5 dB attenuation range in 0.5
dB steps. The PE4304 provides both a parallel (latched or
direct mode) and serial CMOS control interface, operates on a
single 3-volt supply and maintains high attenuation accuracy
over frequency and temperature. It also has a unique control
interface that allows the user to select an initial attenuation
state at power-up. The PE4304 exhibits very low insertion loss
and low power consumption. This functionality is delivered in a
4x4 mm QFN footprint.
• Attenuation: 0.5 dB steps to 31.5 dB
• Low distortion for CATV and multi-carrier
applications
• Flexible parallel and serial programming
interfaces
• Unique power-up state selection
• Positive CMOS control logic
• High attenuation accuracy and linearity
over temperature and frequency
• Very low power consumption
The PE4304 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• Single-supply operation
• Packaged in a 20 lead 4x4 mm QFN
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
4x4 mm -20 Lead QFN
Switched Attenuator Array
RF Input
RF Output
6
3
2
Parallel Control
Serial Control
Control Logic Interface
Power-Up Control
Table 1. Electrical Specifications @ +25 °C, VDD = 3.0 V, Zo = 75 Ω
Parameter
Operation Frequency
Insertion Loss2
Test Conditions
Frequency
Minimum
Typical
Maximum
2000
Units
MHz
dB
DC
-
DC ≤ 1.2 GHz
DC ≤ 1.2 GHz
1.4
-
1.8
Any Bit or Bit
Combination
±(0.15 + 4% of attenuation
setting)
Attenuation Accuracy
1 dB Compression3,4
Input IP31,2,4
-
dB
dBm
dBm
dB
1 MHz ≤ 1.2 GHz
1 MHz ≤ 1.2 GHz
DC ≤ 1.2 GHz
30
-
34
52
13
-
-
-
Two-tone inputs up to
+18 dBm
Return Loss
10
50% control to 0.5 dB
of final value
Switching Speed
-
-
1
µs
Notes: 1. Device Linearity will begin to degrade below 1Mhz
2. Max input rating in Table 2 & Figures on Pages 4 to 6 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50 Ω system.
Document No. 70-0066-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4304
Product Specification
Figure 3. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min Max Units
VDD
Power supply voltage
-0.3
-0.3
-65
-40
4.0
V
V
VI
TST
TOP
PIN
Voltage on any input
VDD
150
85
+
Storage temperature range
Operating temperature
Input power (50 ꢀ)
°C
1
2
3
4
5
15
14
13
12
11
C16
RF1
C8
°C
RF2
20-lead QFN
24
dBm
V
4x4mm
Data
Clock
LE
P/S
Exposed Solder Pad
VESD
ESD voltage (Human Body
500
Vss/GND
GND
Table 4. DC Electrical Specifications
Parameter
Min
Typ
Max
3.3
Units
VDD Power Supply
Voltage
2.7
3.0
V
IDD Power Supply Current
Digital Input High
Digital Input Low
Input Leakage
100
µA
V
Table 2. Pin Descriptions
0.7xVDD
Pin
No.
Pin
Name
Description
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
0.3xVDD
1
V
1
C16
µA
2
RF1
3
Data
Clock
LE
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Exposed Solder Pad Connection
4
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
5
6
VDD
7
PUP1
PUP2
VDD
Power-up selection bit, MSB.
Power-up selection bit, LSB.
Power supply pin.
Electrostatic Discharge (ESD) Precautions
8
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
9
10
11
12
GND
GND
Vss/GND
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
13
14
P/S
RF2
C8
Parallel/Serial mode select.
RF port (Note 1).
Latch-Up Avoidance
15
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
16
C4
17
C2
Switching Frequency
18
GND
C1
19
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
The PE4304 has a maximum 25 kHz switching
rate.
20
C0.5
GND
Paddle
Resistor on Pin 1 & 3
Note 1: Both RF ports must be DC blocked with an external series
capacitor or held at 0 VDC
A 10 kꢀ resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
.
2: Latch Enable (LE) has an internal 100 kꢀ resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kꢀ resistor in series, as close to pin as possible.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 11
PE4304
Product Specification
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4304 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC cable
to supply VDD, GND, and –VDD. If use of the internal
negative voltage generator is desired, then do not
connect –VDD (Black banana plug). If an external –
VDD is desired, then apply -3V.
J1 should be connected to the parallel port of a PC
with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) should be ON with all other
switches off. Using the software, enable or disable
each attenuation setting to the desired combined
attenuation. The software automatically programs
the DSA each time an attenuation state is enabled or
disabled.
To evaluate the Power up options, first disconnect
the parallel ribbon cable from the evaluation board.
The parallel cable must be removed to prevent the
PC parallel port from biasing the control pins to
unknown states. During power up in serial mode (P/
S=1 and LE=0) or in parallel mode with P/S=0 and
LE=1, the default power-up signal attenuation is set
to the value present on the six control bits on the six
parallel data inputs (C0.5 to C16). This allows any
one of the 64 attenuation settings to be specified as
the power-up state.
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
To power up in Parallel mode (P/S=0) with LE=0, the
control bits are automatically set to one of four
possible values. These four values are selected by
the two power-up control bits, PUP1 and PUP2, as
shown in the Parallel PUP Truth Table (Table 6).
Note: Resistors on pins 1 and 3
are required to avoid package
resonance and meet error
specifications over frequency.
Document No. 70-0066-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4304
Product Specification
Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified)
Figure 6. Insertion Loss
Figure 7. Attenuation at Major steps
0
-1
-2
-3
-4
-5
35
30
25
20
15
10
5
31.5dB
16dB
2dB
1dB
0.5dB
8dB
4dB
0
0
400
800
1200
1600
2000
0
400
800
1200
1600
2000
RF Frequency (MHz)
RF Frequency (MHz)
Figure 8. Input Return Loss at Major
Attenuation Steps
Figure 9. Output Return Loss at Major
Attenuation Steps
0
-5
0
-5
-10
-15
-10
-15
-20
-25
-30
-35
-20
8dB
-25
16dB
-30
31.5dB
-35
-40
0
400
800
1200
1600
2000
0
400
800
1200
1600
2000
RF Frequency (MHz)
RF Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions
Page 4 of 11
PE4304
Product Specification
Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified)
Figure 10. Attenuation Error Vs. Frequency
Figure 11. Attenuation Error Vs. Attenuation
Setting
1
0.5
0.25
0
0.5
10MHz
250MHz
0
8dB
510MHz
750MHz
-0.5
-0.25
-0.5
-0.75
-1
16dB
-1
31.5dB
1010MHz
1210MHz
-1.5
-2
0
400
800
1200
1600
2000
0
5
10
15
20
25
30
35
40
RF Frequency (MHz)
AttenuationSetting (dB)
Figure 12. Attenuation Error Vs. Attenuation
Setting
Figure 13. Attenuation Error Vs. Attenuation
Setting
0.6
0.4
0.4
0.2
10MHz, -40C
500MHz, -40C
10MHz, 25C
10MHz, 85C
0.2
0
0
-0.2
-0.4
-0.6
500MHz, 25C
500MHz, 85C
-0.2
-0.4
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
AttenuationSetting (dB)
10Mhz error 85
Document No. 70-0066-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
PE4304
Product Specification
Typical Performance Data @ 25°C, VDD = 3.0 V (unless otherwise specified)
Figure 14. Attenuation Error Vs. Frequency
Figure 15. Input IP3 Vs. Frequency
0.2
0
0.2
0
-0.2
-0.4
-0.2
-0.4
-0.6
-0.8
-1
1000MHz, -40C
1000MHz, 25C
1200MHz, -40C
1200MHz, 25C
-0.6
-0.8
-1
1000MHz, 85C
1200MHz, 85C
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
AttenuationSetting (dB)
AttenuationSetting (dB)
Figure 16. Input 1dB Compression
Figure 17. Input IP3 Vs. Frequency
(Major attenuation states, 50 ꢀ System)
(Major attenuation states, 50 ꢀ System)
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
0
0
400
800
1200
1600
2000
0
400
800
1200
1600
2000
RF Frequency (MHz)
RF Frequency (MHz)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions
Page 6 of 11
PE4304
Product Specification
Programming Options
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4304. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 18 (Serial Interface Timing Diagram) and
Table 8 (AC Characteristics).
The parallel interface timing requirements are
defined by Figure 19 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
Power-up Control Settings
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 19) to latch new attenuation state into
device.
The PE4304 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
When the attenuator powers up in Serial mode (P/
S=1), the six control bits are set to whatever data is
present on the six parallel data inputs (C0.5 to C16).
This allows any one of the 64 attenuation settings to
be specified as the power-up state.
Table 5. Truth Table
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Attenuation
P/S C16 C8
C4
C2
C1 C0.5
State
Reference Loss
0.5 dB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
1 dB
2 dB
Table 6. Parallel PUP Truth Table
4 dB
8 dB
P/S
0
LE
0
PUP2 PUP1
Attenuation State
Reference Loss
8 dB
16 dB
31.5 dB
0
1
0
1
X
0
0
1
1
X
0
0
Note: Not all 64 possible combinations of C0.5-C16 are shown in table
0
0
16 dB
0
0
31 dB
Serial Interface
0
1
Defined by C0.5-C16
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
Note:
Power up with LE=1 provides normal parallel operation
with C0.5-C16, and PUP1 and PUP2 are not active.
Document No. 70-0066-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE4304
Product Specification
Figure 18. Serial Interface Timing Diagram
Table 7. 6-Bit Attenuator Serial Programming
Register Map
LE
B5
B4
B3
B2
B1
B0
Clock
C16
C8
C4
C2
C1
C0.5
↑
↑
Data
MSB
LSB
MSB (first in)
LSB (last in)
tLESUP
tLEPW
tSDSUP
tSDHLD
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C16:C0.5
tLEPW
tPDSUP
tPDHLD
Table 8. Serial Interface AC Characteristics
Table 9. Parallel Interface AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
Symbol
Parameter
Min
Max
Unit
Serial data clock
frequency (Note 1)
fClk
10
MHz
tLEPW
LE minimum pulse width
10
ns
Data set-up time before
rising edge of LE
tClkH
tClkL
tLESUP
tLEPW
Serial clock HIGH time
Serial clock LOW time
30
30
ns
ns
tPDSUP
tPDHLD
10
10
ns
ns
Data hold time after
falling edge of LE
LE set-up time after last
clock falling edge
10
30
10
ns
ns
ns
LE minimum pulse width
Serial data set-up time
before clock rising edge
tSDSUP
Serial data hold time
after clock falling edge
tSDHLD
10
ns
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions
Page 8 of 11
PE4304
Product Specification
Figure 20. Package Drawing
4.00
2.00
INDEX AREA
2.00 X 2.00
- B -
0.25
C
- A -
0.10
0.08
C
C
SEATING
PLANE
- C -
EXPOSED PAD &
TERMINAL PADS
2.00
1.00
0.435
6
10
5
1
11
0.18
15
20
16
EXPOSED PAD
2
DETAIL A
DETAIL A
0.23
0.10
C A B
1
1. Dimension applies to metallized terminal and is measured
between 0.25 and 0.30 from terminal tip.
2. Coplanarity applies to the exposed heat sink slug as well as
the terminals.
3. Dimensions are in millimeters.
Document No. 70-0066-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE4304
Product Specification
Figure 21. Marking Specifications
4304
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of PSC Lot Number
Figure 22. Tape and Reel Drawing
Table 10. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
75 units / Tube
3000 units / T&R
1 / Box
4304-01
4304-02
4304-00
4304-51
4304-52
4304
4304
PE4304-20MLP 4x4mm-75A
PE4304-20MLP 4x4mm-3000C
PE4304-20MLP 4x4mm-EK
20-lead 4x4 mm QFN
20-lead 4x4 mm QFN
Evaluation Kit
PE4304-EK
4304
PE4304G-20MLP 4x4mm-75A
PE4304G-20MLP 4x4mm-3000C
Green 20-lead 4x4 mm QFN
Green 20-lead 4x4 mm QFN
75 units / Tube
3000 units / T&R
4304
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0066-03 │ UltraCMOS™ RFIC Solutions
Page 10 of 11
PE4304
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel 858-731-9400
Fax 858-731-9499
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
South Asia Pacific
Peregrine Semiconductor Europe
Commercial Products:
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Fax : +33-1-47-41-91-73
Space and Defense Products:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
Document No. 70-0066-03 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
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