PE43501_技术文档

Product Specification

PE43501

50 Ω RF Digital Attenuator

5-bit, 7.75 dB, DC-6.0 GHz

Product Description

Features

The PE43501 is a HaRP™-enhanced, high linearity, 5-bit RF

Digital Step Attenuator (DSA). This highly versatile DSA

covers a 7.75 dB attenuation range in 0.25 dB steps. The

Peregrine 50Ω RF DSA provides a serial-addressable CMOS

control interface. It maintains high attenuation accuracy over

frequency and temperature and exhibits very low insertion loss

and low power consumption. Performance does not change

with Vdd due to on-board regulator. This next generation

Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint.

• HaRP™-enhanced UltraCMOS™ device

• Attenuation: 0.25 dB steps to 7.75 dB

• High Linearity: Typical +58 dBm IP3

• Excellent low-frequency performance

• 3.3 V or 5.0 V Power Supply Voltage

• Fast switch settling time

• Programming Modes:

The PE43501 is manufactured on Peregrine’s UltraCMOS™

process, a patented variation of silicon-on-insulator (SOI)

technology on a sapphire substrate, offering the performance

of GaAs with the economy and integration of conventional

CMOS.

• Direct Parallel

• Latched Parallel

• Serial-Addressable: Program up to

eight addresses 000 - 111

• High-attenuation state @ power-up (PUP)

• CMOS Compatible

Figure 1. Package Type

• No DC blocking capacitors required

• Packaged in a 32-lead 5x5x0.85 mm QFN

32-lead 5x5x0.85 mm QFN Package

Figure 2. Functional Schematic Diagram

Switched Attenuator Array

RF Output

RF Input

5

Parallel Control

Serial In

CLK

Control Logic Interface

LE

A0

A1

A2

P/S

Document No. 70-0251-03 │ www.psemi.com

Page 1 of 13

PE43501

Product Specification

Table 1. Electrical Specifications @ +25°C, V_DD= 3.3 V or 5.0 V

Parameter

Test Conditions

Frequency

Min

Typical

Max

Units

Frequency Range

Attenuation Range

Insertion Loss

DC – 6

0 – 7.75

2.3

GHz

dB

0.25 dB Step

DC ≤ 6 GHz

2.8

dB

±(0.15+4%)

+0.2+4%

+0.3+4%

-0.2 - 4%

0 dB - 7.75 dB Attenuation settings

0dB to 3.5 dB Attenuation Settings

3.75 dB to 7.75 dB Attenuation Settings

0dB to 7.75dB Attenuation Settings

DC < 4 GHz

dB

4 GHz ≤ 6 GHz

Attenuation Error

Return Loss

DC - 6 GHz

20 MHz - 6 GHz

1 MHz

18

9

dB

deg

dBm

mVpp

ns

Relative Phase

P1dB

All States

Input

30

32

IIP3

Two tones at +18 dBm, 20 MHz spacing

58

Typical Spurious Value

Video Feed Through

Switching Time

RF Trise/Tfall

-110

10

50% CTRL to 10% / 90% RF

10% / 90% RF

650

400

ns

RF settled to within 0.05 dB of final value

RBW = 5 MHz, Averaging ON.

Settling Time

4

µs

Performance Plots

Figure 3. 0.25 dB Step Error vs. Frequency*

Figure 4. 0.25dB Attenuation vs. Attenuation

State

Attenuation

200 MHz

900 MHz

1800 MHz

2200 MHz

3000 MHz

5400 MHz

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

8

7

6

5

4

3

2

1

0

900 MHz

1800 MHz

2200 MHz

3000 MHz

5400 MHz

5800 MHz

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

Attenuation Setting (dB.)

Attenuation State

*Monotonicity is held so long as step-error does not cross zero.

Figure 5. 0.25 dB Major State Bit Error

Figure 6. 0.25 dB Attenuation Error vs. Frequency

200 MHz

3000 MHz

900 MHz

4000 MHz

1800 MHz

6000 MHz

2200 MHZ

0.25dB State

2dB State

0.5 dB State

4dB State

1dB State

7.75dB State

1.00

0.75

0.50

0.25

0.00

-0.25

-0.50

-0.75

-1.00

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

0

1

2

3

4

5

6

7

8

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Attenuation Setting (dB.)

Frequency (GHz)

Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions

Page 2 of 13

PE43501

Product Specification

Figure 7. Insertion Loss vs. Temperature

Figure 8. Input Return Loss vs. Attenuation:

T = +25C

0dB

0.25dB

0.5dB

1dB

-40C

+25C

+85C

2dB

4dB

7.75dB

0

-0.5

-1

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

-1.5

-2

-2.5

-3

-3.5

-4

-4.5

-5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

0

1

2

3

4

5

6

7

8

9

Frequency (GHz)

Frequency(GHz.)

Figure 10. Input Return Loss vs. Temperature:

7.75 dB State

Figure 9. Output Return Loss vs. Attenuation:

T = +25C

0dB

0.25dB

0.5dB

1dB

2dB

4dB

7.75dB

-40C

25C

85C

0

-10

-20

-30

-40

-50

-60

0

-10

-20

-30

-40

-50

-60

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

Frequency (GHz.)

Figure 12. Relative Phase vs. Frequency

Figure 11. Output Return Loss vs. Temperature:

7.75 dB State

-40C

25C

85C

0dB

0.25dB

0.5dB

1dB

2dB

4dB

7.75dB

0

-10

-20

-30

-40

-50

-60

-70

16

14

12

10

8

6

4

2

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

9

Frequency (GHz.)

Frequency(GHz.)

Document No. 70-0251-03 │ www.psemi.com

Page 3 of 13

PE43501

Product Specification

Figure 13. Relative Phase vs. Temperature:

7.75 dB State

Figure 14. Attenuation Error vs. Attenuation

Setting: 900 MHz

900 MHz

1800 MHz

3000 MHz

900 MHz @ T=+25 C

900 MHz@ T= -40C

900 MHz@ T= +85C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0.50

0.30

0.10

-0.10

-0.30

-0.50

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

-40

-20

0

20

40

60

80

Temperature (Deg. C.)

Attenuation Setting (dB.)

Figure 16. Attenuation Error vs. Attenuation

Setting: 3000 MHz

Figure 15. Attenuation Error vs. Attenuation

Setting: 1800 MHz

1800 MHz @ T= +25C

1800 MHz @ T= -40C

1800 MHz @ T= +85C

3000 MHz @ T= +25C

3000 MHz @ T= -40C

3000 MHz @ T= +85C

0.50

0.30

0.50

0.30

0.10

-0.10

-0.30

-0.50

-0.10

-0.30

-0.50

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Attenuation Setting (dB.)

Figure 17. Input IP3 vs. Frequency

0dB

0.25dB

0.5dB

1dB

2dB

4dB

70

65

60

55

50

45

40

35

30

0

1000

2000

3000

4000

5000

6000

7000

Frequency(MHz.)

Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions

Page 4 of 13

PE43501

Product Specification

Figure 18. Pin Configuration (Top View)

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS™ device, observe the

same precautions that you would use with other ESD-

sensitive devices. Although this device contains

circuitry to protect it from damage due to ESD,

precautions should be taken to avoid exceeding the

specified rating.

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

NC

V_DD

CLK

LE

P/S

A1

Latch-Up Avoidance

A0

A2

Exposed

Solder pad

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

GND

RF1

GND

RF2

GND

Moisture Sensitivity Level

The Moisture Sensitivity Level rating for the PE43501 in

the 32-lead 5x5 QFN package is MSL1.

9

10 11 12 13 14 15 16

Switching Frequency

The PE43501 has a maximum 25 kHz switching rate.

Switching rate is defined to be the speed at which the

DSA can be toggled across attenuation states.

Table 2. Pin Descriptions

Pin No.

Pin Name

Description

Exposed Solder Pad Connection

1

2

3

4

N/C

V_DD

P/S

A0

No Connect

The exposed solder pad on the bottom of the package

must be grounded for proper device operation.

Power supply pin

Serial/Parallel mode select

A0 connection

5, 6, 8-17, 19,

20, 26, 27

GND

Ground

7

18

RF1

RF2

A2

RF1 port

RF2 port

21

A2 connection

22

A1

A1 connection

23

LE

Latch Enable input

24

CLK

SI

Serial interface clock input

Serial Interface input

Attenuation control bit, 4 dB

Attenuation control bit, 2 dB

Attenuation control bit, 1 dB

Attenuation control bit, 0.5 dB

Attenuation control bit, 0.25 dB

Ground for proper operation

25

28

C4

29

C2

30

C1

31

C0.5

C0.25

GND

32

Paddle

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Page 5 of 13

PE43501

Product Specification

Table 3. Operating Ranges

Table 4. Absolute Maximum Ratings

Parameter

Min

Typ

3.3

5.0

70

Max

Units

V

Symbol

V_DD

Parameter/Conditions

Power supply voltage

Min

-0.3

Max

6.0

Units

V

_DDPower Supply Voltage

3.0

V

5.5

350

5.5

V

V_I

Voltage on any Digital input

5.8

Input power (50Ω)

1 Hz ≤ 20 MHz

I_DDPower Supply Current

Digital Input High

µA

V

P_IN

T_ST

See fig. 19 dBm

20 MHz ≤ 4 GHz

+23

dBm

2.6

Storage temperature range

-65

150

°C

P

_INInput power (50Ω):

1 Hz ≤ 20 MHz

20 MHz ≤ 4 GHz

See fig. 19

dBm

+23

ESD voltage (HBM)¹

ESD voltage (Machine Model)

500

100

V

V_ESD

T

_OPOperating temperature

-40

0

25

85

°C

range

Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)

Digital Input Low

1

V

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be restricted to

the limits in the Operating Ranges table. Operation

between operating range maximum and absolute

maximum for extended periods may reduce reliability.

Digital Input Leakage¹

15

µA

Note 1. Input leakage current per Control pin

Figure 19. Maximum Power Handling Capability: Z₀= 50 Ω

30.0

25.0

20.0

15.0

10.0

5.0

0.0

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

Hz

Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions

Page 6 of 13

PE43501

Product Specification

Table 5. Control Voltage

Table 8. Address Word Truth Table

Address Word

State

Bias Condition

Address

Setting

A7

(MSB)

Low

0 to +1.0 Vdc at 2 µA (typ)

A6

A5

A4

A3

A2

A1

A0

X

L

H

L

000

001

010

011

100

101

110

111

High

+2.6 to +5 Vdc at 10 µA (typ)

L

H

L

H

L

H

Table 6. Latch and Clock Specifications

L

H

L

Shift Clock

Latch Enable

Function

H

X

↑

Shift Register Clocked

H

Contents of shift register

transferred to attenuator core

↑

X

Table 7. Parallel Truth Table

Table 9. Serial Attenuation Word Truth Table

Attenuation Word

Attenuation

Setting

RF1-RF2

Parallel Control Setting

Attenuation Setting

RF1-RF2

D0

(LSB)

D6

D7

D5

D4

D3

D2

D1

D4

D3

D2

D1

D0

L

H

L

Reference I.L.

0.25 dB

0.5 dB

1 dB

X

L

H

L

Reference I.L.

0.25 dB

0.5 dB

1 dB

L

H

L

H

L

H

L

H

L

H

L

2 dB

L

H

L

2 dB

H

L

4 dB

H

L

4 dB

H

7.75 dB

H

7.75 dB

Table 10. Serial-Addressable Register Map

Bits can either be set to logic high or logic low

MSB (last in)

LSB (first in)

Q15

Q14

A6

Q13

Q12

Q11

Q10

Q9

Q8

Q7

Q6

Q5

Q4

D4

Q3

D3

Q2

D2

Q1

Q0

A7

A5

A4

A3

A2

A1

A0

D7

D6

D5

D1

D0

Address Word

Attenuation Word

Attenuation Word is derived directly from the attenuation value. For example, to program the 3.75 dB state at

address 3:

Address Word: XXXXX011

Attenuation Word: Multiply by 4 and convert to binary → 4 * 3.75 dB → 15 → 0001111

Serial Input: XXXXX011X0001111

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Page 7 of 13

PE43501

Product Specification

Programming Options

Parallel/Serial Selection

The serial-addressable interface is controlled

Either a parallel or serial interface can be used to

control the PE43501. The P/S bit provides this

selection, with P/S=LOW selecting the parallel

interface and P/S=HIGH selecting the serial

interface.

using three CMOS-compatible signals: Serial-In

(SI), Clock (CLK), and Latch Enable (LE). The SI

and CLK inputs allow data to be serially entered

into the shift register. Serial data is clocked in

LSB first, beginning with the attenuation word.

Parallel Mode Interface

The shift register must be loaded while LE is held

LOW to prevent the attenuator value from

The parallel interface consists of five CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 7.

changing as data is entered. The LE input should

then be toggled HIGH and brought LOW again,

latching the new data into the DSA. Address word

and attenuation word truth tables are listed in

Table 8 & Table 9, respectively. A programming

example of the Serial-Addressable register is

illustrated in Table 10. The serial-addressable

timing diagram is illustrated in Fig. 20.

The parallel interface timing requirements are

defined by Fig. 21 (Parallel Interface Timing

Diagram), Table 12 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched-parallel programming the Latch

Enable (LE) should be held LOW while changing

attenuation state control values, then pulse LE

HIGH to LOW (per Fig. 21) to latch new

attenuation state into device.

Power-up Control Settings

The PE43501 will always initialize to the maximum

attenuation setting (7.75 dB) on power-up for both

the serial-addressable and latched-parallel modes

of operation and will remain in this setting until the

user latches in the next programming word. In

direct-parallel mode, the DSA can be preset to

any state within the 7.75 dB range by pre-setting

the parallel control pins prior to power-up. In this

mode, there is a 400-µs delay between the time

the DSA is powered-up to the time the desired

state is set. During this power-up delay, the

device attenuates to the maximum attenuation

setting (7.75 dB) before defaulting to the user

defined state. If the control pins are left floating in

this mode during power-up, the device will default

to the minimum attenuation setting (insertion loss

state).

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

attenuation state control values will change device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

Serial-Addressable Interface

The serial interface is a 16-bit serial-in, parallel-

out shift register buffered by a transparent latch.

The 16-bits make up two words comprised of 8-

bits each. The first word is the Attenuation Word,

which controls the state of the DSA. The second

word is the Address Word, which is compared to

the static (or programmed) logical states of the

A0, A1 and A2 digital inputs. If there is an address

match, the DSA changes state; otherwise its

current state will remain unchanged. Fig. 20

illustrates a example timing diagram for

programming a state. It is recommended that all

parallel control inputs be grounded when the DSA

is used in serial mode.

Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions

Page 8 of 13

PE43501

Product Specification

Figure 20. Serial-Addressable Timing Diagram

Bits can either be set to logic high or logic low

DI[6:0]

ADD[2:0]

P/S

T_DISU

VALID

T_ASU

T_DIH

T_AH

T_PSSU

T_PSH

D[0]

D[1]

T_CLKL

D[2]

D[3]

D[4]

D[5]

D[6]

A[0]

A[1]

A[2]

SI

T_SISU

T_SIH

CLK

LE

T_CLKH

T_LESU

T_LEPW

T_PD

VALID

DO[6:0]

Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram

P/S

T_PSSU

T_PSH

VALID

DI[6:0]

T_DISU

T_DIH

LE

T_LEPW

VALID

T_PD

DO[6:0]

T_DIPD

Table 11. Serial Interface AC Characteristics

V_DD= 3.3 or 5.0 V, -40° C < T_A< 85° C, unless otherwise specified

Table 12. Parallel and Direct Interface AC

Characteristics

V_DD= 3.3 or 5.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Min Max Unit

F_CLK

T_CLKH

T_CLKL

Serial clock frequency

Serial clock HIGH time

Serial clock LOW time

-

10

-

MHz

ns

Symbol

Parameter

Min Max Unit

30

Latch Enable minimum

pulse width

T_LEPW

30

-

ns

-

ns

Last serial clock rising edge

setup time to Latch Enable

rising edge

T_DISU

T_DIH

T_PSSU

T_PSIH

Parallel data setup time

Parallel data hold time

Parallel/Serial setup time

Parallel/Serial hold time

100

-

ns

T_LESU

10

-

ns

T_LEPW

T_SISU

T_SIH

Latch Enable min. pulse width

Serial data setup time

Serial data hold time

30

10

-

ns

10

-

Digital register delay

(internal)

T_DISU

T_DIH

Parallel data setup time

Parallel data hold time

Address setup time

100

-

T_PD

-

10

5

ns

-

Digital register delay

(internal, direct mode only)

T_DIPD

T_ASU

T_AH

-

Address hold time

-

T_PSSU

T_PSH

T_PD

Parallel/Serial setup time

Parallel/Serial hold time

Digital register delay (internal)

-

10

Note: f_Clkis verified during the functional pattern test. Serial

programming sections of the functional pattern are clocked

at10 MHz to verify fclk specification.

Document No. 70-0251-03 │ www.psemi.com

Page 9 of 13

PE43501

Product Specification

Figure 22. Evaluation Board Layout

Peregrine Specification 101-0312

Evaluation Kit

The Digital Attenuator Evaluation Kit board was

designed to ease customer evaluation of the

PE43501 Digital Step Attenuator.

Direct-Parallel Programming Procedure

For automated direct-parallel programming,

connect the test harness provided with the EVK

from the parallel port of the PC to the J1 & Serial

header pin and set the D0-D4 SP3T switches to

the ‘MIDDLE’ toggle position. Position the

Parallel/Serial (P/S) select switch to the Parallel

(or left) position. The evaluation software is

written to operate the DSA in either Parallel or

Serial-Addressable Mode. Ensure that the

software is set to program in Direct-Parallel mode.

Using the software, enable or disable each setting

to the desired attenuation state. The software

automatically programs the DSA each time an

attenuation state is enabled or disabled.

Note: Reference Fig. 23 for Evaluation Board Schematic

the LE pin on the Serial header must be logic low

as the parallel bits are applied. The user must

then pulse LE from 0V to V_DDand back to 0V to

latch the programming word into the DSA. LE

must be logic low prior to programming the next

word.

For manual direct-parallel programming,

disconnect the test harness provided with the EVK

from the J1 and Serial header pins. Position the

Parallel/Serial (P/S) select switch to the Parallel

(or left) position. The LE pin on the Serial header

must be tied to logic high. Switches D0-D4 are

SP3T switches which enable the user to manually

program the parallel bits. When any input D0-D4

is toggled ‘UP’, logic high is presented to the

parallel input. When toggled ‘DOWN’, logic low is

presented to the parallel input. Setting D0-D4 to

the ‘MIDDLE’ toggle position presents an OPEN,

which forces an on-chip logic low. Table 7 depicts

the parallel programming truth table and Fig. 21

illustrates the parallel programming timing

diagram.

Serial-Addressable Programming Procedure

Position the Parallel/Serial (P/S) select switch to

the Serial (or right) position. Prior to

programming, the user must define an address

setting using the ADD header pin. Jump the

middle pins on the ADD header A0-A2 (or lower)

row of pins to set logic high, or jump the middle

pins to the upper row of pins to set logic low. If

the ADD pins are left open, then 000 become the

default address. The evaluation software is

written to operate the DSA in either Parallel or

Serial-Addressable Mode. Ensure that the

software is set to program in Serial-Addressable

mode. Using the software, enable or disable each

setting to the desired attenuation state. The

software automatically programs the DSA each

time an attenuation state is enabled or disabled.

Latched-Parallel Programming Procedure

For automated latched-parallel programming, the

procedure is identical to the direct-parallel

method. The user only must ensure that Latched-

Parallel is selected in the software.

For manual latched-parallel programming, the

procedure is identical to direct-parallel except now

Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions

Page 10 of 13

PE43501

Product Specification

Figure 23. Evaluation Board Schematic

Peregrine Specification 102-0381

VDD

_

D5

D4

D6

D0

D1

D3

D2

P/S

J1

HEADER 14

D0

2

4

6

1

3

5

7

9

11

13

2

4

6

8

10

12

14

1

3

5

7

9

11

13

D1

D2

D3

D4

D5

D6

SERIAL

HEADER

4

8

CLK

SI

LE

1

2

3

4

CLOCK

SI

LE

10

12

14

GND

VDD

C5

100pF

C3

C1

100pF

ADD

A0_2

A1_2

A2_2

A2_1

A1_1

A0_1

100pF

A0 VDD

A1 VDD

A2 VDD

C6

C4

C2

C0

100pF

HEADER3X3

100pF

VDD

J3

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CLK

LE

J2

GND

VDD

CON2

VDD

VSS

1

2

1

2

_

A1

A2

P/S

A0

C9

0.1µF

PS

A1

R1

OHM

C10

C8

100pF

C13

C14

CON2

U1

0

C12

C11

A0

A2

100pF

PE43XOX DSA 50 OHM 5X5 MLPQ32

R2

100pf

0.1uF

GND

VSS

GND

J4

SMA

J5

SMA

0

OHM

Z=50 Ohm

1

RF1

RF2

De-embeding trace

Z=50 Ohm

J6

SMA

J7

SMA

GND

1

Note: Capacitors C1-C8, C13, & C14 may be omitted. Pin 26 & 27 are ground.

Figure 24. Package Drawing

QFN 5x5 mm

0.900

MAX

NOM

MIN

0.850

A

0.800

Document No. 70-0251-03 │ www.psemi.com

Page 11 of 13

PE43501

Product Specification

Figure 24. Tape and Reel Drawing

Tape Feed Direction

Pin 1

Top of

Device

Device Orientation in Tape

Figure 25. Marking Specifications

43501

YYWW

ZZZZZ

YYWW = Date Code

ZZZZZ = Last five digits of Lot Number

Table 13. Ordering Information

Order Code Part Marking

Description

Package

Shipping Method

Bulk or tape cut from reel

3000 units / T&R

PE43501MLI

PE43501MLI-Z

EK43501-01

43501

PE43501 G - 32QFN 5x5mm-75A

PE43501 G – 32QFN 5x5mm-3000C

PE43501 – 32QFN 5x5mm-EK

Green 32-lead 5x5mm QFN

Evaluation Kit

1 / Box

Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions

Page 12 of 13

PE43501

Product Specification

Sales Offices

The Americas

Peregrine Semiconductor Corporation

Peregrine Semiconductor, Asia Pacific (APAC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

9380 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Peregrine Semiconductor, Korea

#B-2607, Kolon Tripolis, 210

Geumgok-dong, Bundang-gu, Seongnam-si

Gyeonggi-do, 463-943 South Korea

Tel: +82-31-728-3939

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

Fax: +82-31-728-3940

13-15 rue des Quatre Vents

F-92380 Garches, France

Tel: +33-1-4741-9173

Fax : +33-1-4741-9173

Peregrine Semiconductor K.K., Japan

Teikoku Hotel Tower 10B-6

1-1-1 Uchisaiwai-cho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

High-Reliability and Defense Products

Americas

San Diego, CA, USA

Phone: 858-731-9475

Fax: 848-731-9499

Europe/Asia-Pacific

Aix-En-Provence Cedex 3, France

Phone: +33-4-4239-3361

Fax: +33-4-4239-7227

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The information in this data sheet is believed to be reliable.

However, Peregrine assumes no liability for the use of this

information. Use shall be entirely at the user’s own risk.

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Preliminary Specification

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks

of Peregrine Semiconductor Corp.

Document No. 70-0251-03 │ www.psemi.com

Page 13 of 13


型号：	PE43501
厂家：	Peregrine Semiconductor
描述：	RF Digital Attenuator 5-bit, 7.75dB, DC-6.0 GHz 射频数字衰减器5位， 7.75分贝， DC- 6.0 GHz的射频衰减器
文件：	总13页 (文件大小：378K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PE43501 [PSEMI]

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