PE43702MLI-Z [PSEMI]
50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-4.0 GHz; 50 Ω RF数字衰减器7位， 31.75分贝， DC- 4.0 GHz的
| 型号： | PE43702MLI-Z |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-4.0 GHz |
| 文件： | 总11页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE43702
50 Ω RF Digital Attenuator
7-bit, 31.75 dB, DC-4.0 GHz
Product Description
Features
The PE43702 is a HaRP™-enhanced, high linearity, 7-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 31.75 dB attenuation range in 0.25 dB steps. The
Peregrine 50Ω RF DSA provides both a serial and parallel
CMOS control interface. It maintains high attenuation accuracy
over frequency and temperature and exhibits very low insertion
loss and low power consumption. Performance does not
change with Vdd due to on-board regulator. This next
generation Peregrine DSA is available in a 4x4 mm 24 lead
QFN footprint.
• HaRP™-enhanced UltraCMOS™ device
• Attenuation: 0.25 dB steps to 31.75 dB
• High Linearity: Typical +57 dBm IIP3
• Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast switch settling time
• Programming Modes:
• Direct Parallel
• Latched Parallel
• Serial
The PE43702 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
• No DC blocking capacitors required
• Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 1. Package Type
24-lead 4x4x0.85 mm QFN Package
Figure 2. Functional Schematic Diagram
RF Output
RF Input
7
Parallel Control
Serial In
Control Logic Interface
CLK
LE
P/S
Document No. 70-0244-03 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE43702
Product Specification
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V
Parameter
Frequency Range
Attenuation Range
Insertion Loss
Test Conditions
Frequency
Min
Typical
DC – 4
0 – 31.75
2.0
Max
Units
GHz
dB
0.25 dB Step
DC - 4 GHz
2.5
dB
±(0.2 + 3%)
±(0.3 + 4%)
0 dB - 7.75 dB Attenuation settings
8 dB - 31.75 dB Attenuation settings
DC - 4 GHz
DC - 4 GHz
dB
dB
Attenuation Error
Return Loss
DC - 4 GHz
DC - 4 GHz
20 MHz - 4 GHz
20 MHz - 4 GHz
1MHz
18
44
dB
deg
Relative Phase
P1dB
All States
Input
30
32
dBm
dBm
dBm
mVpp
IIP3
Two tones at +18 dBm, 20 MHz spacing
57
Typical Spurious Value
Video Feed Through
-110
10
Switching Time
RF Trise/Tfall
50% DC CTRL to 10% / 90% RF
10% / 90% RF
650
400
ns
ns
RF settled to within 0.05 dB of final value.
RBW = 5 MHz, Averaging ON.
Settling Time
4
µs
Performance Plots
Figure 3. 0.25dB Step Error vs. Frequency*
Figure 4. 0.25dB Attenuation vs. Attenuation State
200MHz
900MHz
1800MHz
4000MHz
2200MHz
3000MHz
35
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
900 MHz
2200 MHz
30
3800 MHz
25
20
15
10
5
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
0
5
10
15
20
25
30
35
Attenuation Setting (dB.)
Attenuation State
*Monotonicity is held so long as Step-Error does not cross zero
Figure 5. 0.25dB Major State Bit Error
Figure 6. 0.25dB Attenuation Error vs. Frequency
0.25dB State
4dB State
0.5 dB State
8dB State
1dB State
16dB State
2dB State
31.75dB State
200MHz
2200MHz
3000MHz
4000MHz
2
1.5
1
2.00
1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
0.5
0
-0.5
-1
-1.5
-2
0.0
1.0
2.0
Frequency (GHz)
3.0
4.0
0
5
10
15
20
25
30
35
Attenuation Setting (dB.)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0244-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 11
PE43702
Product Specification
Figure 7. Insertion Loss vs. Temperature
Figure 8. Input Return Loss vs. Attenuation
@ T = +25C
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
2dB
-40C
+25C
+85C
31.75dB
0
-0.5
-1
0
-5
-10
-15
-20
-25
-30
-35
-40
-1.5
-2
-2.5
-3
-3.5
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Frequency (GHz.)
Frequency (GHz.)
Figure 10. Relative Phase vs. Frequency
Figure 9. Output Return Loss vs. Attenuation
@ T = +25C
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
2dB
31.75dB
0
-5
140
120
100
80
-10
-15
-20
-25
-30
-35
-40
-45
60
40
20
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
Frequency (GHz.)
Frequency(GHz.)
Figure 12. Input IP3 vs. Frequency
Figure 11. Attenuation Error vs. Temperature
@ 4 GHz
0dB
4dB
0.25dB
8dB
0.5dB
16dB
1dB
31.75dB
2dB
-40C
+25C
+85C
2
1.5
1
70
65
60
55
50
45
40
35
30
0.5
0
-0.5
-1
-1.5
-2
0
5
10
15
20
25
30
35
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Attenuation Setting (dB.)
Frequency (MHz)
Document No. 70-0244-03 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE43702
Product Specification
Figure 13. Pin Configuration (Top View)
Table 3. Operating Ranges
Parameter
Min
Typ
3.3
5.0
50
Max
Units
VDD Power Supply Voltage
3.0
V
V
VDD Power Supply Voltage
IDD Power Supply Current
Digital Input High
5.5
350
5.5
1
C0.25
VDD
18
17
16
SI
µA
V
2
3
4
CLK
LE
Exposed
Solder
Pad
2.6
P/S
PIN Input power (50Ω):
15 GND
14 RF2
GND
RF1
1 Hz ≤ 20 MHz
Fig. 14 dBm
5
6
20 MHz ≤ 4 GHz
+23
dBm
13
GND
GND
T
OP Operating temperature range
-40
0
25
85
°C
Digital Input Low
1
V
Digital Input Leakage1
15
µA
Note 1. Input leakage current per Control pin
Table 2. Pin Descriptions
Table 4. Absolute Maximum Ratings
Pin No. Pin Name
Description
Symbol
VDD
Parameter/Conditions
Power supply voltage
Min
-0.3
-0.3
-65
Max
6.0
Units
V
1
2
C0.25
VDD
Attenuation control bit, 0.25 dB
Power supply pin
VI
Voltage on any Digital input
Storage temperature range
Input power (50Ω)
5.8
V
3
P/S
GND
RF1
GND
RF2
GND
LE
Serial/Parallel mode select
Ground
TST
150
°C
4
5
RF1 port
PIN
1 Hz ≤ 20 MHz
20 MHz ≤ 4 GHz
ESD voltage (HBM)1
ESD voltage (Machine Model)
Fig. 14 dBm
+23
6 - 13
14
Ground
dBm
RF2 port
500
100
V
V
VESD
15
Ground
16
Latch Enable input
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
17
CLK
SI
Serial interface clock input
Serial Interface input
Attenuation control bit, 16 dB
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Attenuation control bit, 1 dB
Attenuation control bit, 0.5 dB
Ground for proper operation
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
18
19
C16
C8
20
21
C4
22
C2
23
C1
Figure 14. Maximum Power Handling Capability
24
C0.5
GND
30.0
25.0
20.0
15.0
10.0
5.0
Paddle
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43702 in
the 24-lead 4x4 QFN package is MSL1.
0.0
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
1.0E+09
Hz
Switching Frequency
Electrostatic Discharge (ESD) Precautions
The PE43702 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0244-03 │ UltraCMOS™ RFIC Solutions
Page 4 of 11
PE43702
Product Specification
Table 5. Control Voltage
Table 9. Serial Attenuation Word Truth Table
State
Bias Condition
Attenuation Word
Attenuation
Setting
RF1-RF2
0 to +1.0 Vdc at 2 µA (typ)
Low
D0
(LSB)
D6
D7
D5
D4
D3
D2
D1
+2.6 to +5 Vdc at 10 µA (typ)
High
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
Reference I.L.
0.25 dB
0.5 dB
1 dB
Table 6. Latch and Clock Specifications
Shift Clock
Latch Enable
Function
2 dB
0
↑
Shift Register Clocked
4 dB
Contents of shift register
transferred to attenuator core
↑
X
8 dB
16 dB
Table 7. Parallel Truth Table
31.75 dB
Parallel Control Setting
Attenuation
Setting
RF1-RF2
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.75 dB
Table 8. Serial Register Map
MSB (last in)
LSB (first in)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Bits can either be set to logic high or logic low
D7
D6
D5
D4
D3
D2
D1
D0
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:
Attenuation Word: Multiply by 4 and convert to binary → 4 * 12.5 dB → 50 → X0110010
Serial Input: X0110010
Document No. 70-0244-03 │ www.psemi.com
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Page 5 of 11
PE43702
Product Specification
Programming Options
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from
changing as data is entered. The LE input should
then be toggled HIGH and brought LOW again,
latching the new data into the DSA. Attenuation
Word truth table is listed in Table 9. A
programming example of the serial register is
illustrated in Table 8. The serial timing diagram is
illustrated in Fig. 15. It is recommended that all
parallel pins be grounded when the DSA is used
in serial mode.
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE43702. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of seven CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 7.
Power-up Control Settings
The parallel interface timing requirements are
defined by Fig. 16 (Parallel Interface Timing
Diagram), Table 11 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
The PE43702 will always initialize to the maximum
attenuation setting (31.75 dB) on power-up for
both the serial and latched-parallel modes of
operation and will remain in this setting until the
user latches in the next programming word. In
direct-parallel mode, the DSA can be preset to
any state within the 31.75 dB range by pre-setting
the parallel control pins prior to power-up. In this
mode, there is a 400-µs delay between the time
the DSA is powered-up to the time the desired
state is set. During this power-up delay, the
device attenuates to the maximum attenuation
setting (31.75 dB) before defaulting to the user
defined state. If the control pins are left floating in
this mode during power-up, the device will default
to the minimum attenuation setting (insertion loss
state).
For latched-parallel programming the Latch
Enable (LE) should be held LOW while changing
attenuation state control values, then pulse LE
HIGH to LOW (per Fig. 16) to latch new
attenuation state into device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Serial Interface
The serial interface is a 8-bit serial-in, parallel-out
shift register buffered by a transparent latch. The
8-bits make up the Attenuation Word that controls
the DSA. Fig. 15 illustrates a example timing
diagram for programming a state.
The serial-interface is controlled using three
CMOS-compatible signals: Serial-In (SI), Clock
(CLK), and Latch Enable (LE). The SI and CLK
inputs allow data to be serially entered into the
shift register. Serial data is clocked in LSB first.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0244-03 │ UltraCMOS™ RFIC Solutions
Page 6 of 11
PE43702
Product Specification
Figure 15. Serial Timing Diagram
Bits can either be set to logic high or logic low
DI[6:0]
P/S
TDISU
TDIH
TPSSU
TPSH
D[0]
TCLKL
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
SI
TSISU
TSIH
CLK
LE
TCLKH
TLESU
TLEPW
TPD
VALID
DO[6:0]
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
TPSSU
TPSH
VALID
DI[6:0]
TDISU
TDIH
LE
TLEPW
VALID
TPD
DO[6:0]
TDIPD
Table 10. Serial Interface AC Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Table 11. Parallel and Direct Interface AC
Characteristics
VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Min Max Unit
FCLK
TCLKH
TCLKL
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
-
10
-
MHz
ns
Symbol
Parameter
Min Max Unit
30
30
Latch Enable minimum
pulse width
TLEPW
30
-
ns
-
ns
Last serial clock rising edge
setup time to Latch Enable
rising edge
TDISU
TDIH
TPSSU
TPSIH
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
100
100
100
100
-
-
-
-
ns
ns
ns
ns
TLESU
10
-
ns
TLEPW
TSISU
TSIH
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
30
10
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
-
Digital register delay
(internal)
TDISU
TDIH
Parallel data setup time
Parallel data hold time
Address setup time
100
100
100
100
100
100
-
-
TPD
-
-
10
5
ns
ns
-
Digital register delay
(internal, direct mode only)
TDIPD
TASU
TAH
-
Address hold time
-
TPSSU
TPSH
TPD
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
-
-
10
Note:
fClk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
Document No. 70-0244-03 │ www.psemi.com
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Page 7 of 11
PE43702
Product Specification
Figure 17. Evaluation Board Layout
Peregrine Specification 101-0310
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE43702 Digital Step Attenuator.
Direct-Parallel Programming Procedure
For automated direct-parallel programming,
connect the test harness provided with the EVK
from the parallel port of the PC to the J1 & Serial
header pin and set the D0-D6 SP3T switches to
the ‘MIDDLE’ toggle position. Position the
Parallel/Serial (P/S) select switch to the Parallel
(or left) position. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Direct-Parallel mode.
Using the software, enable or disable each setting
to the desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
For manual direct-parallel programming,
disconnect the test harness provided with the EVK
from the J1 and Serial header pins. Position the
Parallel/Serial (P/S) select switch to the Parallel
(or left) position. The LE pin on the Serial header
must be tied to VDD. Switches D0-D6 are SP3T
switches which enable the user to manually
program the parallel bits. When any input D0-D6
is toggled ‘UP’, logic high is presented to the
parallel input. When toggled ‘DOWN’, logic low is
presented to the parallel input. Setting D0-D6 to
the ‘MIDDLE’ toggle position presents an OPEN,
which forces an on-chip logic low. Table 9 depicts
the parallel programming truth table and Fig. 16
illustrates the parallel programming timing
diagram.
Note: Reference Figure 18 for Evaluation Board Schematic
as the parallel bits are applied. The user must
then pulse LE from 0V to VDD and back to 0V to
latch the programming word into the DSA. LE
must be logic low prior to programming the next
word.
Serial Programming Procedure
Position the Parallel/Serial (P/S) select switch to
the Serial (or right) position. The evaluation
software is written to operate the DSA in either
Parallel or Serial Mode. Ensure that the software
is set to program in Serial mode. Using the
software, enable or disable each setting to the
desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
Latched-Parallel Programming Procedure
For automated latched-parallel programming, the
procedure is identical to the direct-parallel
method. The user only must ensure that Latched-
Parallel is selected in the software.
For manual latched-parallel programming, the
procedure is identical to direct-parallel except now
the LE pin on the Serial header must be logic low
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0244-03 │ UltraCMOS™ RFIC Solutions
Page 8 of 11
PE43702
Product Specification
Figure 18. Evaluation Board Schematic
Peregrine Specification 102-0379
VDD
D5
D4
D6
D0
D1
D3
D2
P/S
J1
HEADER 14
D0
2
4
6
1
3
5
7
9
11
13
2
4
6
8
10
12
14
1
3
5
7
9
D1
D2
8
D3
D4
D5
D6
10
12
14
11
13
C5
C7
C6
SERIAL
100pF
100pF
100pF
HEADER 4
CLK
DATA
LE
1
2
3
4
C1
C2
CLOCK
DATA
LE
C4
C3
100pF
100pF
100pF
100pF
GND
VDD
J3
CON2
D0
VDD
P/S
1
2
3
4
5
6
18
17
16
15
14
13
CP25
VDD
S/P
SI
CLK
LE
1
2
C9
C10
100pF
U1
C8
100pF
C13
100pF
C14
100pF
GND
RF1
GND
RF2
GND
0.1µF
43X0X DSA 50 Ohm 4x4 MLP24
J5
SMA
J4
SMA
Z=50 Ohm
1
GND
1
Z=50 Ohm
De-embeding trace
Z=50 Ohm
J6
SMA
J7
SMA
1
1
Note: Capacitors C1-C8, C13, & C14 may be omitted.
Figure 19. Package Drawing
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE43702
Product Specification
Figure 20. Tape and Reel Drawing
Tape Feed Direction
Pin 1
A0 = 4.35
B0 = 4.35
K0 = 1.1
Top of
Device
Device Orientation in Tape
Figure 21. Marking Specifications
43702
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Table 12. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
Bulk or tape cut from reel
3000 units / T&R
PE43702MLI
PE43702MLI-Z
EK43702-01
43702
43702
43702
PE43702 G - 24QFN 4x4mm-75A
PE43702 G – 24QFN 4x4mm-3000C
PE43702 G – 24QFN 4x4mm-EK
Green 24-lead 4x4mm QFN
Green 24-lead 4x4mm QFN
Evaluation Kit
1 / Box
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0244-03 │ UltraCMOS™ RFIC Solutions
Page 10 of 11
PE43702
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
Fax: +82-31-728-3940
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
High-Reliability and Defense Products
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
Europe/Asia-Pacific
Aix-En-Provence Cedex 3, France
Phone: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Document No. 70-0244-03 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
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