PE9704EK [PSEMI]
3.0 GHz Integer-N PLL for Rad Hard Apllications; 3.0 GHz的整数N分频PLL，抗辐射Apllications
| 型号： | PE9704EK |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 3.0 GHz Integer-N PLL for Rad Hard Apllications |
| 文件： | 总11页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
PE9704
3.0 GHz Integer-N PLL for Rad
Product Description
Hard Applications
Peregrine’s PE9704 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in
current consumption, when compared with existing
commercial space PLLs.
Features
• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Phase detector output
• Serial interface or hardwired
programmable
The PE9704 features a ÷10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through a serial
interface, and can also be directly hard wired.
• Ultra-low phase noise
• SEU < 10-9 errors / bit-day
• 100 Krad (Si) total dose
• 44-lead CQFJ
The PE9704 is optimized for commercial space
applications. Single Event Latch-up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. Fabricated in Peregrine’s
patented UTSi® (Ultra Thin Silicon) CMOS technology,
the PE9704 offers excellent RF performance and intrinsic
radiation tolerance.
Figure 1. Block Diagram
Prescaler
FIN
Main
10 / 11
Counter
13
MSEL
20-Bit
fp
Frequency
Register
Serial
PD_U
PD_D
Phase
Control
3
Detector
20
19*
fc
M(8:0)
A(3:0)
R(5:0)
Direct
LD
Control
6
6
C ext
FR
R Counter
* prescaler bypass not available in Direct mode
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PE9704
Advance Information
Figure 2. Pin Configuration
6
5
4
3
2
1
44 43 42 41 40
R4
R5
7
8
39
38
37
36
35
34
33
32
31
30
29
CEXT
VDD
M0
PD_U
PD_D
GND
N/C
9
M1
10
11
12
13
14
15
16
17
VDD
VDD
M2
VDD
M3
DOUT
VDD
S_WR, M4
DATA, M5
GND
N/C
GND
18 19 20 21 22 23 24 25 26 27 28
Table 1. Pin Descriptions
Pin No.
Pin Name
Interface Mode
Type
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
1
VDD
Both
(Note 1)
2
R0
Direct
Direct
Direct
Direct
Both
Input
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
3
R1
Input
4
R2
Input
5
R3
Input
6
GND
R4
(Note 1)
Input
7
Direct
Direct
Direct
Direct
Both
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
8
R5
Input
9
M0
M1
VDD
VDD
M2
M3
Input
10
11
12
13
14
Input
(Note 1)
(Note 1)
Input
Both
Direct
Direct
Input
Frequency register load enable input. Buffered data is transferred to the frequency
register on S_WR rising edge.
S_WR
M4
Serial
Direct
Input
Input
15
16
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-
bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR
“high”) on the rising edge of CLOCK.
DATA
Serial
Input
File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 2 of 12
PE9704
Advance Information
Pin No.
Pin Name
Interface Mode
Type
Description
M5
Direct
Both
Input
M Counter bit5
Ground
17
GND
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK.
CLOCK
Serial
Input
18
M6
Direct
Direct
Direct
Direct
Both
Input
M Counter bit6
19
20
21
22
23
M7
Input
M Counter bit7
M8
Input
M Counter bit8 (MSB)
A0
Input
A Counter bit0
DMODE
VDD
Input
Selects direct interface mode (DMODE=1) or serial interface mode (DMODE=0)
Same as pin 1
Both
(Note 1)
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
E_WR
Serial
Input
24
A1
Direct
Direct
Direct
Both
Input
Input
Input
Input
A Counter bit1.
25
26
27
28
29
30
31
A2
A Counter bit2
A3
A Counter bit3 (MSB)
FIN
RF prescaler input from the VCO. 3.0 GHz maximum frequency.
GND
GND
N/C
VDD
Both
Ground.
Both
Ground.
No connect.
Same as pin 1
Both
Serial
Both
(Note 1)
Output
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to DOUT through enhancement register programming.
32
DOUT
33
34
35
36
37
38
VDD
(Note 1)
Same as pin 1
N/C
No connect.
GND
PD_D
PD_U
VDD
Both
Both
Both
Both
Ground.
Output
PD_D pulses down when fp leads fc.
PD_U pulses down when fc leads fp.
Same as pin 1
(Note 1)
Output
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series resistor.
Connecting CEXT to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
39
CEXT
Both
40
41
42
GND
GND
FR
Both
Both
Both
Ground
Ground
Input
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
43
44
ENH
Both
Output, OD
Lock detect output, the open-drain logical inversion of CEXT. When the loop is locked,
LD is high impedance; otherwise LD is a logic low (“0”).
LD
Serial
Output
Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
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PE9704
Advance Information
Table 2. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 4.
Symbol
Parameter/Conditions Min Max Units
VDD
VI
Supply voltage
Voltage on any input
-0.3
-0.3
4.0
V
V
VDD
+ 0.3
II
IO
Tstg
DC into any input
DC into any output
Storage temperature
range
-10
-10
-65
+10
+10
150
mA
mA
°C
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
Table 3. Operating Ratings
devices are immune to latch-up.
Symbol
Parameter/Conditions Min Max Units
VDD
TA
Supply voltage
Operating ambient
temperature range
2.85
-40
3.15
85
V
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level Units
VESD
ESD voltage (Human Body
Model) – Note 1
1000
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
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PE9704
Advance Information
Table 5. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDD
Operational supply current;
Prescaler disabled
Prescaler enabled
VDD = 2.85 to 3.15 V
10
24
mA
mA
31
Digital Inputs: All except FR, FIN (all digital inputs have 70k ohm pull-up resistors)
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
0.7 x VDD
V
V
0.3 x VDD
+70
µA
µA
IIL
-1
Reference Divider input: FR
IIHR High level input current
IILR Low level input current
Counter and phase detector outputs: fc, fp.
VIH = VDD = 3.15 V
+100
0.4
µA
µA
VIL = 0, VDD = 3.15 V
-100
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
V
V
VDD - 0.4
VDD - 0.4
Lock detect outputs: CEXT, LD
VOLC
VOHC
VOLLD
Output voltage LOW, CEXT
Output voltage HIGH, CEXT
Output voltage LOW, LD
Iout = 100 µ
Iout = -100 µ
Iout = 6 mA
0.4
0.4
V
V
V
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PE9704
Advance Information
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 1and 3)
fClk
tClkH
tClkL
tDSU
tDHLD
tPW
tCWR
tCE
tWRC
tEC
CLOCK Serial data clock frequency
CLOCK Serial clock HIGH time
CLOCK Serial clock LOW time
(Note 1)
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
10
10
30
30
30
30
30
DATA set-up time after CLOCK rising edge
DATA hold time after CLOCK rising edge
S_WR pulse width
CLOCK rising edge to S_WR rising edge.
CLOCK falling edge to E_WR transition
S_WR falling edge to CLOCK rising edge.
E_WR transition to CLOCK rising edge
MSEL data out delay after FIN rising edge
tMDO
CL = 12 pf
8
Main Divider (Including Prescaler)
FIN
PFin
Operating frequency
Input level range
500
-5
3000
5
MHz
dBm
External AC coupling
External AC coupling
Main Divider (Prescaler Bypassed)
FIN
PFin
Operating frequency
Input level range
50
-5
300
5
MHz
dBm
Reference Divider
FR
PFr
Operating frequency
Reference input power (Note 2)
(Note 3)
Single-ended input
100
MHz
dBm
-2
Phase Detector
fc
Comparison frequency
(Note 3)
20
MHz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p
.
Note 3: Parameter is guaranteed through characterization only and is not tested.
File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
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PE9704
Advance Information
Functional Description
The PE9704 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via a serial bus or
hardwired directly to the pins. There are also
various operational and test modes and a lock
detect output.
Prescaler Bypass Mode
Setting the frequency control register bit PB “high”
allows FIN to bypass the ÷10/11 prescaler. In this
mode, the prescaler and A counter are powered
down, and the input VCO frequency is divided by
the M counter directly. This mode is only available
when using the serial port to set the frequency
control bits. The following equation relates FIN to
the reference frequency FR:
FIN = (M + 1) x (FR / (R+1)) )
(3)
where 1 ≤ M ≤ 511
Reference Counter
The reference counter chain divides the reference
frequency FR down to the phase detector
comparison frequency fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
Main Counter Chain
Normal Operating Mode
Setting the PB control bit “low” enables the ÷10/11
prescaler. The main counter chain then divides the
RF input frequency (FIN) by an integer derived from
the values in the “M” and “A” counters.
In this mode, the output from the main counter
chain (fp) is related to the VCO frequency (FIN) by
the following equation:
fc = FR / (R + 1)
(4)
where 0 ≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency (FR) directly to the phase
detector.
fp = FIN / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, FIN is related to the
reference frequency (FR) by the following equation:
FIN = [10 x (M + 1) + A] x (FR / (R+1))
(2)
where A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that FIN
must be greater than or equal to 90 x (FR / (R+1)) to
obtain contiguous channels. The A counter can
accept values as high as 15, but in typical operation
it will cycle from 0 to 9 between increments in M.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
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PE9704
Advance Information
Register Programming
Serial Interface Mode
contents from this buffer register are transferred into
the enhancement register on the falling edge of
E_WR according to the timing diagram shown in
Figure 3. After the falling edge of E_WR, the data
provides control bits as shown in Table 8. These
bits are active when the Enh input is “low”.
Serial Interface Mode is selected by setting the
DMODE input “low”.
While the E_WR input is “low”, serial data (DATA
input), B0 to B19, is clocked into a buffer register on
the rising edge of CLOCK, LSB (B0) first. The
contents from this buffer register are transferred into
the frequency control register on the rising edge of
S_WR according to the timing diagram shown in
Figure 3. This data controls the counters as shown
in Table 7.
While the E_WR input is “high”, serial data (DATA
input), B0 to B7, is clocked into a buffer register on
the rising edge of CLOCK, LSB (B0) first. The
Direct Interface Mode
Direct Interface Mode is selected by setting the
D
MODE input “high”. In this mode, the counter values
are set directly at external pins as shown in Table 7
and Figure 2. All frequency control register bits are
addressable except PB (it is not possible to bypass
the ÷10/11 dual modulus prescaler in Direct Mode).
Table 7. Frequency Register Programming
Interface
Enh
DMODE
R5
B0
R5
R4
B1
R4
M8
B2
M7
B3
PB
B4
0
M6
B5
M5
B6
M4
B7
M3
B8
M2
B9
M1
B10
M1
M0
B11
M0
R3
B12
R3
R2
B13
R2
R1
B14
R1
R0
B15
R0
A3
B16
A3
A2
B17
A2
A1
B18 B19
A1 A0
A0
Mode
Serial*
1
0
1
Direct
1
M8
M7
M6
M5
M4
M3
M2
* Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.
LSB (first in)
MSB (last in)
Table 8. Enhancement Register Programming
Interface
Power
down
Counter
load
MSEL
fc output
Enh
DMODE
Reserved*
Reserved*
fp output
Reserved*
B7
Mode
output
Serial**
0
X
B0
B1
B2
B3
B4
B5
B6
* Program to 0
* Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.
LSB (first in)
MSB (last in)
File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 8 of 12
PE9704
Advance Information
Figure 3. Serial Interface Mode Timing Diagram
DATA
E_WR
tEC
tCE
CLOCK
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
Enhancement Register
The functions of the enhancement register bits are shown below. All bits are active high. Operation is
undefined if more than one output is sent to DOUT
.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
Reserved**
fp output
Drives the M counter output onto the DOUT output.
Power down
Counter load
MSEL output
fc output
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output.
Drives the R counter output onto the DOUT output
Reserved**
** Program to 0
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PE9704
Advance Information
Phase Detector Outputs
Lock Detect Output
The phase detector is triggered by rising edges
from the main counter (fp) and the reference counter
(fc). It has two outputs, PD_U, and PD_D. If the
divided VCO leads the divided reference in phase
or frequency (fp leads fc), PD_D pulses “low”. If the
divided reference leads the divided VCO in phase
or frequency (fc leads fp), PD_U pulses “low”. The
width of either pulse is directly proportional to phase
offset between the two input signals, fp and fc. The
phase detector gain is 430 mV / radian.
PD_U and PD_D are designed to drive an active
loop filter which controls the VCO tune voltage.
PD_U pulses result in an increase in VCO
frequency and PD_D results in a decrease in VCO
frequency.
A lock detect signal is provided at pin LD, via the
pin CEXT (see Figure 1). CEXT is the logical “NAND”
of PD_U and PD_D waveforms, driven through a
series 2k ohm resistor. Connecting CEXT to an
external shunt capacitor provides integration of this
signal.
The CEXT signal is then sent to the LD pin through
an internal inverting comparator with an open drain
output. Thus LD is an “AND” function of PD_U and
PD_D.
Software tools for designing the active loop filter
can be found at Peregrine’s web site
(www.peregrine-semi.com).
File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 10 of 12
PE9704
Advance Information
Figure 4. Package Drawing
44-lead CQFJ
All dimensions are in mils
Table 10. Ordering Information
Order
Shipping
Method
Part Marking
Description
Package
Code
9704-01
9704-11
9704-00
PE9704 ES
PE9704
PE9704 EK
Engineering Samples
Flight Units
Evaluation Kit
44-pin CQFJ
44-pin CQFJ
40 units / Tray
40 units / Tray
1 / Box
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