ASM2I3807AG-20-AR [PULSECORE]
3.3V CMOS 1-TO-10 CLOCK DRIVER; 3.3V CMOS 1到10个时钟驱动器型号: | ASM2I3807AG-20-AR |
厂家: | PulseCore Semiconductor |
描述: | 3.3V CMOS 1-TO-10 CLOCK DRIVER |
文件: | 总18页 (文件大小:655K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
November 2006
rev 0.3
ASM2P3807A
3.3V CMOS 1-TO-10 CLOCK DRIVER
Product Description
Features
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0.5 MICRON CMOS Technology
The ASM2P3807A 3.3V clock driver is built using advanced
dual metal CMOS technology. This low skew clock driver
offers 1:10 fanout. The large fanout from a single input
reduces loading on the preceding driver and provides an
efficient clock distribution network. The ASM2P3807A
offers low capacitance inputs with hysteresis for improved
noise margins. Multiple power and grounds reduce noise.
Typical applications are clock and signal distribution.
Guaranteed low skew < 350pS (max.)
Very low duty cycle distortion < 350pS (max.)
High speed: propagation delay < 3nS (max.)
Very low CMOS power levels
TTL compatible inputs and outputs
1:10 fanout
Maximum output rise and fall time < 1.5nS (max.)
Low input capacitance: 4.5pF typical
Operates with 3.3V ± 0.3V Supply
Inputs can be driven from 3.3V or 5V components
Available in SSOP, SOIC, and QSOP Packages
Block Diagram
O1
O2
O3
O4
O5
IN
O6
O7
O8
O9
O10
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
Pin Configuration
IN
VCC
O10
O9
1
2
20
19
GND
A
S
M
2
3
4
18
17
O1
VCC
O2
GND
O8
5
16
15
14
13
12
11
P
3
VCC
O7
6
GND
O3
8
7
0
GND
O6
8
VCC
7
A
9
O4
O5
10
GND
SOIC / SSOP/ QSOP Packages
TOP VIEW
Pin Description
Pin#
1
Pin Names
I N
Description
Clock Inputs
Clock Outputs
Ground
3,5,7,9,11,12,14,16,18,19
2,6,10,13,17
4,8,15,20
O 1-O10
GND
Vcc
Power
Absolute Maximum Ratings
Symbol
Description
Max
-0.5 to +4.6
Unit
V
1
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
2
VTERM
-0.5 to +7
-0.5 to VCC+0.5
-65 to +150
-60 to +60
V
V
3
VTERM
TSTG
IOUT
° C
mA
DC Output Current
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
NOTES:
1. VCC terminals.
2. Input terminals.
3. Outputs and I/O terminals.
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
Capacitance (TA = +25°C, f = 1.0MHz)
ASM2P3807A
Symbol
Parameter1
Conditions
Typ
Max
Unit
CIN
Input Capacitance
VIN= 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
Note:1. This parameter is measured at characterization but not tested.
Power Supply Characteristics
Symbol
Parameter
Test Conditions1
Min
Typ2
Max
Unit
V
CC= Max.
Quiescent Power Supply
Current TTL Inputs HIGH
∆ICC
10
30
µA
V
IN = VCC –0.6V3
VCC= Max.
Input toggling
50% Duty Cycle
Outputs Open
mA/
MHz
VIN = VCC
Dynamic Power Supply
Current4
ICCD
0.31
0.45
VIN = GND
VCC= Max.
Input toggling
50% Duty Cycle
Outputs Open
fi = 50MHz
VIN = VCC
IC
Total Power Supply Current6
15.5
22.85
mA
VIN = GND
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ
)
∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fi = Input Frequency
All currents are in milliamps and all frequencies are in megahertz.
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 3.3V ± 0.3V
Symbol Parameter
Test Conditions1
Guaranteed Logic HIGH Level
Min
2
Typ
Max
5.5
Unit
V
Input HIGH Level (Input pins)
VIH
VIL
IIH
Input HIGH Level (I/O pins)
Input LOW Level
2
VCC+ 0.5
Guaranteed Logic LOW Level
-0.5
0.8
V
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedence Output Current
(3-State Output Pins)
VCC= Max
VCC= Max
VCC= Max
VI = 5.5V
VI = VCC
±1
±1
µA
VI = GND
VI = GND
VO = VCC
VO = GND
±1
IIL
±1
IOZH
IOZL
VIK
±1
µA
±1
Clamp Diode Voltage
VCC= Min., IIN = –18mA
VCC= 3.3V, VIN = VIH or VIL,
VO = 1.5V3
-0.7
-60
-1.2
V
IODH
Output HIGH Current
-36
50
-110
200
mA
VCC= 3.3V, VIN = VIH or VIL,
VO = 1.5V3
IODL
VOH
Output LOW Current
Output HIGH Voltage
90
3
mA
V
VCC= Min.
IN = VIH or VIL
VCC= Min
IOH= –0.1mA
VCC-0.2
2.45
V
IOH= –8mA
IOL= 0.1mA
IOL= 16mA
IOL= 24mA
VOL
Output LOW Voltage
0.2
0.4
0.5
±1
V
0.2
0.3
VIN = VIH or VIL
IOFF
IOS
Input Power Off Leakage
Short Circuit Current4
Input Hysteresis
VCC= 0V, VIN = 4.5V
VCC= Max., VO = GND3
µA
mA
mV
-60
-135
150
-240
VH
-
ICCL
ICCH
ICCZ
VCC= Max.
Quiescent Power Supply Current
0.1
10
µA
VIN = GND or VCC
NOTES:
1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = Vcc - 0.6V at rated current.
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
ASM2P3807A
rev 0.3
Switching Characteristics Over Operating Range – Commercial3,4
ASM2P3807A
Symbol
Parameter
Conditions1
Unit
Min2
Max
tPLH
tPHL
tR
Propagation Delay
1.5
3
nS
50Ω to VCC/2
CL= 10pF
Output Rise Time
Output Fall Time
1.5
1.5
nS
nS
tF
(See figure 1)
or 10Ω AC
termination,
CL= 50pF
Output skew: skew
between outputs of
same package (same
transition)
Pulse skew: skew
between opposite
transitions of same
output (|tPHL – tPLH|)
tSK(O)
0.35
0.35
nS
nS
(See figure 2)
f≤ 100MHz
Outputs
tSK(P)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package type and
speed grade
connected in
groups of two
tSK(T)
0.65
nS
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
ASM2P3807A
Unit
Conditions1
Min2
Max
Symbol
Parameter
tPLH
Propagation Delay
1.5
4
nS
tPHL
tR
Output Rise Time
1.5
1.5
nS
nS
tF
Output Fall Time
CL= 30pF
tSK(O)
Output skew: skew between outputs of
same package (same transition)
0.45
0.45
nS
nS
f≤ 67MHz
(See figure 3)
tSK(P)
Pulse skew: skew between opposite
transitions of same output (|tPHL – tPLH|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
tSK(T)
0.75
nS
ASM2P3807A
Symbol
Parameter
Conditions1
Unit
Min2
Max
tPLH
tPHL
tR
Propagation Delay
1.5
4.3
nS
Output Rise Time
Output Fall Time
1.5
1.5
nS
nS
tF
CL= 50pF
f≤ 40MHz
Output skew: skew between outputs of
same package (same transition)
tSK(O)
tSK(P)
0.35
0.35
nS
nS
(See figure 4)
Pulse skew: skew between opposite
transitions of same output (|tPHL – tPLH|)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
tSK(T)
0.75
nS
NOTES:1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delays
limits do not imply skew.
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
ASM2P3807A
rev 0.3
Switching Characteristics Over Operating Range - Industrial3,4
ASM2P3807A
Unit
Max
Conditions1
Min2
Symbol
Parameter
tPLH
Propagation Delay
1.5
3
nS
tPHL
tR
Output Rise Time
Output Fall Time
1.5
1.5
nS
nS
50Ω to VCC/2
CL= 10pF
tF
Output skew: skew
between outputs of
same package (same
transition)
(See figure 1)
or 50Ω AC
termination,
CL= 10pF
tSK(O)
0.45
0.45
nS
nS
Pulse
between
skew:
skew
opposite
(See figure 2)
f≤ 100MHz
Outputs
tSK(P)
transitions of same
output (|tPHL – tPLH|)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
connected in
groups of two
tSK(T)
0.65
nS
package
type
and
speed grade
ASM2P3807A
Unit
Symbol
tPLH
Parameter
Conditions1
Min2
Max
Propagation Delay
1.5
4
nS
tPHL
tR
Output Rise Time
Output Fall Time
1.5
1.5
nS
nS
tF
tSK(O)
Output skew: skew
between outputs of
same package (same
transition)
0.45
0.45
nS
nS
CL= 30pF
f≤ 67MHz
tSK(P)
Pulse
skew:
skew
between
opposite
(See figure 3)
transitions of same
output (|tPHL - tPLH|)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
package type and
speed grade
nS
tSK(T)
0.75
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
ASM2P3807A
Unit
Max
Symbol
Parameter
Conditions1
Min2
tPLH
Propagation Delay
1.5
4.3
nS
tPHL
tR
Output Rise Time
Output Fall Time
1.5
1.5
nS
nS
tF
Output skew: skew
between outputs of
same package (same
transition)
tSK(O)
0.45
0.45
nS
nS
CL= 50pF
f≤ 40MHz
Pulse
between
skew:
skew
opposite
(See figure 4)
tSK(P)
transitions of same
output (|tPHL - tPLH|)
Package skew: skew
between outputs of
different packages at
same power supply
voltage, temperature,
tSK(T)
0.75
nS
package
type
and
speed grade
NOTES:1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min and Max limit is due to VCC, operating temperature and process parameters. These propagation delay limits
do not imply skew.
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
Test Circuits
ASM2P3807A
VCC
VCC
100Ω
VN
VOUT
PULSE
D.U.T
GENERATOR
10pF
100Ω
RT
Figure 1. ZO = 50Ω to VCC/2, CL = 10pF
VCC
VCC
100Ω
VN
VOUT
PULSE
D.U.T
GENERATOR
10pF
RT
50Ω
220pF
Figure 2. ZO = 50Ω AC Termination, CL = 10pF
The capacitor value for ac termination is determined by the operating frequency.
For very low frequencies a higher capacitor value should be selected.
VCC
VN
VOUT
PULSE
GENERATOR
D.U.T
30pF
CL
RT
Figure 3. CL = 30pF Circuit
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
VCC
VN
VOUT
PULSE
O.U.T
GENERATOR
50pF
CL
RT
Figure 3. CL = 50pF Circuit
6V
VCC
GND
500Ω
500Ω
VN
VOUT
PULSE
GENERATOR
O.U.T
50pF
CL
RT
Figure 5. Enable and Disable Time Circuit
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
Enable and Disable Time
Switch Position
Test
Switch
Disable LOW
6V
Enable LOW
Disable HIGH
Enable HIGH
GND
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Waveforms
3V
1.5V
INPUT
OV
tPLH
tPHL
VOH
2.0 V
1.5 V
0.8 V
OUTPUT
VOL
tR
tF
Package Delay
1.5V
OV
INPUT
tPLH
tPLH
VOH
1.5 V
VOL
3V
OUTPUT
tSK(p) =[ tPHL – tPLH
]
Pulse Skew - tSK(P)
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
3V
1.5V
INPUT
OV
tPLH 1
tPLHL
1
VOH
1.5 V
OUTPUT 2
VOL
tSK(0)
tSK(O
VOH
1.5 V
VOL
tPHL2
tPLH2
tSK(O) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1
]
Output Skew - tSK(O)
3V
1.5V
INPUT
OV
tPLH 1
tPLHL
1
VOH
1.5 V
VOL
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tSK(t)
tSK(t)
VOH
1.5 V
VOL
tPHL2
tSK(t) =[ tPLH2 – tPLH 1 ] or [tPHL2 - tPHL1
tPLH2
]
Package Skew - tSK(T)
Package 1 and Package 2 are same device type and speed grade
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
ENABLE
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPLZ
tPLZ
3.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
VOL
tPLZ
tPLZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
VOH
0V
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f ≤1.0MHz; tF ≤2.5nS; tR ≤2.5nS
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
Package Information
ASM2P3807A
20-lead SSOP ( 150 mil )
Dimensions
Millimeters
Symbol
Inches
Min
0.053
0.004
….
0.337
0.007
0.228
0.150
0.016
Max
0.069
0.010
0.059
0.344
0.011
0.244
0.157
0.035
Min
1.346
0.102
….
8.560
0.178
5.791
3.810
0.406
Max
1.753
0.254
1.499
8.738
0.274
6.198
3.988
0.890
A
A1
A2
D
c
E
E1
L
L1
b
R1
a
0.010 BASIC
0.254 BASIC
0.008
0.003
0°
0.014
….
8°
0.203
0.08
0°
0.356
…..
8°
e
0.025 BASIC
0.635 BASIC
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
20L SOIC Package (300 mil)
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.104
0.012
0.094
0.512
0.050
0.299
….
Min
2.35
0.10
2.25
12.60
0.40
7.40
0.08
0.33
0.23
10.00
Max
2.65
0.30
2.40
13.00
1.27
7.60
…..
A
A1
A2
D
0.093
0.004
0.088
0.496
0.016
0.291
0.003
0.013
0.009
0.394
L
E1
R1
b
c
E
0.022
0.015
0.419
0.56
0.38
10.65
e
a
0.050 BSC
0°
1.27 BSC
0°
8°
8°
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
20-lead QSOP Package
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.068
0.008
0.012
0.010
0.344
0.157
Min
1.52
0.10
0.23
0.18
8.56
3.81
Max
1.73
0.20
0.30
0.25
8.74
3.99
A
A1
b
0.060
0.004
0.009
0.007
0.337
0.150
c
D
E
e
0.025 BSC
0.64 BSC
H
h
L
S
a
0.230
0.010
0.014
0.056
0°
0.244
0.016
0.030
0.060
8°
5.84
0.25
0.35
1.42
0°
6.20
0.41
0.75
1.52
8°
3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
Ordering Information
ASM2P3807A
Part Number
ASM2P3807AG-20-AR
ASM2P3807AG-20-AT
ASM2P3807AG-20-DR
ASM2P3807AG-20-DT
ASM2P3807AG-20-SR
ASM2P3807AG-20-ST
ASM2I3807AG-20-AR
ASM2I3807AG-20-AT
ASM2I3807AG-20-DR
ASM2I3807AG-20-DT
ASM2I3807AG-20-SR
ASM2I3807AG-20-ST
Marking
2P3807AG
2P3807AG
2P3807AG
2P3807AG
2P3807AG
2P3807AG
2I3807AG
2I3807AG
2I3807AG
2I3807AG
2I3807AG
2I3807AG
Package Type
20-Pin SSOP, TAPE & REEL, Green
20-Pin SSOP, TUBE, Green
20-Pin QSOP, TAPE & REEL, Green
20-Pin QSOP, TUBE, Green
20-Pin SOIC, TAPE & REEL, Green
20-Pin SOIC, TUBE, Green
20-Pin SSOP, TAPE & REEL, Green
20-Pin SSOP, TUBE, Green
20-Pin QSOP, TAPE & REEL, Green
20-Pin QSOP, TUBE, Green
20-Pin SOIC, TAPE & REEL, Green
20-Pin SOIC, TUBE, Green
Temperature
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Device Ordering Information
A S M 2 P 3 8 0 7 A G - 2 0 - A T
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920.
3.3V CMOS 1-TO-10 CLOCK DRIVER
17 of 18
Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
ASM2P3807A
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM2P3807A
Document Version: v0.3
Tel: 408-879-9077
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Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
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3.3V CMOS 1-TO-10 CLOCK DRIVER
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Notice: The information in this document is subject to change without notice.
相关型号:
ASM2I3807AHG-20-AR
Low Skew Clock Driver, 3807 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, GREEN, SSOP-20
PULSECORE
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