ASM2P2351A-24ST [PULSECORE]
Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, PLASTIC, SOIC-24;型号: | ASM2P2351A-24ST |
厂家: | PulseCore Semiconductor |
描述: | Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, PLASTIC, SOIC-24 光电二极管 |
文件: | 总13页 (文件大小:479K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
October 2005
rev 0.2
ASM2P2351AH
1-Line To 10-Line Clock Driver With 3-State Outputs
Product Description
Features
The ASM2P2351AH is a high-performance clock-driver
circuit that distributes one input (A) to ten outputs (Y)
with minimum skew for clock distribution. The output-
enable (OE) input disables the outputs to a high-
impedance state. Each output has an internal series
damping resistor to improve signal integrity at the load.
The ASM2P2351AH operates at nominal 3.3V Supply
Voltage.
•
Low Output Skew, Low Pulse Skew for Clock-
Distribution and Clock-Generation Applications.
•
Operates at 3.3V Supply Voltage.
•
•
LVTTL-Compatible Inputs and Outputs.
Supports Mixed-Mode Signal Operation.
(5V Input and Output Voltages With 3.3V Supply
Voltage).
The propagation delays are adjusted at the factory
using the P0 and P1 pins. The factory adjustments
ensure that the part-to-part skew is minimized and is
kept within a specified window. Pins P0 and P1 are not
intended for customer use and should be connected to
GND.
•
•
Distributes One Clock Input to Ten Outputs.
Outputs have Internal Series Damping Resistor
to Reduce Transmission Line Effects.
•
•
Distributed VCC and Ground Pins Reduce
Switching Noise.
Package Options Include Plastic Small-Outline
and Shrink Small-Outline Packages.
The ASM2P2351AH is characterized for operation
from 0°C to 70°C.
Logic Diagram (Positive Logic)
5
OE
23
21
Y2
19
Y3
18
Y4
6
A
16
Y5
7
8
PO P1
14
Y6
11
Y7
9
Y8
4
Y9
2
Y10
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Pin Configuration
GND
Y1
1
2
3
4
24
23
22
21
GND
Y10
VCC
A
S
M
2
VCC
Y2
GND
Y3
Y4
GND
Y9
OE
A
P0
P1
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
P
2
3
5
Y5
V
Y8
VCC
1
A
H
Y6
Y7
GND
GND
SSOP/ SOIC Packages
TOP VIEW
Pin Description
Pin #
Pin Name
Typ
Description
1
GND
Y10
VCC
Y9
P
Ground Pin
Output 10
2
3
4
5
O
P
O
I
Power Supply Pin
Output 9
OE
Output Enable Pin. When this pin is low, the outputs Y[1:10] are enabled
and when this pin is high , the outputs Y[1:10] are disabled.
6
A
I
Input Clock
No Connect
No Connect
Output 8
7
P0
-
8
P1
-
9
Y8
O
P
O
P
P
O
P
O
P
O
O
P
O
P
O
P
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
Y7
Power Supply
Output 7
GND
GND
Y6
Ground Pin
Ground Pin
Output 6
VCC
Y5
Power Supply
Output 5
GND
Y4
Ground Pin
Output 4
Y3
Output 3
GND
Y2
Ground Pin
Output 2
VCC
Y1
Power Supply
Output 1
GND
Ground Pin
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Function Table
Inputs
Outputs
In
A
OE
L
H
Z
Z
L
H
L
H
L
L
H
H
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VCC
VIN
tSTG
tA
Voltage on Supply pin with respect to Ground
Voltage on any pin with respect to Ground
Storage temperature
-0.5 to +4.6
V
-0.5 to +7.0
-65 to +125
0 to 70
260
V
°C
°C
°C
°C
Operating temperature
ts
Max. Soldering Temperature (10 sec)
Junction Temperature
tJ
150
Static Discharge Voltage
tDV
2
KV
(As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Recommended operating conditions (see Note 3)
Symbol
VCC
VIH
VIL
VI
IOH
IOL
fclock
TA
Parameter
Min
3
2
Max Unit
Supply voltage
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input clock frequency
Operating free air temperature
0.8
5.5
–12
12
V
V
mA
mA
MHz
°C
0
100
70
0
NOTE 3: Unused pins (input or I/O) must be held high or low.
.
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2351AH
Electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
Parameter
Test Conditions
II = –18 mA
IOH = – 12 mA
IOL = 12 mA
VI = VCC or GND
VO = 2.5 V
Min
Typ
Max
–1.2
Unit
V
V
VIK
VOH
VOL
II
VCC = 3 V,
VCC = 3 V,
VCC = 3 V,
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V,
2
0.8
± 1
–70
± 10
0.3
15
V
mA
mA
mA
1
IO
–7
IOZ
VCC = 3 V
Outputs high
Outputs low
Outputs disabled
f = 10 MHz
ICC
VCC = 3.6 V, IO = 0, VI = VCC or GND
mA
0.3
Ci
Co
VI = VCC or GND,
VO = VCC or GND,
VCC = 3.3 V,
VCC = 3.3 V,
4
6
pF
pF
f = 10 MHz
Note: 1 Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
Switching Characteristics, CL = 50 pF (see Figures 1 and 2)
ASM2P2351A
ASM2P2351AH
From
To
VCC = 3.3 V, TA = 25°C
VCC = 3 V to 3.6 V,
Parameter
Unit
(Input)
(Output)
TA = 0°C to 70°C
Min
Typ
4.3
4.1
4.9
4.3
4.4
4.6
0.3
0.2
Max
Min
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
tsk(p)
tsk(pr)
tr
3.8
3.6
2.4
2.4
2.2
2.2
4.8
4.6
6.0
6.0
6.3
6.3
0.5
0.8
1
A
Y
Y
Y
nS
nS
nS
1.8
1.8
2.1
2.1
6.9
6.9
7.1
7.3
0.5
0.8
1
OE
OE
A
A
A
A
A
Y
Y
Y
Y
Y
nS
nS
nS
nS
nS
2.5
2.5
tf
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2351AH
Switching Characteristics temperature and VCC coefficients over recommended operating free-air
temperature and VCC range (see Note 3)
From
To
Parameter
Min
Max
Unit
(Input) (Output)
tPLH(T)
tPHL(T)
Average temperature coefficient of low to high
propagation delay
A
A
A
Y
Y
Y
pS/10°C
pS/10°C
851
Average temperature coefficient of high to low
propagation delay
Average VCC coefficient of low to high propagation
delay
501
tPLH(VCC
)
pS/ 100
mV
–1452
tPHL(VCC
)
Average VCC coefficient of high to low propagation
pS/ 100
A
Y
–1002
delay
mV
Note: 1 tPLH(T) and tPHL(T) are virtually independent of VCC
2 tPLH(VCC) and tPHL(VCC) are virtually independent of temperature.
3 This data was extracted from characterization material and are not tested at the factory.
.
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Parameter Measurement Information
6V
OPEN
GND
S1
500Ω
From Output
Under Test
CL = 50pF
(see Note A)
500Ω
LOAD CIRCUIT
3V
1.5V
TIMING INPUT
OV
tsu
th
3V
1.5V
DATA INPUT
1.5V
3V
1.5V
1.5V
INPUT
O V
tPLH
tPHL
VOH
2V
0.8V
2V
1.5V
0.8V
OUTPUT
VOL
tr
tr
tW
3 V
INPUT
1.5V
1.5V
O V
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2351AH
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
tPLZ
tPHZ
3 V
Output
Waveform 1
S1 at 6 V
(see Note B)
VOL + O.3 V
1.5 V
VOL
tPHZ
tPZH
VOH
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH. – 0.3 V
0 V
Figure 1. Load Circuit and Voltage Waveforms
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 3 10 MHz, ZO = 50ꢀ, tr 3 2.5 nS, tf 3 2.5 nS.
D. The outputs are measured one at a time with one transition per measurement.
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Parameter Measurement Information
A
Y1
tPHL 1
tPLH 1
Y2
tPHL 2
tPLH 2
Y3
tPHL 3
tPLH 3
Y4
tPHL 4
tPLH 4
tPLH 5
tPLH 6
Y5
tPHL 5
Y6
tPHL 6
Y7
tPHL 7
tPLH 7
Y8
tPHL 8
tPLH 8
Y9
tPHL 9
tPLH 9
Y10
tPHL 10
tPLH 10
Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr)
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
– The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
B. Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPHLn | (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10).
C. Process skew, tsk(pr), is calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions
– The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) across multiple devices under identical operating conditions
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Package Information
24L SSOP Package (209 mil)
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.079
…
Min
…
Max
2.0
…
A
A1
A2
D
L
E
E1
R1
b
….
0.002
0.065
0.315
0.021
0.295
0.197
0.004
0.009
0.004
0.05
1.65
8.00
0.55
7.50
5.00
0.09
0.22
0.09
0.073
0.331
0.037
0.319
0.220
….
1.85
8.40
0.95
8.10
5.60
…..
0.015
0.010
0.38
0.25
c
L1
e
a
0.050REF
0.026 BSC
0°
1.25 REF
0.65 BSC
0° 8°
8°
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2351AH
24L SOIC Package (300 mil)
Dimensions
Millimeters
Symbol
Inches
Min
Max
0.104
0.012
0.094
0.614
0.050
0.299
….
Min
2.35
0.10
2.25
15.20
0.40
7.40
0.08
0.33
0.23
10.00
Max
2.65
0.30
2.40
15.60
1.27
7.60
…..
A
A1
A2
D
0.093
0.004
0.088
0.598
0.016
0.291
0.003
0.013
0.009
0.394
L
E1
R1
b
c
E
0.022
0.015
0.419
0.56
0.38
10.65
e
a
0.050 BSC
0°
1.27 BSC
0°
8°
8°
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Ordering Information
Part Number
Marking
2P2351AHF
2P2351AHF
2P2351AHF
2P2351AHF
2P2351AF
2P2351AF
2P2351AF
2P2351AF
2P2351AHG
2P2351AHG
2P2351AHG
2P2351AHG
2P2351AG
2P2351AG
2P2351AG
2P2351AG
2P2351AH
2P2351AH
2P2351AH
2P2351AH
2P2351A
Package Type
24-Pin SSOP, TAPE & REEL, Pb Free
24-Pin SSOP, TUBE, Pb Free
24-Pin SOIC, TAPE & REEL, Pb Free
24-Pin SOIC, TUBE, Pb Free
24-Pin SSOP, TAPE & REEL, Pb Free
24-Pin SSOP, TUBE, Pb Free
24-Pin SOIC, TAPE & REEL, Pb Free
24-Pin SOIC, TUBE, Pb Free
24-Pin SSOP, TAPE & REEL, Green
24-Pin SSOP, TUBE, Green
24-Pin SOIC, TAPE & REEL, Green
24-Pin SOIC, TUBE, Green
24-Pin SSOP, TAPE & REEL, Green
24-Pin SSOP, TUBE, Green
24-Pin SOIC, TAPE & REEL, Green
24-Pin SOIC, TUBE, Green
24-Pin SSOP, TAPE & REEL
24-Pin SSOP, TUBE
Temperature
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
ASM2P2351AHF-24AR
ASM2P2351AHF-24AT
ASM2P2351AHF -24SR
ASM2P2351AHF-24ST
ASM2P2351AF-24AR
ASM2P2351AF-24AT
ASM2P2351AF -24SR
ASM2P2351AF-24ST
ASM2P2351AHG-24AR
ASM2P2351AHG-24AT
ASM2P2351AHG -24SR
ASM2P2351AHG-24ST
ASM2P2351AG-24AR
ASM2P2351AG-24AT
ASM2P2351AG -24SR
ASM2P2351AG-24ST
ASM2P2351AH-24AR
ASM2P2351AH-24AT
ASM2P2351AH -24SR
ASM2P2351AH-24ST
ASM2P2351A-24AR
ASM2P2351A-24AT
24-Pin SOIC, TAPE & REEL
24-Pin SOIC, TUBE
24-Pin SSOP, TAPE & REEL
24-Pin SSOP, TUBE
2P2351A
ASM2P2351A -24SR
ASM2P2351A-24ST
2P2351A
24-Pin SOIC, TAPE & REEL
24-Pin SOIC, TUBE
2P2351A
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
ASM2P2351AH
rev 0.2
Device Ordering Information
A S M 2 P 2 3 5 1 A H F - 2 4 A R
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent Nos 5,488,627 and 5,631,920.
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
ASM2P2351AH
Copyright © Alliance Semiconductor
Alliance Semiconductor Corporation
2575 Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
All Rights Reserved
Advance Information
Part Number: ASM2P2351AH
Document Version: v0.2
Fax: 408-855-4999
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
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other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
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assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
1-Line To 10-Line Clock Driver With 3-State Outputs
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Notice: The information in this document is subject to change without notice.
相关型号:
ASM2P2351AH-24AR
Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, SSOP-24
PULSECORE
ASM2P2351AH-24AT
Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, SSOP-24
PULSECORE
ASM2P2351AH-24SR
Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 INCH, PLASTIC, SOIC-24
PULSECORE
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