ASM3I2110AF-20-JT [PULSECORE]

Clock Generator, 51MHz, CMOS, PDSO20, 0.150 INCH, LEAD FREE, SSOP-20;
ASM3I2110AF-20-JT
型号: ASM3I2110AF-20-JT
厂家: PulseCore Semiconductor    PulseCore Semiconductor
描述:

Clock Generator, 51MHz, CMOS, PDSO20, 0.150 INCH, LEAD FREE, SSOP-20

光电二极管
文件: 总8页 (文件大小:311K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ASM3P2110A  
November 2003  
rev 1.1  
electromagnetic interference (EMI) at the clock source.  
The ASM3P2110A allows significant system cost savings  
by reducing the number of circuit board layers and  
shielding that are required to pass EMI regulations. The  
ASM3P2110A modulates the output of PLL in order to  
spread the bandwidth of a synthesized clock, thereby  
decreasing the peak amplitudes of its harmonics. This  
results in significantly lower system EMI compared to the  
typical narrow band signal produced by oscillators and  
most clock generators. Lowering EMI by increasing a  
signal’s bandwidth is called spread spectrum clock  
generation.  
Features  
ƒ
Generates an EMI optimized clocking  
signal at output.  
ƒ
ƒ
ƒ
ƒ
ƒ
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Input frequency – 12.75 MHz.  
Output Frequency – 51 MHz (modulated)  
Frequency Deviation: ±1%.  
Modulation Rate: 30 KHz.  
Supply voltage range 3.3V.  
Available in commercial and industrial  
temperature ranges.  
Available in 20-pin 150-mil SSOP package.  
ƒ
Product Description  
The ASM3P2110A is  
a versatile spread spectrum  
frequency modulator. The ASM3P2110A reduces  
Block Diagram  
VDD  
XIN  
Crystal  
Oscillator  
PLL  
+
SS  
ClockOut  
(51MHz)  
XOUT  
Output  
Buffer  
REFOUT  
SSON  
VSS  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara CA Tel: 408-855-4900 Fax: 408-855-4999 www.alsc.com  
ASM3P2110A  
November 2003  
rev 1.1  
Pin Configuration  
20  
1
REFOUT  
NC  
X2  
X1  
19  
18  
17  
2
3
NC  
4
NC  
NC  
NC  
GND  
NC  
5
6
7
8
9
16  
ASM3P2110A  
15 NC  
14 NC  
NC  
NC  
13  
NC  
12  
NC  
SSON  
NC  
11  
CLK 10  
Pin Description  
Pin #  
Pin Name Pin Type  
Description  
Crystal connection or external reference frequency input. This pin has  
dual functions. It can be connected to either an external crystal or an  
reference clock.  
1
X2  
O
Crystal connection. If using an external reference, this pin must be left  
unconnected.  
2
X1  
I
3
VDD  
P
Power supply to the entire chip. (3.3V)  
9, 11,  
13-16,  
18, 19  
10  
NC  
CLK  
-
O
I
No connection.  
Modulated output (51MHz).  
Digital logic input used to enable spread spectrum function. (Active  
HIGH). Spread spectrum is enabled when HIGH, disabled when LOW.  
This pin has an internal pull-low resistor.  
12  
SSON  
17  
20  
GND  
P
Ground connection.  
REFOUT  
O
Un-modulated reference output clock of the input frequency.  
Peak Reducing EMI Solution  
2 of 8  
ASM3P2110A  
November 2003  
rev 1.1  
Absolute Maximum Ratings  
Symbol  
VDD  
VI  
Parameter  
Supply voltage, DC  
Input voltage, DC  
Output voltage, DC  
Input clamp current (VI <0 or VI > VDD)  
Output clamp current (VI <0 or VI > VDD)  
Storage temperature  
Ambient temperature range, under bias  
Junction temperature  
Lead temperature (soldering 10 sec)  
Input static discharge voltage protection  
(MIL –STD 883E, Method 3015.7)  
Rating  
(GND – 0.5) to 7  
(GND-0.5) to (VDD+0.5)  
(GND-0.5) to (VDD + 0.5)  
-50 to +50  
Unit  
V
V
VO  
IIK  
IOK  
TS  
TA  
TJ  
V
mA  
mA  
°C  
°C  
°C  
°C  
-50 to +50  
-65 to +150  
-25 to +85  
150  
260  
2
kV  
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum  
ratings for extended periods may affect device reliability.  
Operating Conditions  
Parameter  
Supply Voltage  
Ambient Operating  
Temperature  
Symbol  
Condition / Description  
Min  
3
Typ  
3.3  
Max  
3.6  
Unit  
V
3.3V ± 10%  
VDD  
TA  
-20  
+85  
°C  
Range  
Crystal Resonator  
Frequency  
Output Driver Load  
Capacitance  
FXIN  
CL  
12.75  
MHz  
pF  
15  
Crystal Specifications  
Fundamental AT cut parallel resonant crystal  
Nominal frequency  
12.75MHz  
Frequency tolerance  
Operating temperature range  
Storage temperature  
Load capacitance  
± 50 ppm or better at 25°C  
-20°C to +85°C  
-40°C to +85°C  
18pF  
Shunt capacitance  
ESR  
7pF maximum  
25 Ω  
Peak Reducing EMI Solution  
3 of 8  
ASM3P2110A  
November 2003  
rev 1.1  
DC Electrical Characteristics  
Parameter  
Symbol  
Conditions / Description  
Overall  
Min  
Typ  
Max  
Unit  
Supply Current,  
Dynamic  
VDD=3.3V, FCLK=12.75MHz,  
CL=15pF  
IDD  
43  
mA  
All input pins  
High-Level Input  
Voltage  
Low-Level Input  
Voltage  
High-Level Input  
Current  
VIH  
VIL  
IIH  
VDD=3.3V  
VDD=3.3V  
2.0  
VSS-0.3  
-1  
VDD+0.3  
0.8  
V
V
1
µA  
µA  
mA  
mA  
Low-Level Input  
Current (pull-up)  
High-Level Output  
Source Current  
Low-Level Output  
Source Current  
IIL  
-20  
-36  
21  
-80  
30  
IxOH  
IxOL  
VDD=V(XIN) = 3.3V, VO=0V  
10  
VDD=3.3V, V(XIN)=VO=5.5V  
Clock Outputs  
-10  
-21  
-30  
High-Level Output  
Source Current  
Low-Level Output  
Sink Current  
IOH  
IOL  
VO=2.4V  
-20  
23  
mA  
mA  
VO=0.4V  
ZOH  
ZOL  
VO=0.5VDD; output driving high  
Vo=0.5VDD; output driving low  
29  
27  
Output Impedance  
Peak Reducing EMI Solution  
4 of 8  
ASM3P2110A  
November 2003  
rev 1.1  
AC Electrical Characteristics  
Parameter  
Symbol  
Conditions/ Description  
VO = 0.3V to 3.0V;  
CL = 15pF  
Min  
Typ  
Max  
Unit  
Rise Time  
tr  
2.1  
ns  
VO = 3.0V to 0.3V;  
CL = 15pF  
Ratio of pulse width (as measured from  
rising edge to next falling edge at 2.5V)  
to one clock period  
Fall Time  
tf  
1.9  
ns  
%
Clock Duty  
Cycle  
45  
55  
On rising edges 500 µs apart at 2.5 V  
relative to an ideal clock, PLL B inactive *  
On rising edges 500 µs apart at 2.5 V  
relative to an ideal clock, PLL B active *  
From rising edge to next rising edge at  
2.5 V, PLL B inactive *  
45  
ps  
Jitter, Long  
Term  
Tj (LT)  
165  
110  
390  
ps  
Jitter, peak to  
peak  
Tj (T)  
From rising edge to next rising edge at  
2.5 V, PLL B active *  
* CL = 15 pF, Input clock frequency = 12.75 MHz, Output frequency = 51 MHz  
Peak Reducing EMI Solution  
5 of 8  
ASM3P2110A  
November 2003  
rev 1.1  
Package Information  
20-Pin SSOP package  
H
E
D
A
C
θ
e
D
A1  
L
B
Symbol  
Dimensions in inches  
Dimensions in millimeters  
Min  
Max  
Min  
1.35  
0.10  
0.20  
0.19  
8.56  
3.81  
Max  
1.75  
0.25  
0.30  
0.25  
8.74  
3.99  
A
A1  
B
C
D
E
e
0.053  
0.004  
0.008  
0.007  
0.337  
0.150  
0.069  
0.010  
0.012  
0.010  
0.344  
0.157  
0.025 BSC  
0.635BSC  
H
L
0.228  
0.016  
0°  
0.244  
0.050  
8°  
5.79  
0.41  
0°  
6.20  
1.27  
8°  
θ
Peak Reducing EMI Solution  
6 of 8  
ASM3P2110A  
November 2003  
rev 1.1  
Ordering Codes  
Part number  
Package Configuration  
20-pin SSOP TUBE  
Temperature Range  
ASM3P2110AF-20-JT  
ASM3P2110AF-20-JR  
ASM3I2110AF-20-JT  
ASM3I2110AF-20-JR  
Commercial  
Commercial  
Industrial  
20-pin SSOP TAPE & REEL  
20-pin SSOP TUBE  
20-pin SSOP TAPE & REEL  
Industrial  
Ordering Information  
A S M 3 P 2 1 1 0 A F - 2 0 - J R  
OR - SOT23/T/R  
TT – TSSOP, TUBE  
TR – TSSOP, T/R  
QT - QFN, TUBE  
BT - BGA, TUBE  
BR – BGA, T/R  
ST – SOIC, TUBE  
SR - SOIC, T/R  
QR – QFN, T/R  
VT – TVSOP, TUBE  
VR – TVSOP, T/R  
JR – SSOP, T/R  
JT - SSOP, TUBE  
PIN COUNT  
Pb FREE  
PART NUMBER  
X = Automotive  
I = Industrial  
P or n/c = Commercial  
1 – reserved  
6 – power management  
7 – power management  
8 – power management  
9 – Hi performance  
0 - reserved  
2 - Non PLL based  
3 – EMI Reduction  
4 – DDR support products  
5 – STD Zero Delay Buffer  
Alliance Semiconductor Mixed Signal Product  
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.  
Peak Reducing EMI Solution  
7 of 8  
ASM3P2110A  
November 2003  
rev 1.1  
Alliance Semiconductor Corporation  
2575, Augustine Drive,  
Santa Clara, CA 95054  
Tel# 408-855-4900  
Copyright © Alliance Semiconductor  
All Rights Reserved  
Preliminary Information  
Part Number: ASM3P2110A  
Document Version: v1.1  
Fax: 408-855-4999  
www.alsc.com  
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Dan Hariton / Alliance Semiconductor, dated 11-11-2003  
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are  
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their  
respective companies. Alliance reserves the right to make changes to this document and its products at any time without  
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein  
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this  
data at any time, without notice. If the product described herein is under development, significant changes to these  
specifications are possible. The information in this product data sheet is intended to be general descriptive information for  
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or  
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product  
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products  
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual  
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).  
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of  
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any  
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical  
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant  
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer  
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.  
Peak Reducing EMI Solution  
8 of 8  

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