ASM5I2304AG-2H-08-SR [PULSECORE]
3.3V Zero Delay Buffer; 3.3V零延迟缓冲器
| 型号： | ASM5I2304AG-2H-08-SR |
| 厂家： | 
PulseCore Semiconductor |
| 描述： | 3.3V Zero Delay Buffer |
| 文件： | 总14页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2006
rev 1.5
ASM5P2304A
3.3V Zero Delay Buffer
Features
the REF pin. The PLL feedback is required to be driven to
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
than 250pS, and the output-to-output skew is guaranteed to
be less than 200pS.
•
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P2304A
Configurations Table”.
•
•
•
Input frequency range: 15MHz to 133MHz
Multiple low-skew outputs.
The ASM5P2304A has two banks of two outputs each.
Multiple ASM5P2304A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500pS.
•
•
•
Output-output skew less than 200pS.
Device-device skew less than 500pS.
Two banks of four outputs.
•
•
Less than 200pS Cycle-to-Cycle jitter
(-1, -1H, -2, -2H).
Available in space saving, 8 pin 150-mil SOIC
packages.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
The ASM5P2304A is available in two different
configurations (Refer “ASM5P2304A Configurations Table).
The ASM5P2304A-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2304A-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster.
•
•
•
Functional Description
The ASM5P2304A-2 allows the user to obtain REF and
1/2X or 2X frequencies on each output bank. The exact
configuration and output frequencies depend on which
output drives the feedback pin.
ASM5P2304A is
a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks in PC,
workstation, datacom, telecom and other high-performance
applications. It is available in 8 pin package. The part has
an on-chip PLL which locks to an input clock presented on
Block Diagram
FBK
CLKA1
PLL
REF
CLKA2
/2
CLKB1
CLKB2
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
ASM5P2304A Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P2304A-1
ASM5P2304A-1H
ASM5P2304A-2
ASM5P2304A-2
ASM5P2304A-2H
ASM5P2304A-2H
Bank A or Bank B
Bank A or Bank B
Bank A
Reference
Reference
Reference
Reference
Reference /2
Reference
Reference/2
Reference
Reference
Bank B
2 X Reference
Reference
Bank A
Bank B
2 X Reference
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
1000
500
0
5
-30
30
-25
10
15
20
25
-20
-15
-10
-5
0
-500
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
To close the feedback loop of the ASM5P2304A, the FBK
pin can be driven from any of the four available output
pins. The output driving the FBK pin will be driving a total
load of 7pF plus any additional load that it drives. The
relative loading of this output (with respect to the
remaining outputs) can adjust the input output delay. This
is shown in the above graph.
For applications requiring zero input-output delay, all
outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output-output skew, be sure to load
outputs equally.
3.3V Zero Delay Buffer
2 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Pin Configuration
8
7
6
FBK
REF 1
VDD
2
3
4
CLKA1
CLKA2
GND
CLKB2
5
CLKB1
Pin Description for ASM5P2304A
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF1
CLKA12
CLKA22
GND
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Ground
CLKB12
CLKB2 2
VDD
Buffered clock output, bank B
Buffered clock output, bank B
3.3V supply
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3V Zero Delay Buffer
3 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
-0.5
-0.5
-0.5
-65
+7.0
VDD + 0.5
7
V
V
V
Storage Temperature
+150
260
°C
°C
°C
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
2000
V
(As per JEDEC STD22- A114-B)
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P2304A Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
0
3.6
70
30
15
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, from 15MHz to 100MHz
Load Capacitance, from 100MHz to 133MHz
Input Capacitance3
°C
pF
pF
pF
CL
CL
CIN
Note:
3. Applies to both Ref Clock and FBK.
3.3V Zero Delay Buffer
4 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Electrical Characteristics for ASM5P2304A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
0.8
V
V
2.0
VIN = 0V
VIN = VDD
50.0
µA
µA
IIH
100.0
I
OL = 8mA (-1, -2)
VOL
Output LOW Voltage 4
Output HIGH Voltage 4
0.4
V
V
IOH = 12mA (-1H, -2H)
I
OL = -8mA (-1, -2)
VOH
2.4
IOH = -12mA (-1H, -2H)
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
45.0
IDD
Supply Current
mA
Unloaded outputs, 66MHz REF
(-1, -1H, -2, -2H)
32.0
18.0
Unloaded outputs, 33MHz REF
(-1, -1H, -2, -2H)
Note:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
5 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Switching Characteristics for ASM5P2304A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
1/t1
1/t1
Output Frequency
30pF load, -1H, -2H devices
15
15
133
133
MHz
MHz
Output Frequency
15pF load, -1, -2 devices
Duty Cycle5= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = 66.66MHz
30pF load
40.0
45.0
50.0
50.0
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
%
Duty Cycle5 = (t2 / t1) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, FOUT = <50MHz
15 pF load
%
Output Rise Time5
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
t3
t3
t3
t4
t4
t4
nS
nS
nS
nS
nS
nS
Output Rise Time5
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
Output Rise Time5
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
Output Fall Time5
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
Output-to-output skew on same bank (-1, -2)5
Output-to-output skew (-1H, -2H)
All outputs equally loaded
All outputs equally loaded
200
200
t5
pS
Output bank A -to- output bank B skew
(-1, -2H)
All outputs equally loaded
200
Output bank A to output Bank B skew (-2)
Delay, REF Rising Edge to FBK Rising Edge5
Device-to-Device Skew5
All outputs equally loaded
400
±250
500
t6
t7
Measured at VDD /2
0
0
pS
pS
Measured at VDD/2 on the FBK pins of the device
Measured between 0.8V and 2.0V using
Test Circuit #2
t8
Output Slew Rate5
1
V/nS
Measured at 66.67MHz, loaded outputs,
15pF load
175
200
Cycle-to-cycle jitter 5
(-1, -1H, -2H)
Measured at 66.67MHz, loaded outputs,
30pF load
tJ
pS
Measured at 25MHz, loaded outputs,
15pF load
100
400
375
Measured at 66.67MHz, loaded outputs, 30pF load
Cycle-to-cycle jitter 5
(-2)
tJ
pS
Measured at 66.67MHz, loaded outputs,
15pF load
Stable power supply, valid clock presented on REF
and FBK pins
tLOCK
PLL Lock Time 5
1.0
mS
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
6 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Operating Conditions for ASM5I2304A Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
-40
3.6
85
30
15
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, from 15MHz to 100MHz
Load Capacitance, from 100MHz to 133MHz
Input Capacitance6
°C
pF
pF
pF
CL
CL
CIN
Note:
6. Applies to both Ref Clock and FBK.
Electrical Characteristics for ASM5I2304A Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
Input LOW Voltage
0.8
V
V
Input HIGH Voltage
Input LOW Current
Input HIGH Current
2.0
VIN = 0V
VIN = VDD
50.0
µA
µA
IIH
100.0
I
OL = 8mA (-1, -2)
VOL
Output LOW Voltage 7
Output HIGH Voltage 7
0.4
V
V
IOH = 12mA (-1H, -2H)
I
I
OL = -8mA (-1, -2)
VOH
2.4
OH = -12mA (-1H, -2H)
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
45.0
35.0
20.0
Unloaded outputs, 66MHz REF
(-1, -2)
IDD
Supply Current
mA
Unloaded outputs, 33MHz REF
(-1, -2)
Note:
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
7 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Switching Characteristics for ASM5I2304A Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Output Frequency
Test Conditions
Min
Typ
Max
Unit
1/t1
1/t1
30pF load, -1H, -2H devices
15pF load, -1 and -2 devices
15
15
133
133
MHz
MHz
Output Frequency
Duty Cycle8 = (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <66.66MHz
30pF load
40.0
45.0
50.0
50.0
60.0
55.0
2.50
1.50
1.50
2.50
1.50
%
%
Duty Cycle8= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <50 MHz
15pF load
Output Rise Time8
(-1, -2)
Measured between 0.8V and 2.0V
30pF load
t3
t3
t3
t4
t4
t4
nS
nS
nS
nS
nS
nS
Output Rise Time8
(-1, -2)
Measured between 0.8V and 2.0V
15pF load
Output Rise Time8
(-1H, -2H)
Measured between 0.8V and 2.0V
30pF load
Output Fall Time8
(-1, -2)
Measured between 2.0V and 0.8V
30pF load
Output Fall Time8
(-1, -2)
Measured between 2.0V and 0.8V
15pF load
Output Fall Time8
(-1H, -2H)
Measured between 2.0V and 0.8V
30pF load
1.25
200
200
Output-to-output skew on same bank (-1, -2)8
All outputs equally loaded
All outputs equally loaded
Output-to-output skew
(-1H, -2H)
t5
pS
Output bank A -to- output bank B skew (-1, -2H)
Output bank A -to- output bank B skew (-2)
Delay, REF Rising Edge to FBK Rising Edge8
All outputs equally loaded
All outputs equally loaded
Measured at VDD /2
200
400
t6
t7
0
0
±250
pS
pS
Measured at VDD/2 on the FBK pins of the
device
Device-to-Device Skew8
Output Slew Rate8
500
Measured between 0.8V and 2.0V using
Test Circuit #2
t8
1
V/nS
Measured at 66.67MHz, loaded outputs,
15pF load
180
200
100
400
380
1.0
Cycle-to-cycle jitter 8
(-1, -1H, -2H)
Measured at 66.67MHz, loaded outputs,
30pF load
tJ
pS
Measured at 25MHz, loaded outputs,
15pF load
Measured at 66.67MHz, loaded outputs,
30pF load
Cycle-to-cycle jitter8
(-2)
tJ
pS
Measured at 66.67MHz, loaded outputs,
15pF load
Stable power supply, valid clock presented
on REF and FBK pins
tLOCK
PLL Lock Time8
mS
Note: 8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
8 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
2.0 V
0.8 V
0.8 V
OUTPUT
t4
t3
Output - Output Skew
1.4 V
OUTPUT1
1.4 V
OUTPUT2
t
5
Input - Output Propagation Delay
VDD /2
INPUT
VDD /2
OUTPUT
t6
Device - Device Skew
VDD /2
CLKOUT, Device 1
VDD /2
CLKOUT, Device 2
t7
3.3V Zero Delay Buffer
9 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Test Circuits
TEST CIRCUIT #1
+3.3V
CLOAD
OUTPUT
VDD
0.1uF
GND
TEST CIRCUIT # 2
1KΩ
1KΩ
+3.3V
OUTPUT
VDD
CLOAD
10pF
0.1uF
GND
For parameter t8 (output skew rate) on -1H devices
3.3V Zero Delay Buffer
10 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
0.010
0.069
0.059
0.020
0.010
Min
0.10
1.35
1.25
0.31
0.18
Max
0.25
1.75
1.50
0.51
0.25
A1
A
0.004
0.053
0.049
0.012
0.007
A2
B
C
D
E
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
e
H
L
0.016
0°
0.050
8°
0.41
0°
1.27
8°
θ
3.3V Zero Delay Buffer
11 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Ordering Codes
Ordering Code
Marking
Package Type
Temperature
ASM5P2304AF-1-08-SR
ASM5P2304AF-1-08-ST
ASM5I2304AF-1-08-SR
ASM5I2304AF-1-08-ST
ASM5P2304AF-1H-08-SR
ASM5P2304AF-1H-08-ST
ASM5I2304AF-1H-08-SR
ASM5I2304AF-1H-08-ST
ASM5P2304AF-2-08-SR
ASM5P2304AF-2-08-ST
ASM5I2304AF-2-08-SR
ASM5I2304AF-2-08-ST
ASM5P2304AF-2H-08-SR
ASM5P2304AF-2H-08-ST
ASM5I2304AF-2H-08-SR
ASM5I2304AF-2H-08-ST
ASM5P2304AG-1-08-SR
ASM5P2304AG-1-08-ST
ASM5I2304AG-1-08-SR
ASM5I2304AG-1-08-ST
ASM5P2304AG-1H-08-SR
ASM5P2304AG-1H-08-ST
ASM5I2304AG-1H-08-SR
ASM5I2304AG-1H-08-ST
ASM5P2304AG-2-08-SR
ASM5P2304AG-2-08-ST
ASM5I2304AG-2-08-SR
ASM5I2304AG-2-08-ST
ASM5P2304AG-2H-08-SR
ASM5P2304AG-2H-08-ST
ASM5I2304AG-2H-08-SR
ASM5I2304AG-2H-08-ST
5P2304AF-1
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
5P2304AF-1
5I2304AF-1
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
5I2304AF-1
Industrial
5P2304AF-1H
5P2304AF-1H
5I2304AF-1H
5I2304AF-1H
5P2304AF-2
5P2304AF-2
5I2304AF-2
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free, Pb free
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
5I2304AF-2
Industrial
5P2304AF-2H
5P2304AF-2H
5I2304AF-2H
5I2304AF-2H
5P2304AG-1
5P2304AG-1
5I2304AG-1
5I2304AG-1
5P2304AG-1H
5P2304AG-1H
5I2304AG-1H
5I2304AG-1H
5P2304AG-2
5P2304AG-2
5I2304AG-2
5I2304AG-2
5P2304AG-2H
5P2304AG-2H
5I2304AG-2H
5I2304AG-2H
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
3.3V Zero Delay Buffer
12 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Device Ordering Information
A S M 5 P 2 3 0 4 A F - 0 8 - S R
R = Tape & Reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V Zero Delay Buffer
13 of 14
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.5
ASM5P2304A
Copyright © PulseCore Semiconductor
All Rights Reserved
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Part Number: ASM5P2304A
Document Version: 1.5
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or
correct this data at any time, without notice. If the product described herein is under development, significant changes to
these specifications are possible. The information in this product data sheet is intended to be general descriptive
information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to
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from such use.
3.3V Zero Delay Buffer
14 of 14
Notice: The information in this document is subject to change without notice.
相关型号：
ASM5I2304AG-5H-08-SR
PLL Based Clock Driver, 2304 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8
PULSECORE
ASM5I2304AG-5H-08-ST
PLL Based Clock Driver, 2304 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8
PULSECORE
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