ASM5P2304AF-5H-08-SR [PULSECORE]
2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, SOIC-8;
| 型号： | ASM5P2304AF-5H-08-SR |
| 厂家： | 
PulseCore Semiconductor |
| 描述： | 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, SOIC-8 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总14页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2005
rev 3.16
ASMP5P2304A
3.3 V Zero Delay Buffer
Features
than 250ps, and the output-to-output skew is guaranteed to
be less than 200ps.
.
Zero input - output propagation delay,
adjustable by capacitive load on FBK input.
Multiple configurations - Refer
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Input frequency range: 10MHz to 133MHz
Multiple low-skew outputs.
Output-output skew less than 200 ps.
Device-device skew less than 500 ps.
Two banks of four outputs.
.
The ASM5P2304A has two banks of two outputs each.
Multiple ASM5P2304A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500ps.
.
.
.
.
.
.
Less than 200 ps cycle-to-cycle jitter (-1, -1H,
-5H).
The ASM5P2304A is available in two different
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ꢒꢑꢘꢉꢩꢐꢚꢞꢉꢍꢒꢔꢓꢘꢑꢙ
.
Available in space saving, 8-pin 150-mil
SOIC packages.
.
.
.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
Functional Description
ASM5P2304A is versatile, 3.3V zero-delay buffer
a
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designed to distribute high-speed clocks in PC,
workstation, datacom, telecom and other high-performance
applications. It is available in a 8-pin package. The part has
an on-chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
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ꢋꢌꢉꢖꢋꢓꢞꢉꢖꢒꢌꢦꢔ
Block Diagram
FBK
CLKA1
PLL
REF
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
June 2005
ASM5P2304A
rev 3.16
ASM5P2304A Configurations
Device
Feedback From
Bank A or Bank B Reference
Bank A or Bank B Reference
Bank A Frequency
Bank B Frequency
Reference
ASM5P2304A-1
ASM5P2304A-1H
ASM5P2304A-2
ASM5P2304A-2
ASM5P2304A-5H
Reference
Bank A
Bank B
Reference
Reference /2
Reference
2 X Reference
Bank A or Bank B Reference /2
Reference /2
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
1000
500
0
5
-30
30
-25
10
15
20
25
-20
-15
-10
-5
0
-500
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
For applications requiring zero input-output delay, all
outputs including the one providing feedback should
be equally loaded. If input-output delay adjustments
are required, use the above graph to calculate
loading differences between the feedback output and
remaining outputs. For zero output-output skew, be
sure to load outputs equally.
To close the feedback loop of the ASM5P2304A, the
FBK pin can be driven from any of the four available
output pins. The output driving the FBK pin will be
driving a total load of 7 pF plus any additional load
that it drives. The relative loading of this output (with
respect to the remaining outputs) can adjust the input
output delay. This is shown in the above graph.
3.3 Zero Delay Buffer
2 of 14
June 2005
ASM5P2304A
rev 3.16
Pin Configuration
1
REF
CLKA1
CLKA2
GND
8
FBK
VDD
2
3
4
7
6
ASM5P2304A
CLKB2
CLKB1
5
Pin Description for ASM5P2304A
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF1
CLKA12
CLKA22
GND
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Ground
CLKB12
CLKB2 2
VDD
Buffered clock output, bank B
Buffered clock output, bank B
3.3V supply
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3 Zero Delay Buffer
3 of 14
June 2005
ASM5P2304A
rev 3.16
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
-0.5
-0.5
-0.5
-65
+7.0
VDD + 0.5
7
V
V
V
Storage Temperature
+150
260
C
C
C
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
>2000
V
(per MIL-STD-883, Method 3015)
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute
maximum ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P2304A Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
0
3.6
70
30
15
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance3
ûC
pF
pF
pF
CL
CL
CIN
Note:
3. Applies to both Ref Clock and FBK.
3.3 Zero Delay Buffer
4 of 14
June 2005
ASM5P2304A
rev 3.16
Electrical Characteristics
for ASM5P2304A Commercial Temperature Devices
Test Conditions
Parameter
Description
Input LOW Voltage
Min
Max
Unit
VIL
VIH
IIL
0.8
V
V
Input HIGH Voltage
Input LOW Current
Input HIGH Current
2.0
VIN = 0V
VIN = VDD
50.0
µA
µA
IIH
100.0
IOL = 8mA (-1, -2)
VOL
Output LOW Voltage 4
Output HIGH Voltage 4
0.4
V
V
IOH = 12mA (-1H, -5H)
IOL = -8mA (-1, -2)
VOH
2.4
IOH = -12mA (-1H, -5H)
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
45.0
IDD
Supply Current
mA
Unloaded outputs, 66MHz REF
(-1, -2)
32.0
18.0
Unloaded outputs, 33MHz REF
(-1, -2)
Note:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 Zero Delay Buffer
5 of 14
June 2005
ASM5P2304A
rev 3.16
Switching Characteristics for ASM5P2304A Commercial Temperature Devices
Paramete
Description
Test Conditions
Min
Typ
Max
Unit
r
t1
t1
t1
Output Frequency
30-pF load, All devices
10
10
10
100
MHz
MHz
MHz
Output Frequency
Output Frequency
20-pF load, -1H, -5H devices
15-pF load, -1, -2 devices
133.3
133.3
Duty Cycle 4= (t2 / t1) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, FOUT = 66.66 MHz
30-pF load
40.0
45.0
50.0
50.0
60.0
55.0
2.20
1.50
1.50
2.20
1.50
%
%
Duty Cycle 4 = (t2 / t1) * 100
(-1, -2,-1H, -5H)
Measured at 1.4V, FOUT = <50 MHz
15-pF load
Output Rise Time 4
(-1, -2)
Measured between 0.8V and 2.0V
30-pF load
t3
t3
t3
t4
t4
t4
ns
ns
ns
ns
ns
ns
Output Rise Time 4
(-1, -2)
Measured between 0.8V and 2.0V
15-pF load
Output Rise Time 4
(-1H, -5H)
Measured between 0.8V and 2.0V
30-pF load
Output Fall Time 4
(-1, -2)
Measured between 2.0V and 0.8V
30-pF load
Output Fall Time 4
(-1, -2)
Measured between 2.0V and 0.8V
15-pF load
Output Fall Time 4
(-1H, -5H)
Measured between 2.0V and 0.8V
30-pF load
1.25
200
200
Output-to-output skew on same bank (-1, -2) 4
All outputs equally loaded
All outputs equally loaded
Output-to-output skew
(-1H, -5H)
t5
ps
Output bank A -to- output bank B skew (-1, -
5H)
All outputs equally loaded
200
Output bank A to output bank b skew (-2)
Delay, REF Rising Edge to FBK Rising Edge 3
Device-to-Device Skew 4
All outputs equally loaded
400
±250
500
t6
t7
Measured at VDD /2
0
0
ps
ps
Measured at VDD/2 on the FBK pins of the device
Measured between 0.8V and 2.0V using
Test Circuit #2
t8
Output Slew Rate4
1
V/ns
Measured at 66.67 MHz, loaded outputs,
15 pF load
175
200
100
400
375
1.0
Cycle-to-cycle jitter 4
(-1, -1H, -5H)
Measured at 66.67 MHz, loaded outputs,
30 pF load
tJ
ps
Measured at 133.3 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs, 30pF
load
Cycle-to-cycle jitter 4
(-2,)
tJ
ps
Measured at 66.67 MHz, loaded outputs,
15 pF load
Stable power supply, valid clock presented on
REF and FBK pins
tLOCK
PLL Lock Time 4
ms
3.3 Zero Delay Buffer
6 of 14
June 2005
rev 3.16
ASM5P2304A
Operating Conditions for ASM5I2304A Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
-40
3.6
85
30
15
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance3
ûC
pF
pF
pF
CL
CL
CIN
Electrical Characteristics for ASM5I2304A Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
0.8
V
V
2.0
VIN = 0V
50.0
µA
µA
IIH
VIN = VDD
100.0
0.4
IOL = 8mA (-1, -2)
VOL
Output LOW Voltage 4
Output HIGH Voltage 4
V
V
IOH = 12mA (-1H, -5H)
IOL = -8mA (-1, -2)
VOH
2.4
IOH = -12mA (-1H, -5H)
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
45.0
IDD
Supply Current
mA
Unloaded outputs, 66MHz REF
(-1, -2)
35.0
20.0
Unloaded outputs, 33MHz REF
(-1, -2)
3.3 Zero Delay Buffer
7 of 14
June 2005
ASM5P2304A
rev 3.16
Switching Characteristics for ASM5I2304A Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Test Conditions
30-pF load, All devices
Min
Typ
Max
Unit
t1
t1
t1
Output Frequency
Output Frequency
Output Frequency
10
10
10
100
MHz
MHz
MHz
20-pF load, -1H, -5H devices
15-pF load, -1 and -2 devices
133.3
133.3
Duty Cycle 4 = (t2 / t1) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, FOUT = <66.66 MHz
30-pF load
40.0
45.0
50.0
50.0
60.0
55.0
2.50
1.50
1.50
2.50
1.50
%
%
Duty Cycle 4= (t2 / t1) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, FOUT = <50 MHz
15-pF load
Output Rise Time 4
(-1, -2)
Measured between 0.8V and 2.0V
30-pF load
t3
t3
t3
t4
t4
t4
ns
ns
ns
ns
ns
ns
Output Rise Time 4
(-1, -2)
Measured between 0.8V and 2.0V
15-pF load
Output Rise Time 4
(-1H, -5H)
Measured between 0.8V and 2.0V
30-pF load
Output Fall Time 4
(-1, -2)
Measured between 2.0V and 0.8V
30-pF load
Output Fall Time 4
(-1, -2)
Measured between 2.0V and 0.8V
15-pF load
Output Fall Time 4
(-1H, -5H)
Measured between 2.0V and 0.8V
30-pF load
1.25
200
200
Output-to-output skew on same bank (-1, -2) 4
All outputs equally loaded
All outputs equally loaded
Output-to-output skew
(-1H, -5H)
t5
ps
Output bank A -to- output bank B skew (-1, -5H)
Output bank A -to- output bank B skew (-2)
Delay, REF Rising Edge to FBK Rising Edge 4
Device-to-Device Skew 4
All outputs equally loaded
200
400
All outputs equally loaded
t6
t7
Measured at VDD /2
0
0
±250
500
ps
ps
Measured at VDD/2 on the FBK pins of the device
Measured between 0.8V and 2.0V using
Test Circuit #2
t8
Output Slew Rate4
1
V/ns
Measured at 66.67 MHz, loaded outputs,
15 pF load
180
200
Cycle-to-cycle jitter 4
(-1, -1H, -5H)
Measured at 66.67 MHz, loaded outputs,
30 pF load
tJ
ps
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
400
380
Measured at 66.67 MHz, loaded outputs, 30pF load
Cycle-to-cycle jitter 4
(-2)
tJ
ps
Measured at 66.67 MHz, loaded outputs,
15 pF load
Stable power supply, valid clock presented on REF
and FBK pins
tLOCK
PLL Lock Time 4
1.0
ms
3.3 Zero Delay Buffer
8 of 14
June 2005
rev 3.16
ASM5P2304A
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
2.0 V
0.8 V
OUTPUT
0.8 V
t4
t3
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
/2
V
DD
INPUT
/2
V
DD
OUTPUT
t6
Device - Device Skew
/2
V
DD
FBK, Device 1
FBK, Device 2
/2
V
DD
t7
3.3 Zero Delay Buffer
9 of 14
June 2005
ASM5P2304A
rev 3.16
Test Circuits
Test Circuit #2
Test Circuit #1
V
V
V
V
1k
DD
DD
OUTPUTS
GND
OUTPUTS
0.1 ÿF
0.1 ÿF
0.1 ÿF
0.1 ÿF
1k
C
10 pF
LOAD
DD
DD
GND
GND
GND
For parameter 8t (output slew rate) on -1H devices
3.3 Zero Delay Buffer
10 of 14
June 2005
ASM5P2304A
rev 3.16
Package Information: 8-lead (150 Mil) Molded SOIC
H
E
D
A
C
D
e
A1
L
B
Dimensions in
millimeters
Dimensions in inches
Symbo
l
Min
Max
Min
Max
A
A1
B
0.053
0.004
0.013
0.007
0.188
0.150
0.228
0.069
0.010
0.022
0.012
0.197
0.158
0.244
1.35
0.10
0.33
0.18
4.78
3.80
5.80
1.75
0.25
0.53
0.27
5.00
4.01
6.20
C
D
E
H
e
0.050 BSC
1.27 BSC
L
0.016
0.035
0.40
0.89
ꢇꢯ
ꢰꢯ
ꢇꢯ
ꢰꢯ
3.3 Zero Delay Buffer
11 of 14
June 2005
rev 3.16
ASM5P2304A
Ordering Code
Package Type
Operating Range
ASM5P2304A-1-08-SR
ASM5P2304A-1-08-ST
ASM5I2304A-1-08-SR
ASM5I2304A-1-08-ST
ASM5P2304A-1H-08-SR
ASM5P2304A-1H-08-ST
ASM5I2304A-1H-08-SR
ASM5I2304A-1H-08-ST
ASM5P2304A-2-08-SR
ASM5P2304A-2-08-ST
ASM5I2304A-2-08-SR
ASM5I2304A-2-08-ST
ASM5P2304A-5H-08-SR
ASM5P2304A-5H-08-ST
ASM5I2304A-5H-08-SR
ASM5I2304A-5H-08-ST
ASM5P2304AG-1-08-SR
ASM5P2304AG-1-08-ST
ASM5I2304AG-1-08-SR
ASM5I2304AG-1-08-ST
ASM5P2304AG-1H-08-SR
ASM5P2304AG-1H-08-ST
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial
Commercial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial
Industrial
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Commercial -GREEN
Commercial -GREEN
Industrial -GREEN
Industrial -GREEN
Commercial -GREEN
Commercial -GREEN
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
3.3 Zero Delay Buffer
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June 2005
ASM5P2304A
rev 3.16
ASM5I2304AG-1H-08-SR
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
Industrial -GREEN
ASM5I2304AG-1H-08-ST
ASM5P2304AG-2-08-SR
ASM5P2304AG-2-08-ST
ASM5I2304AG-2-08-SR
ASM5I2304AG-2-08-ST
ASM5P2304AG-5H-08-SR
ASM5P2304AG-5H-08-ST
ASM5I2304AG-5H-08-SR
ASM5I2304AG-5H-08-ST
Industrial -GREEN
Commercial -GREEN
Commercial -GREEN
Industrial -GREEN
Industrial -GREEN
Commercial -GREEN
Commercial -GREEN
Industrial -GREEN
Industrial -GREEN
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
8-pin 150-mil SOIC-TAPE & REEL
8-pin 150-mil SOIC-TUBE
ꢱꢋꢓꢘꢲꢉ ꢀꢳꢳꢉ“ꢉꢴꢑꢘꢘꢌꢉ“ꢉꢥꢘꢨꢎꢚꢘꢔꢉꢒꢑꢘꢉꢍꢐꢗꢗꢵꢉꢜꢋꢧꢁꢉꢚꢋꢩꢡꢗꢎꢒꢌꢓ
Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920.
Preliminary datasheet. Specification subject to change without notice.
3.3 Zero Delay Buffer
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June 2005
rev 3.16
ASM5P2304A
Package Suffix & T/R - Tube/Tray designators
ASM5P2304A F - 08- O R
R = Tape & reel, T = Tube or Tray
O = SOTTSOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
Q = QFN
F = Lead free and RoHS compliant part
G = Green package
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
1 = reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management * * *
7 = Power Management * * *
8 = Power Management * * *
9 = Hi Performance
0 = reserved
Alliance Semiconductor
Mixed Signal Product
* * * NOTE: Industry Standard Part Numbers May Be used
That Differ from this part numbering system...
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5P2304A
Document Version: 3.16
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3 Zero Delay Buffer
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相关型号：
ASM5P2304AF-5H-08-ST
2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, SOIC-8
PULSECORE
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