ASM5P23SS05A-1-08-ST [PULSECORE]
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8;
| 型号： | ASM5P23SS05A-1-08-ST |
| 厂家： | 
PulseCore Semiconductor |
| 描述： | PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8 光电二极管 |
| 文件： | 总15页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASMP5P23SS09A
ASMP5P23SS05A
November 2003
rev 1.1
3.3V Peak Reducing Zero Delay Buffer
General Features
typically 1000 times slower than the fundamental clock, the
spread spectrum process has negligible impact on system
performance while giving significant cost savings. Alliance
offers options with different spreading patterns with more
spread and greater EMI reduction.
10 MHz to 133- MHz operating range, compatible
with CPU and PCI bus frequencies.
•
EMI reduced output with on-chip EMI reduction
capability.
•
•
Zero input - output propagation delay.
Multiple low-skew outputs.
The -1H version of the ASM5P23SXXA operates at up to
133- MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
•
•
•
Output-output skew less than 250 ps.
Device-device skew less than 700 ps.
One input drives 9 outputs, grouped as 4 + 4 + 1
(ASM5P23SS09A).
One input drives 5 outputs (ASM5P23SS05A).
•
•
•
•
Less than 200 ps cycle-to-cycle jitter is compatible with
The ASM5P23SS09A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Pentium® based systems.
Test Mode to bypass PLL (ASM5P23SS09A only, refer
Select Input Decoding Table).
Available in 16-pin, 150-mil SOIC, 4.4 mm TSSOP,
and 150-mil SSOP packages (ASM5P23SS09A) or in
8-pin, 150-mil SOIC package (ASM5P23SS05A).
3.3V operation, advanced 0.35µ CMOS technology.
•
Multiple ASM5P23SS09A and ASM5P23SS05A devices
can accept the same input clock and distribute it. In this
case the skew between the outputs of the two devices is
guaranteed to be less than 700ps. All outputs have less
than 200 ps of cycle-to-cycle jitter. The input and output
propagation delay is guaranteed to be less than 250 ps,
and the output to output skew is guaranteed to be less than
250ps.
Functional Description
ASM5P23SS09A is a versatile, spread spectrum output,
3.3V zero-delay buffer designed to distribute high-speed
clocks with EMI suppression capability. It is available in a
16-pin package. The ASM5P23SS05A is the eight-pin
version of the ASM5P23SS09A. It accepts one reference
input and drives out five low-skew clocks. The
ASM5P23SXXA family incorporates the latest advances in
PLL spread spectrum techniques to greatly reduce the
peak EMI by modulating the output frequency with a low
frequency carrier. The ASM5P23SXXA allows significant
system cost savings by reducing the number of circuit
board layers and shielding that are traditionally required to
pass EMI regulations. Because the modulating frequency is
The ASM5P23SS09A and the ASM5P23SS05A are
available in two different configurations, as shown in the
ordering information table. The ASM5P23SXXA-1 is the
base part. The ASM5P23SXXA-1H is the high drive version
of the -1 and its rise and fall times are much faster than -1
part.
Peak Reducing
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
PLL
Block Diagram
REF
Peak Reducing
CLKOUT
REF
PLL
CLK1
CLK2
CLK3
CLK4
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
S2
S1
Select Input
Decoding
ASM5P23SS05A
ASM5P23SS09A
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASMP5P23SS09A
ASMP5P23SS05A
November 2003
rev 1.1
Select Input Decoding for ASM5P23SS09A
S2
S1
Clock A1 - A4
Clock B1 - B4
CLKOUT 1
Output Source
PLL
Shut-Down
0
0
1
0
1
Three-state
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
PLL
PLL
N
N
Y
N
0
1
1
Driven
Reference
PLL
Driven
Driven
Notes:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to
change the skew between the reference and the output.
wave is composed of fundamental frequency and
Zero Delay and Skew Control
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of EMI.
Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as the
frequency increases. The standard methods of reducing
EMI are to use shielding, filtering, multi- layer-PCBs etc.
These methods are expensive. Spread spectrum clocking
reduces the peak energy by reducing the Q factor of the
clock. This is done by slowly modulating the clock freqency.
The ASM5P23SXXA uses the center modulation spread
spectrum technique in which the modulated output
frequency varies above and below the reference frequency
with a specified modulation rate. With center modulation,
the average frequency is the same as the unmodulated
frequency and there is no performance degradation
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Pin Configuration
1
2
REF
16 CLKOUT
CLKA1
15
CLKA4
CLKA2
VDD
3
4
5
6
14
13
CLKA3
VDD
ASM5P23SS09A
GND
12 GND
CLKB1
11
CLKB4
7
8
10
9
CLKB2
S2
CLKB3
S1
CLKOUT
8
7
6
1
REF
2
CLK2
CLK4
VDD
ASM5P23SS05A
CLK1
GND
3
4
CLK3
5
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Pin Description for ASM5P23SS09A
Pin #
Pin Name
Description
1
2
REF2
CLKA13
CLKA23
VDD
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
3
4
5
GND
Ground
6
CLKB13
CLKB2 3
S2 4
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
7
8
9
S1 4
Select input, bit 1
10
11
12
13
14
15
16
CLKB3 3
CLKB4 3
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
VDD
3.3V supply
CLKA3 3
CLKA4 3
CLKOUT3
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
Pin Description for ASM5P23SS05A
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF2
CLK2 3
CLK13
GND
CLK3 3
VDD
Input reference frequency, 5V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
CLK43
CLKOUT 3
Buffered clock output
Buffered clock output, internal feedback on this pin
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
-0.5
-0.5
-0.5
-65
+7.0
VDD + 0.5
7
V
V
V
Storage Temperature
+150
260
°C
°C
°C
V
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
2000
(per MIL-STD-883, Method 3015)
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P23SS05A and ASM5P23SS09A - Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
0
3.6
70
30
10
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
°C
pF
pF
pF
CL
CL
CIN
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Electrical Characteristics for ASM5P23SS05A and ASM5P23SS09A - Commercial Temperature Devices
Parameter
VIL
Description
Input LOW Voltage 5
Input HIGH Voltage 5
Input LOW Current
Input HIGH Current
Output LOW Voltage 6
Test Conditions
Min
Max
Unit
0.8
V
V
VIH
IIL
2.0
VIN = 0V
50.0
100.0
0.4
µA
µA
V
IIH
VIN = VDD
VOL
IOL = 8mA (-1)
IOH = 12mA (-1H)
VOH
IDD
Output HIGH Voltage 6
Supply Current
IOL = -8mA (-1)
2.4
V
IOH = -12mA (-1H)
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
TBD
mA
Switching Characteristics for ASM5P23SS05A-1 and ASM5P23SS09A-1 - Commercial Temperature
Devices7
Parameter
Description
Output Frequency
Test Conditions
Min
Typ
Max
Unit
1/t1
30-pF load
10-pF load
10
10
100
133.3 3
60.0
MHz
Duty Cycle 6 = (t2 / t1) * 100
Output Rise Time 6
Output Fall Time 6
Output-to-output skew 6
Delay, REF Rising Edge to
CLKOUT Rising Edge 6
Device-to-Device Skew 6
Measured at 1.4V, FOUT = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
40.0
50.0
%
ns
ns
ps
ps
t3
t4
t5
t6
2.50
2.50
250
Measured at VDD /2
0
0
±350
t7
Measured at VDD/2 on the CLKOUT pins of
the device
700
ps
tJ
Cycle-to-cycle jitter 6
PLL Lock Time 6
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
200
1.0
ps
tLOCK
ms
Notes:
5. REF input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. All parameters specified with loaded outputs.
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Switching Characteristics for ASM5I23SS05A-1H and ASM5I23SS09A-1H - Industrial Temperature
Devices7
Parameter
Description
Output Frequency
Test Conditions
Min
Typ
Max
Unit
1/t1
30-pF load
10-pF load
10
10
100
133.3 3
60.0
MHz
Duty Cycle 6 = (t2 / t1) * 100
Output Rise Time 6
Output Fall Time 6
Output-to-output skew 6
Delay, REF Rising Edge to
CLKOUT Rising Edge 6
Device-to-Device Skew 6
Measured at 1.4V, FOUT = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
40.0
50.0
%
ns
ns
ps
ps
t3
t4
t5
t6
2.50
2.50
250
Measured at VDD /2
0
0
±350
t7
Measured at VDD/2 on the CLKOUT pins of
the device
700
ps
tJ
Cycle-to-cycle jitter 6
PLL Lock Time 6
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
200
1.0
ps
tLOCK
ms
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4 V
1.4 V
1. 4 V
All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
2. 0 V
0.8 V
0.8 V
OUTPUT
t4
t3
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
VDD /2
INPUT
VDD /2
OUTPUT
t6
Device - Device Skew
VDD /2
CLKOUT, Device 1
VDD /2
CLKOUT, Device 2
t7
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Test Circuits
Test Circuit #2
Test Circuit #1
VDD
VDD
1k
Ω
CLK OU T
OUTPUTS
GND
OUTPUTS
0.1 µF
0.1 µF
0.1 µF
1k
Ω
CLOAD
10 pF
VDD
VDD
GND
GND
GND
0.1 µF
For parameter t8 (output slew rate) on -1H devices
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Package Information: 8-lead (150-mil) SOIC
H
E
D
A2
A
C
θ
e
A1
L
B
Symbol Dimensions in inches
Dimensions in
millimeters
Min
Max
0.071
0.010
0.069
0.020
0.01
Min
1.45
0.10
1.35
0.31
0.10
4.72
3.75
Max
1.80
0.25
1.75
0.51
0.25
5.12
4.15
A
A1
A2
B
C
D
E
0.057
0.004
0.053
0.012
0.004
0.186
0.148
0.202
0.164
e
0.050 BSC
1.27 BSC
H
L
0.224
0.012
0°
0.248
0.028
8°
5.70
0.30
0°
6.30
0.70
8°
θ
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
10 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Package Information: 16-lead (150 Mil) Molded SOIC
PIN 1 ID
1
8
H
E
9
16
h
D
Seating Plane
A2
A
C
θ
0.004
e
L
A1
B
DIMENSIONS
INCHES
MILLIMETERS
MIN
0.061
0.004
0.055
0.013
0.0075
0.386
0.150
MAX
MIN
1.55
0.102
1.40
0.33
0.191
9.80
3.81
MAX
1.73
0.249
1.55
0.49
0.249
9.98
3.99
A
A1
A2
B
C
D
E
0.068
0.0098
0.061
0.019
0.0098
0.393
0.157
e
0.050 BSC
1.27 BSC
H
h
L
0.230
0.010
0.016
0°
0.244
0.016
0.035
8°
5.84
0.25
0.41
0°
6.20
0.41
0.89
8°
θ
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Package Information: 16-lead Thin Shrunk Small Outline Package (4.40-MM Body)
1
8
PIN 1 ID
E
H
9
16
A
Seating Plane
C
θ
A2
A1
e
B
L
D
DIMENSIONS (inches)
DIMENSIONS (mm)
MIN
MAX
0.043
0.006
0.37
0.012
0.008
2.008
0.177
MIN
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
A
A1
A2
B
C
D
E
0.002
0.003
0.007
0.004
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
e
0.026 BSC
0.65 BSC
H
L
0.246
0.020
0°
0.256
0.028
8°
6.25
0.50
0°
6.50
0.70
8°
θ
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
12 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Package Information: 16-lead (150-mil) SSOP
8
1
PIN 1 ID
E
H
16
9
D
A
Seating Plane
C
θ
0.004
A1
B
L
e
DIMENSIONS (inches)
DIMENSIONS (millimeters)
MIN
MAX
0.065
0.010
0.012
0.010
0.197
0.157
MIN
1.245
0.102
0.203
0.178
4.801
3.81
MAX
1.651
0.254
0.305
0.254
5.004
3.988
A
A1
B
C
D
E
e
0.049
0.004
0.008
0.007
0.189
0.150
0.025 BSC
0.635 BSC
H
L
0.228
0.016
0°
0.244
0.050
8°
5.791
0.406
0°
6.198
1.27
8°
θ
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
13 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Ordering Codes
Ordering Code
Package Type
Operating Range
ASM5P23SS09A-1-16-ST
ASM5I23SS09A-1-16-ST
ASM5P23SS09A-1-16-SR
ASM5I23SS09A-1-16-SR
ASM5P23SS09A-1-16-TT
ASM5I23SS09A-1-16-TT
ASM5P23SS09A-1-16-TR
ASM5I23SS09A-1-16-TR
ASM5P23SS09A-1H-16-ST
ASM5I23SS09A-1H-16-ST
ASM5P23SS09A-1H-16-SR
ASM5I23SS09A-1H-16-SR
ASM5P23SS09A-1H-16-TT
ASM5I23SS09A-1H-16-TT
ASM5P23SS09A-1H-16-TR
ASM5I23SS09A-1H-16-TR
ASM5P23SS05A-1-08-ST
ASM5I23SS05A-1-08-ST
ASM5P23SS05A-1-08-SR
ASM5I23SS05A-1-08-SR
ASM5P23SS05A-1-08-TT
ASM5I23SS05A-1-08-TT
ASM5P23SS05A-1-08-TR
ASM5I23SS05A-1-08-TR
ASM5P23SS05A-1H-08-ST
ASM5I23SS05A-1H-08-ST
ASM5P23SS05A-1H-08-SR
ASM5I23SS05A-1H-08-SR
ASM5P23SS05A-1H-08-TT
ASM5I23SS05A-1H-08-TT
ASM5P23SS05A-1H-08-TR
ASM5I23SS05A-1H-08-TR
16-pin 150-mil SOIC-TUBE
Commercial
Industrial
16-pin 150-mil SOIC-TUBE
16-pin 150-mil SOIC-TAPE & REEL
16-pin 150-mil SOIC-TAPE & REEL
16-pin 4.4-mm TSSOP-TUBE
Commercial
Industrial
Commercial
Industrial
16-pin 4.4-mm TSSOP-TUBE
16-pin 4.4-mm TSSOP-TAPE & REEL
16-pin 4.4-mm TSSOP - TAPE & REEL
16-pin 150-mil SOIC-TUBE
Commercial
Industrial
Commercial
Industrial
16-pin 150-mil SOIC-TUBE
16-pin 150-mil SOIC-TAPE & REEL
16-pin 150-mil SOIC-TAPE & REEL
16-pin 4.4-mm TSSOP-TUBE
Commercial
Industrial
Commercial
Industrial
16-pin 4.4-mm TSSOP-TUBE
16-pin 4.4-mm TSSOP-TAPE & REEL
16-pin 4.4-mm TSSOP - TAPE & REEL
08-pin 150-mil SOIC-TUBE
Commercial
Industrial
Commercial
Industrial
08-pin 150-mil SOIC-TUBE
08-pin 150-mil SOIC-TAPE & REEL
08-pin 150-mil SOIC-TAPE & REEL
08-pin 4.4-mm TSSOP-TUBE
Commercial
Industrial
Commercial
Industrial
08-pin 4.4-mm TSSOP-TUBE
08-pin 4.4-mm TSSOP-TAPE & REEL
08-pin 4.4-mm TSSOP - TAPE & REEL
08-pin 150-mil SOIC-TUBE
Commercial
Industrial
Commercial
Industrial
08-pin 150-mil SOIC-TUBE
08-pin 150-mil SOIC-TAPE & REEL
08-pin 150-mil SOIC-TAPE & REEL
08-pin 4.4-mm TSSOP-TUBE
Commercial
Industrial
Commercial
Industrial
08-pin 4.4-mm TSSOP-TUBE
08-pin 4.4-mm TSSOP-TAPE & REEL
08-pin 4.4-mm TSSOP - TAPE & REEL
Commercial
Industrial
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
14 of 15
ASM5P23SS09A
ASM5P23SS05A
November 2003
rev 1.1
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM5P23SS09A
ASM5P23SS05A
Fax: 408-855-4999
www.alsc.com
Document Version: 1.1
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Dan Hariton / Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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3.3V Peak Reducing Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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ASM5P23SS05A-1-08-TR
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ASM5P23SS05A-1-08-TT
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ASM5P23SS05A-1H-08-SR
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ASM5P23SS05A-1H-08-TR
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ASM5P23SS08A-1-16-SR
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