PCC028-01BSC-1 [PULSECORE]
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16;
| 型号： | PCC028-01BSC-1 |
| 厂家： | 
PulseCore Semiconductor |
| 描述： | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2003
rev 1.1
PCC028-01B
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
General Features
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
40MHz to 100-/133MHz operating range,
compatible with CPU and PCI bus frequencies.
Zero input - output propagation delay
Multiple low-skew outputs
Output-output skew less than 250 ps
Device-device skew less than 700 ps
One input drives 9 outputs, grouped as 4 + 4
+ 1
The PCC028-01B PLL shuts down in one case as shown in
the Select Input Decoding Table. Multiple PCC028-01B
devices can accept the same input clock and distribute it. In
this case the skew between the outputs of the two devices
is guaranteed to be less than 700ps.
Less than 200 ps cycle-to-cycle jitter is compatible
with Pentium® based systems
Test Mode to bypass PLL
Available in 16-pin, 150-mil SOIC, 4.4 mm TSSOP
and 150-mil SSOP packages
All outputs have less than 200 ps of cycle-to-cycle jitter.
The input to output propagation delay is guaranteed to be
less than 350 ps, and the output to output skew is
guaranteed to be less than 250ps.
3.3V
operation,
advanced
0.35µ
CMOS
technology
‘SpreadTrak’.
Block Diagram
Functional Description
PLL
MUX
The PCC028-01B is a low-cost 3.3V zero delay buffer
designed to distribute high-speed clocks and is available in
a 16-pin SOIC package. All parts have on-chip PLLs that
lock to an input clock on the REF pin. The PLL feedback is
on-chip and is obtained from the CLKOUT pad.
CLKOUT
CLKA1
CLKA2
CLKA3
REF
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
S2
S1
Selec t In pu t
Decoding
The PCC028-01B has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
PCC028-01B
Select Input Decoding for PCC028-01B
S2
S1
Clock A1 - A4
Clock B1 - B4
CLKOUT 1
Output Source
PLL
Shut-Down
0
0
1
1
0
1
0
1
Three-state
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
PLL
PLL
N
N
Y
N
Driven
Reference
PLL
Driven
Driven
Notes:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to
change the skew between the reference and the output
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
PCC028-01B
Zero Delay and Skew Control
SpreadTrak
All outputs should be uniformly loaded to achieve Zero
Delay between the input and output. Since the CLKOUT
pin is the internal feedback to the PLL, its relative loading
can adjust the input-output delay.
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
PCC028-01B is designed so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it
exists. When a zero delay buffer is not designed to pass
the Spread Spectrum feature through, the result is a
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
Pin Configuration
1
2
16
15
14
13
12
11
10
9
REF
CL KA1
CLKA2
VD D
CLKOUT
CLKA4
CL KA3
3
4
VDD
PCC028-01B
GND
5
6
7
8
GND
CLKB1
CL KB4
CLK B3
S1
CL KB2
S2
Low-Cost 3.3V ‘SpreadTrak” Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 13
November 2003
rev 1.1
PCC028-01B
Pin Description
Pin #
Pin Name
Description
1
REF
CLKA1
CLKA2
VDD
Input reference frequency, 5V-tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
2
3
4
5
GND
Ground
6
CLKB1
CLKB2
S2 2
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
7
8
9
S1 2
Select input, bit 1
10
CLKB3
CLKB4
GND
Buffered clock output, bank B
Buffered clock output, bank B
Ground
11
12
13
14
VDD
3.3V supply
CLKA3
CLKA4
CLKOUT
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
15
16
Notes:
2. Weak pull-up on these inputs
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3
November 2003
rev 1.1
PCC028-01B
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
-0.5
-0.5
-0.5
-65
+7.0
VDD + 0.5
7
V
V
V
Storage Temperature
+150
260
°C
°C
°C
V
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
2000
(per MIL-STD-883, Method 3015)
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
ratings for prolonged periods can affect device reliability.
Operating Conditions for PCC028-01BSC-XX Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
0
3.6
70
V
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133MHz
Input Capacitance
°C
pF
pF
pF
CL
TBD
TBD
TBD
CL
CIN
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4
November 2003
PCC028-01B
rev 1.1
Electrical Characteristics for PCC028-01BSC-XX Commercial Temperature Devices
Parameter
Description
Input LOW Voltage 3
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
0.8
V
V
Input HIGH Voltage 3
Input LOW Current
Input HIGH Current
Output LOW Voltage 4
Output HIGH Voltage 4
Supply Current
2.0
VIN = 0V
50.0
100.0
0.4
µA
µA
V
IIH
VIN = VDD
IOL = 8mA
IOL = -8mA
VOL
VOH
IDD
2.4
V
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
32.0
mA
Switching Characteristics for PCC028-01BSC-1 Commercial Temperature Devices 5
Parameter
Description
Output Frequency
Test Conditions
Min
Typ
Max
Unit
1/t1
30-pF load
10-pF load
40
40
100
133.3 3
60.0
MHz
Duty Cycle 4= (t2 / t1) * 100
Rise Time 4
Fall Time 4
Output-to-output skew 4
Delay, REF Rising Edge to
CLKOUT Rising Edge 4
Device-to-Device Skew 4
Measured at 1.4V, FOUT = 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
40.0
50.0
%
ns
ns
ps
ps
t3
t4
t5
t6
2.50
2.50
250
Measured at VDD /2
0
0
±350
t7
t8
Measured at VDD/2 on the CLKOUT pins of
the device
700
ps
Output Slew Rate 5
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/ns
tJ
Cycle-to-cycle jitter 4
PLL Lock Time 4
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
200
1.0
ps
tLOCK
ms
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5
November 2003
rev 1.1
PCC028-01B
Switching Characteristics for PCC028-01BSC-1 Industrial Temperature Devices 5
Parameter
Description
Output Frequency
Test Conditions
Min
Typ
Max
Unit
1/t1
30-pF load
10-pF load
40
40
100
133.3
60.0
55.0
1.50
1.50
250
MHz
Duty Cycle 4= (t2 / t1) * 100
Duty Cycle 4= (t2 / t1) * 100
Rise Time 4
Measured at 1.4V, FOUT = 66.67 MHz
Measured at 1.4V, FOUT < 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
40.0
45.0
50.0
50.0
%
%
t3
t4
t5
t6
ns
ns
ps
ps
Fall Time 4
Output-to-output skew 4
Delay, REF Rising Edge to
CLKOUT Rising Edge 4
Device-to-Device Skew 4
Measured at VDD /2
0
0
±350
t7
t8
Measured at VDD/2 on the CLKOUT pins of
the device
700
ps
Output Slew Rate 5
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/ns
tJ
Cycle-to-cycle jitter 4
PLL Lock Time 4
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented
on REF pin
200
1.0
ps
tLOCK
ms
Notes:
3. REF input has a threshold voltage of VDD/2
4. Parameter is guaranteed by design and characterization. Not 100% tested in production
5. All parameters specified with loaded outputs.
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
2.0 V
0.8 V
OUTPUT
0.8 V
t4
t3
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6
November 2003
PCC028-01B
rev 1.1
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
VDD /2
INPUT
VDD /2
OUTPUT
t6
Device - Device Skew
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7
November 2003
rev 1.1
PCC028-01B
Test Circuits
Test Circuit #2
Test Circuit #1
VDD
VDD
1k
Ω
CLK OUT
OUTPUTS
GND
OUTPUTS
GND
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1k
Ω
CLOAD
10 pF
VDD
VDD
GND
GND
For parameter t8 (output slew rate)
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8
November 2003
rev 1.1
PCC028-01B
Package Information: 16-lead (150 Mil) Molded SOIC S16
PIN 1 ID
1
8
H
E
9
16
h
D
Seating Plane
A2
A
C
θ
0.004
e
L
A1
B
DIMENSIONS
INCHES
MILLIMETERS
MIN
0.061
0.004
0.055
0.013
0.0075
0.386
0.150
MAX
MIN
1.55
0.102
1.40
0.33
0.191
9.80
3.81
MAX
1.73
0.249
1.55
0.49
0.249
9.98
3.99
A
A1
A2
B
C
D
E
0.068
0.0098
0.061
0.019
0.0098
0.393
0.157
e
0.050 BSC
1.27 BSC
H
h
L
0.230
0.010
0.016
0°
0.244
0.016
0.035
8°
5.84
0.25
0.41
0°
6.20
0.41
0.89
8°
θ
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9
November 2003
rev 1.1
PCC028-01B
Package Information: 16-lead Thin Shrunk Small Outline Package (4.40-MM Body) Z-16
1
8
PIN 1 ID
E
H
9
16
A
Seating Plane
C
θ
A2
A1
e
B
L
D
DIMENSIONS (inches)
DIMENSIONS (mm)
MIN
MAX
0.043
0.006
0.37
0.012
0.008
2.008
0.177
MIN
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
A
A1
A2
B
C
D
E
0.002
0.003
0.007
0.004
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
e
0.026 BSC
0.65 BSC
H
L
0.246
0.020
0°
0.256
0.028
8°
6.25
0.50
0°
6.50
0.70
8°
θ
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003
PCC028-01B
rev 1.1
Package Information: 16-lead (150-mil) SSOP O-16
8
1
PIN 1 ID
E
H
16
9
D
A
Seating Plane
C
θ
0.004
A1
B
L
e
DIMENSIONS (inches)
DIMENSIONS (millimeters)
MIN
MAX
0.065
0.010
0.012
0.010
0.197
0.157
MIN
1.245
0.102
0.203
0.178
4.801
3.81
MAX
1.651
0.254
0.305
0.254
5.004
3.988
A
A1
B
C
D
E
e
0.049
0.004
0.008
0.007
0.189
0.150
0.025 BSC
0.635 BSC
H
L
0.228
0.016
0°
0.244
0.050
8°
5.791
0.406
0°
6.198
1.27
8°
θ
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003
PCC028-01B
rev 1.1
Ordering Codes
Ordering Code
Package Name
Package Type
Operating Range
PCC028-01BSC-1
PCC028-01BSI-1
PCC028-01BZC-1
PCC028-01BZI-1
PCC028-01BOC-1
PCC028-01BOI-1
S16
S16
Z16
Z16
O16
O16
16-pin 150 - mil SOIC
16-pin 150 - mil SOIC
16-pin 4.4mm TSSOP
16-pin 4.4mm TSSOP
16-pin 150 - mil SSOP
16-pin 150 - mil SSOP
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
November 2003
rev 1.1
PCC028-01B
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: PCC028-01B
Document Version: 1.1
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Dan Hariton / Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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Low-Cost 3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
相关型号：
PCC028-01BSI-1
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16
PULSECORE
PCC028-01BZC-1
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16
PULSECORE
PCC028-01BZI-1
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16
PULSECORE
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