概述
数据手册PCS3P623Z0XYG-16-TR 概述
Timing-Safe™ Peak EMI reduction IC 时序-SAFE ™峰值EMI降低IC
PCS3P623Z0XYG-16-TR 数据手册
通过下载PCS3P623Z0XYG-16-TR数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
High Frequency Timing-Safe™ Peak EMI reduction IC
with Peak EMI reduction. PCS3P624Z05 is an eight-pin
version, accepts one reference input and drives out five
low-skew Timing-Safe™ clocks. PCS3P624Z09 accepts
one reference input and drives out nine low-skew Timing-
Safe™clocks.
General Features
•
High Frequency Clock distribution with Timing-
Safe™ Peak EMI Reduction
•
•
Input frequency range: 50MHz - 100MHz
Multiple low skew Timing-safe™ Outputs:
PCS3P624Z05: 5 Outputs
PCS3P624Z05/09 has a DLY_CTRL for adjusting the
Input-Output clock delay, depending upon the value of
capacitor connected at this pin to GND.
PCS3P624Z09: 9 Outputs
•
•
•
•
External Input-Output Delay Control option
Supply Voltage: 3.3V±0.3V
PCS3P624Z05/09 operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
Commercial and Industrial temperature range
Packaging Information:
ASM3P624Z05: 8 pin SOIC, and TSSOP
ASM3P624Z09:16 pin SOIC, and TSSOP
True Drop-in Solution for Zero Delay Buffer,
ASM5P2305A / 09A
•
Application
PCS3P624Z05/09 is targeted for use in Displays and
memory interface systems.
Functional Description
PCS3P624Z05/09 is a versatile, 3.3V Zero-delay buffer
designed to distribute high frequency Timing-Safe™ clocks
General Block Diagram
DLY_CTRL
DLY_CTRL
PLL
PLL
MUX
CLKIN
CLKOUTA1
CLKOUTA2
CLKOUTA3
CLKOUT1
CLKOUT2
CLKOUT3
CLKIN
CLKOUTA4
CLKOUTB1
PCS3P624Z05B/C
CLKOUT4
S2
S1
Select Input
Decoding
CLKOUTB2
CLKOUTB3
CLKOUTB4
PCS3P624Z09B/C
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The PCS3P624Z05/09
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with
a
specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation
Zero Delay and Skew Control
For applications requiring zero input-output delay, all
outputs, including DLY_CTRL, must be equally loaded.
Even if DLY_CTRL is not used, it must have a capacitive
load equal to that on other outputs, for obtaining zero-
input-output delay.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the DLY_CTRL pin
is the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Pin Configuration for PCS3P624Z05B/C
CLKIN
CLKOUT1
CLKOUT2
GND
1
2
3
4
8
DLY_CTRL
CLKOUT4
VDD
7
6
5
PCS3P624Z05B/C
CLKOUT3
Pin Description for PCS3P624Z05B/C
Pin #
Pin Name
Type
Description
1
CLKIN1
I
External reference Clock input, 5V tolerant input
Buffered clock output4
Buffered clock output4
Ground
2
3
4
5
6
7
8
CLKOUT12
CLKOUT22
GND
O
O
P
CLKOUT32
O
P
Buffered clock output4
VDD
3.3V supply
Buffered clock output4
CLKOUT42
DLY_CTRL
O
O
External Input-Output Delay control. This pin can be used as clock output4
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Pin Configuration for PCS3P624Z09B/C
1
16
DLY_CTRL
CLKOUTA4
CLKIN
2
3
CLKOUTA1
CLKOUTA2
15
14
CLKOUTA3
VDD
13
12
4
5
6
VDD
GND
PCS3P624Z09B/C
GND
CLKOUTB1
11 CLKOUTB4
10
9
CLKOUTB3
S1
7
8
CLKOUTB2
S2
Pin Description for PCS3P624Z09B/C
Pin #
1
Pin Name
CLKIN1
CLKOUTA12
CLKOUTA22
VDD
Pin Type
Description
I
External reference Clock input, 5V tolerant input
Buffered clock Bank A output4
Buffered clock Bank A output4
3.3V supply
2
O
O
P
P
O
O
I
3
4
5
GND
Ground
6
CLKOUTB12
CLKOUTB22
S23
Buffered clock Bank B output4
Buffered clock Bank B output4
7
8
Select input, bit 2.See Select Input Decoding table for PCS3P624Z09 for more details
9
S13
I
Select input, bit 1.See Select Input Decoding table for PCS3P624Z09 for more details
10
11
12
13
14
15
16
CLKOUTB32
CLKOUTB42
GND
O
O
P
P
O
O
O
Buffered clock Bank B output4
Buffered clock Bank B output4
Ground
VDD
3.3V supply
Buffered clock Bank A output4
Buffered clock Bank A output4
CLKOUTA32
CLKOUTA42
DLY_CTRL2
External Input-Output Delay control. This pin can be used as clock output
Notes: 1. Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Select Input Decoding table for PCS3P624Z09
PLL
S2
S1
CLKOUT A1 - A4 CLKOUT B1 - B4 DLY_CTRL1 Output Source
Shut-Down
0
0
1
1
0
1
0
1
Three-state
Driven
Three-state
Three-state
Driven
Driven
Driven
Driven
Driven
PLL
PLL
N
N
Y
N
Driven
Reference
Driven
Driven
PLL
Notes: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and
the Output.
Spread Spectrum Control and Input-Output Skew Table
Frequency (MHz)
Device
Deviation (±%)
Input-Output Skew (±TSKEW)
PCS3P624Z05B / 09B
PCS3P624Z05C / 09C
0.25
0.5
0.0625
0.125
75
Note: TSKEW is measured in units of the Clock Period
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VDD
Supply Voltage to Ground Potential
-0.5 to +4.6
V
VIN
TSTG
Ts
DC Input Voltage (CLKIN)
Storage temperature
-0.5 to +7
-65 to +125
°C
°C
°C
KV
Max. Soldering Temperature (10 sec)
Junction Temperature
260
150
2
TJ
TDV
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
Description
Min
3.0
Max
3.6
+85
30
Unit
V
VDD
TA
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
-40
°C
CL
pF
pF
CIN
Input Capacitance
7
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PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
V
VIL
VIH
IIL
Input LOW Voltage5
Input HIGH Voltage5
Input LOW Current
Input HIGH Current
Output LOW Voltage6
Output HIGH Voltage6
Dynamic Supply Current
Output Impedance
0.8
2.0
V
VIN = 0V
50
100
0.4
µA
µA
V
IIH
VIN = VDD
VOL
VOH
IDD
Zo
IOL = 8mA
IOH = -8mA
2.4
V
Unloaded outputs
40
mA
Ω
23
Note: 5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
Switching Characteristics
Parameter
Test Conditions
Min
50
Typ
Max
Unit
MHz
MHz
%
Input Frequency
100
100
60
Output Frequency
30pF load
50
Duty Cycle 7,8 = (t2 / t1) * 100
Output Rise Time 7, 8
Output Fall Time 7, 8
Output-to-output skew 7, 8
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge 8
Measured at VDD/2
40
50
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
2.5
2.5
250
nS
nS
pS
Measured at VDD /2
±350
pS
Measured at VDD/2 on the CLKOUT pins
of the device
Device-to-Device Skew 8
Cycle-to-Cycle Jitter 7, 8
PLL Lock Time 8
700
±200
1.0
pS
pS
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
mS
Note: 7. All parameters specified with 30pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production
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PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Switching Waveforms
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
All Outputs Rise/Fall Time
2V
2V
3.3V
0V
0.8V
0.8V
OUTPUT
t3
t4
Output - Output Skew
VDD/2
OUTPUT
OUTPUT
VDD/2
t 5
Input - Output Propagation Delay
VDD/2
INPUT
VDD/2
OUTPUT
t 6
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Device - Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
t 7
Test Circuit
Input-Output Skew
Timing-Safe™
Output
+3.3V
Input
VDD
0.1uF
CLKOUT
LOAD
OUTPUT
TSKEW
+
TSKEW
-
+3.3V
VDD
GND
One clock cycle
N=1
0.1uF
T
SKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
A Typical example of Timing-Safe™ waveform
Input
Input
Timing-Safe™ CLKOUT
CLKOUT with SSOFF
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Millimeters
Min Max
Min
Max
0.010
0.069
0.059
0.020
0.010
A1
A
0.004
0.053
0.049
0.012
0.007
0.10
1.35
1.25
0.31
0.18
0.25
1.75
1.50
0.51
0.25
A2
B
C
D
E
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
e
H
L
0.016
0°
0.050
8°
0.41
0°
1.27
8°
θ
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
8-lead TSSOP (4.40-MM Body)
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
Min
Max
A
A1
A2
B
0.043
0.006
0.037
0.012
0.008
0.122
0.177
1.10
0.002
0.033
0.008
0.004
0.114
0.169
0.05
0.85
0.19
0.09
2.90
4.30
0.15
0.95
0.30
0.20
3.10
4.50
c
D
E
e
0.026 BSC
0.252 BSC
0.65 BSC
6.40 BSC
H
L
0.020
0°
0.028
8°
0.50
0°
0.70
8°
θ
High Frequency Timing-Safe™ Peak EMI Reduction IC
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PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
16-lead (150 Mil) Molded SOIC Package
PIN 1 ID
1
8
H
E
9
16
h
D
Seating Plane
A2
A
C
θ
0.004
e
L
A1
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
0.069
0.010
0.059
0.022
0.012
0.394
0.157
Min
1.35
0.10
1.25
0.33
0.19
9.80
3.80
Max
1.75
0.25
1.50
0.53
0.27
10.01
4.00
A
A1
A2
B
0.053
0.004
0.049
0.013
0.008
0.386
0.150
C
D
E
e
0.050 BSC
1.27 BSC
H
h
0.228
0.010
0.016
0°
0.244
0.016
0.035
8°
5.80
0.25
0.40
0°
6.20
0.41
0.89
8°
L
θ
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
16-lead TSSOP (4.40-MM Body)
1
8
PIN 1 ID
E
H
9
16
A
Seating Plane
C
θ
A2
A1
e
B
L
D
Dimensions
Symbol
Inches
Millimeters
Min
Max
Min
Max
1.20
0.15
1.05
0.30
0.20
5.10
4.50
A
A1
A2
B
0.043
0.006
0.041
0.012
0.008
0.201
0.177
0.002
0.031
0.007
0.004
0.193
0.169
0.05
0.80
0.19
0.09
4.90
4.30
C
D
E
e
0.026 BSC
0.252 BSC
0.65 BSC
6.40 BSC
H
L
0.020
0°
0.030
8°
0.50
0°
0.75
8°
θ
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Ordering Code
Ordering Code
Marking
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
3P624Z0xyG
3I624Z0xyG
Package Type
8-pin 150-mil SOIC-TUBE, Green
8-pin 150-mil SOIC-TUBE, Green
Temperature
Commercial
Industrial
PCS3P624Z0xyG-08-ST
PCS3I624Z0xyG-08-ST
PCS3P624Z0xyG-08-SR
PCS3I624Z0xyG -08-SR
PCS3P624Z0xyG-08-TT
PCS3I624Z00xyG -08-TT
PCS3P624Z0xyG-08-TR
PCS3I624Z0xyG -08-TR
PCS3P624Z0xyG -16-ST
PCS3I624Z0xyG -16-ST
PCS3P624Z0xyG -16-SR
PCS3I624Z0xyG -16-SR
PCS3P624Z0xyG -16-TT
PCS3I624Z0xyG -16-TT
PCS3P624Z0xyG -16-TR
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 4.4-mm TSSOP - TUBE, Green
Commercial
Industrial
Commercial
Industrial
8-pin 4.4-mm TSSOP - TUBE, Green
8-pin 4.4-mm TSSOP - TAPE & REEL, Green
8-pin 4.4-mm TSSOP - TAPE & REEL, Green
16-pin 150-mil SOIC-TUBE, Green
Commercial
Industrial
Commercial
Industrial
16-pin 150-mil SOIC-TUBE, Green
16-pin 150-mil SOIC-TAPE & REEL, Green
16-pin 150-mil SOIC-TAPE & REEL, Green
16-pin 4.4-mm TSSOP - TUBE, Green
16-pin 4.4-mm TSSOP - TUBE, Green
16-pin 4.4-mm TSSOP - TAPE & REEL, Green
16-pin 4.4-mm TSSOP - TAPE & REEL, Green
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
PCS3I624Z0xyG -16-TR
Note: x=5 / 9; y=B / C
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Device Ordering Information
P C S 3 P 6 2 4 Z 0 x y G - 0 8 - T R
R = Tape & Reel, T = Tube or Tray
O = TSOT23
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
J=TSOT26
C=TDFN (2X2) COL
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
(-40C to +125C) (-40C to +85C)
I= Industrial
P or n/c = Commercial
(0C to +70C)
1 = Clock Generator
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
High Frequency Timing-Safe™ Peak EMI Reduction IC
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Notice: The information in this document is subject to change without notice.
PCS3P624Z05B/C
PCS3P624Z09B/C
May 2008
rev 0.1
Copyright © PulseCore Semiconductor
All Rights Reserved
Part Number: PCS3P624Z05B/C
PCS3P624Z09B/C
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
Document Version: 0.1
www.pulsecoresemi.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
Many PulseCore Semiconductor products are protected by issued patents or by applications for patent
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of
PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the
right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that
may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance.
PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive
information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and
disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to
fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s
Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to
PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights,
copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not
authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to
result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
High Frequency Timing-Safe™ Peak EMI Reduction IC
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| PCS3P624Z05BG-16-ST | PULSECORE | Clock Generator, 100MHz, CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16 | 获取价格 |
|
| PCS3P624Z05C | PULSECORE | High Frequency Timing-Safe™ Peak EMI reduction IC | 获取价格 |
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| PCS3P624Z05CG-08-TR | PULSECORE | Clock Generator, 100MHz, CMOS, PDSO8, 4.40 MM, GREEN, TSSOP-8 | 获取价格 |
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| PCS3P624Z05CG-16-ST | PULSECORE | Clock Generator, 100MHz, CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16 | 获取价格 |
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| PCS3P624Z05CG-16-TR | PULSECORE | Clock Generator, 100MHz, CMOS, PDSO16, 4.40 MM, GREEN, TSSOP-16 | 获取价格 |
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