P1757M-20PGMB [PYRAMID]
Microprocessor, 20MHz, CMOS, CPGA144, PGA-144;
| 型号： | P1757M-20PGMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Microprocessor, 20MHz, CMOS, CPGA144, PGA-144 |
| 文件： | 总34页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PACE1757M/ME
COMPLETE EMBEDDED CPU SUBSYSTEM
FEATURES
Programmable memory and I/O data wait
state generation permits up to four different
memory speeds in the same system.
Implements complete MIL-STD-1750A ISA including
optional MMU, MFSR, and BPU functions.
Two throughput options:
P1757M 2.5MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz
P1757ME 3.6MIPS USAF Dais Mix (Inc.Flt.Pt.)@40 MHz
Programmable address wait states.
Sixteen levels of interrupts are provided per
MIL-STD-1750A. Interrupts can be either
edge- or level-sensitive.
All MIL-STD-1750A data formats and address
types implemented.
Fault detection and handling
P1757ME includes additional matrix and vector
instructions to enhance throughput in
navigation, DSP transcendental and other
complex alorithms.
Programmable detection of unimplemented
memory or illegal I/O addresses.
Full implementation of MIL-STD-1750A fault
register.
Error detection and correction and parity bit
provided.
External address error detection.
Testability and diagnostics.
Separate high drive external address & data
busses.
First falling address and data registers.
10MHz data rate at 40MHz CPU clock
System support functions included:
Built in test - runs automatically at power on
and after each reset. All hardware blocks
and external busses examined. Hardware
pass/fail for catastrophic failures. Status
register indicates failed test.
Arbitrator for use in tightly coupled
multiprocessor design. Bus control provided
to aid in implementation of multi-processor
systems.
Console operating mode which allows
operator to examine and change contents of
registers within the CPU, any system
memory location, or the I/O subsystems.
MIL-STD-1750A timers A & B, programmable
watch dog timer and programmable bus time-
out function.
Single 144-pin Quad straight lead or Gullwing
1.5 square inches of board surface.
Start up ROM support per MIL-STD-1750A.
DMA support for logical and physical memory
addresses.
Operating temperature range -55 to +125°C;
single 5V ± 10% V power supply; power
CC
dissipation < 1.9W (worst case at 40 MHz).
GENERAL DESCRIPTION
The PACE 1757M uses the application-proven PACE
1750A microprocessor, the PACE 1753, and the PACE
1754. The PACE1757ME uses the enhanced PACE
1750AEmicroprocessor,whichhasadditionalinstructions
thatprovidehighthroughputfortranscendentalfunctions,
navigational algorithms, and DSP functions. The PACE
1750AE is an architectural enhancement of the PACE
1750A.
All functions required for a complete MIL-STD-1750A
embedded CPU subsystem are in this single VLSI
microcircuit occupying 1.5 square inches of board space
with less than 1.9 watts of power dissipation at 40 MHz.
Pyramid'sP1757M/MEisacomplete,singlepackage,3.6
MIPS subsystem solution to embedded processor
requirements.
Do c um e nt # MICRO-10 REV B
Re vise d Aug ust 2005
PACE 1757 M/ME
Do c um e nt # MICRO-10 REV B
Pa g e 2 o f 34
PACE 1757 M/ME
AC/DC ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
(Above which the useful life may be impaired)
Storage Temperature
-65°C to +150°C
-55°C to +125°C
-0.5V to 7.0V
Ambient Temperature with Power
VCC Pin Potential to Ground Pin
Input Voltage
-0.5V to V + 0.5V
CC
-30 mA to 5 mA
Input Current
-0.5V to V + 0.5V
Voltage Applied to Inputs
Current Applied to any Output
Power Dissipation
CC
100 mA
2.5 Watts
35°C/W
θJA
RECOMMENDED OPERATING CONDITIONS
Grade
Case Temperature
GND
V
CC
Military
-55°C to +125°C
0V
5.0V ± 10%
DC ELECTRICAL SPECIFICATIONS
(Over recommended operating conditions)
Symbol
Parameter
Min
Typ.
Max
Unit
Conditions
Input HIGH Level
Input LOW Level2
2.0
V
VIH
VCC+0.5
0.8
-0.5
V
V
VIL
Input clamp diode voltage
-1.2
VCD
IIN=-18mA
VCC=Min
OH=-8mA
Output HIGH Voltage
2.4
V
V
VOH
I
VCC -0.2
IOH=-300µA
VCC=Min
IOL=8mA
Output LOW Voltage
Except A0-A15,
0.5
0.2
V
V
VOL
EXT ADR0-EXT ADR7
IOL=300µA
VCC=Min
IOL=20mA
Output LOW Voltage
A0-A15,
0.5
0.2
V
V
EXT ADR0-EXT ADR7
IOL=300µA
VCC=Min
VIN=VCC
VCC=Max
Input HIGH Current except
10
µA
IIH
IB -IB , EDC -EDC ,
BUS
0
15
0
5
,
BUSY BUS LOCK
,
EXT ADR0-EXT ADR7
50
µA
Input HIGH Current IB0-IB15,
VIN=VCC
EDC -EDC ,
,
VCC=Max
BUS BUSY
0
5
,
BUS LOCK
EXT ADR0-EXT ADR7
Do c um e nt # MICRO-10 REV B
Pa g e 3 o f 34
PACE 1757 M/ME
DC ELECTRICAL SPECIFICATIONS (Continued)
(Over recommended operating conditions)
Symbol
Parameter
Min
Typ.
Max Unit
Conditions
VIN=GND
CC=Max
IIL
Input LOW current except IB0-IB15, EDC0-
EDC ,
,
BUS BUSY BUS LOCK
,
V
-10
µA
5
EXT ADR0-EXT ADR7, TEST ON
Input LOW current TEST ON
-500
-50
VIN=VCC
Input LOW current IB0-IB15, EDC0-EDC5,
VCC=Max
µA
,
BUS BUSY BUS LOCK
,
EXT ADR0-EXT ADR7
Output 3-state current Except SINGERR,
STRBA
Output 3-state current SINGERR, STRBA
IOZH
V
V
OUT=2.4V
CC=Max
50
µA
µA
500
-50
Output 3-state current Except
STRBD
IOZL
VOUT=0.5V
CC=Max
V
Output 3-state current
STRBD
-500
Quiescent Power Supply Current
(CMOS Input Levels)
ICCQC
VIN < 0.2V or
> VCC -0.2V, f=0Hz
Outputs open
VCC=Max
80
mA
mA
Quiescent Power Supply Current
(TTL Levels)
ICCQT
VIN=3.4V, All inputs,
f=0Hz
Outputs open
210
V
CC=Max
Dynamic Power Supply Current f=20 MHz
ICCD
TTL
VIN < 0.8V or > 3.4V,
Outputs open
280
310
325
340
f=30 MHz
f=35 MHz
f=40 MHz
mA
V
CC=Max
Dynamic Power Supply Current f=20 MHz
ICCD
VIN < 0.2V or
150
180
195
210
f=30 MHz
f=35 MHz
f=40 MHz
> VCC -0.2V
Outputs open,
VCC=Max
mA
mA
IOS
Output Short Circuit Current1
(one output shorted at a time)
V
V
OUT=GND
CC=Max
-25
Input Capacitance3
5
9
pF
pF
Inputs Only
CIN
COUT Output Capacitance3
Outputs (includes I/O
Buffers)
Note 1: Duration of the short should not exceed one second.
Note 2: V =-3.0V for pulse widths less than or equal to 20ns.
IL
Note 3: This parameter is set by design and not tested.
Do c um e nt # MICRO-10 REV B
Pa g e 4 o f 34
PACE 1757 M/ME
TIMING GENERATOR STATE DIAGRAMS
Two separate and almost independent state diagrams
may be used to describe the PACE1757M machine
cycle.
The Execution Unit performs according to a cycle of
three state represented by Diagram A (the A machine)
and the External Bus Unit follows a minimum cycle of
four states, indicated in Diagram B (the B machine).
Referring to Diagram A, the paths are defined as
follows for the Execution Unit:
(0) External Reset true
(1) External Reset false
(2) ALU wait or Bus wait.
(3) ALU Branch false
(4) ALU Branch true
Diagram A
Diagram B defines the paths for the External Bus as
follows:
(0) External Reset false
(8) Bus Req. false
(9) Bus Req. true and Bus Av. true
(10) Bus Req. true and Bus Av. false
(11) Bus Av. false
(12) Bus Av. true
(13) RDYA false
(14) RDYA true
(16) RDYD false
Diagram B
(17) RDYD true and Bus Req. true and Bus Av. true
(18) RDYD true and Bus Req. false
(19) RDYD true and Bus Req. true and Bus Av. false
(20) Bus Req. true and Bus Av. true
NOTE:
Bus A = Bus grant and Bus not busy and Bus not locked.
V
Do c um e nt # MICRO-10 REV B
Pa g e 5 o f 34
PACE 1757 M/ME
DIFFERENCES BETWEEN THE PACE1757M AND PACE1757ME
The PACE1757ME, which uses the P1750AE CPU, achieves a 41% boost in performance (in clock cycles) over the
PACE1757M, which uses the P1750A CPU. This reduction in clocks per instruction is because of three architectural
enhancements:
1. The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2. A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU's peripheral
chips).
3. Branch calculation logic.
The table below shows how the MAC improves all multiply operations - both integer and floating point - by 477% to 760%
PACE1750AE
PACE1750A
Gain
# Clocks
(%)
Execution
Execution
Instruction
Clocks
Time
Clocks
Time
(40 MHz)
(40 MHz)
Integer Add/Sub
4
6
100ns
150ns
100ns
225ns
450ns
850ns
225ns
425ns
200ns
100ns
675ns
1275ns
3.56
4
9
100ns
225ns
575ns
1725ns
700ns
1225ns
1075ns
2400ns
300ns
100ns
1775ns
3675ns
2.52
⎯
50
Double Precision Integer Add/Sub
Integer Multiply
4
23
69
28
51
43
96
12
4
575
760
55
Double Precision Integer Add/Sub
Floating Add/Sub
9
18
34
9
Extended Floating Add/Sub
Floating Multiply
50
477
564
50
Extended Floating Point Multiply
Branch (Taken)
17
8
Branch (Not Taken)
4
⎯
263
Flt'g' Point Polynomial Step (Mul+Add/Sub)
Ext Flt'g' Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
27
51
⎯
71
147
⎯
2400
41/59
PACE1757ME BUILT-IN FUNCTIONS
A core set of additional instructions have been included in the PACE1757ME. These instructions use the Built-In Function (BIF)
opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application areas
such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BIFs and their
execution times (N = the number of elements in the vector being processed).
Address
Mode
Number of
Clocks
Instruction
Mnemonic
Notes
Memory Parametric Dot Product - Single
Memory Parametric Dot Product - Double
3 x 3 Register Dot Product
VDPS
VDPD
R3DP
MACD
4F06
4F3(RA)
4F1(RA)
4F03
4F02
7 • N -2
4
10 + 8 • N
Interruptable
10 + 16 • N Interruptable
6
8
Double Precision Multiply Accumulate
Polynomial POLY
Clear Accumulator CLAC
Store Accumulator (32-Bit)
4F00
STA
4F08
4F04
4F05
4F07
4F0F
4F0D
4F0E
7
11
9
Store Accumulator (48-Bit)
STAL
LAC
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
LACL
MMPG
LTAR
LTBR
9
16 + 8 • N
Priveleged
Load Timer A Reset Register
Load Timer B Reset Register
4
4
Do c um e nt # MICRO-10 REV B
Pa g e 6 o f 34
PACE 1757 M/ME
TIMING GENERATOR STATE DIAGRAMS
Two separate and almost independent state diagrams
may be used to describe the PACE1757ME machine
cycle.
The Execution Unit performs according to a cycle of
three states represented by Diagram A (the A machine)
and the External Bus Unit follows a minimum cycle of
four states, indicated in Diagram B (the B machine).
Referring to Diagram A, the paths are defined as
follows for the Execution Unit:
(0) External Reset true
(1) External Reset false
(2) ALU wait or Bus wait.
(3) ALU Branch false
(4) ALU Branch true
Diagram A
Diagram B defines the paths for the External Bus as
follows:
(0) External Rest false
(1) No Internal Bus Req.
(2) Internal Bus Req.
(3) Bus Busy or No Bus Grant
(4) Bus Grant and Not Busy or
Bus Locked by CPU
(5) RDYA false
(6) RDYA true
(7) RDYD false
(8) RDYD true, and no Internal Bus Request
(9) RDYD true, Internal Bus Request pending
(10) Bus Locked by CPU and No Internal Request
(11) Bus Locked by CPU Internal Req.
Diagram B
NOTE:
Bus A = Bus grant and Bus not busy and Bus not locked.
V
Do c um e nt # MICRO-10 REV B
Pa g e 7 o f 34
PACE 1757 M/ME
SIGNAL PROPAGATION DELAYS
20 MHz
30 MHz
35 MHz
40 MHz
Symbol
TC(BR)L
TC(BR)H
TBGV(C)
TC(BG)X
TC(BB)L
TC(BB)H
TBBV(C)
TC(BB)X
TC(BL)L
TC(BL)H
TBLV(C)
TC(BL)X(IN)
TC(ST)V
Description
BUS REQUEST
MIN
MAX
33
33
MIN
MAX MIN MAX MIN
MAX
22
22
25
25
22
22
- Setup
- Hold
5
5
5
5
5
5
5
5
BUSGRANT
BUSGRANT
BUS BUSY
25
25
24
20
22
18
20
17
- Setup
- Hold
5
5
5
5
5
5
5
5
BUS BUSY
BUS BUSY
BUS LOCK
30
30
25
20
23
19
21
17
- Setup
- Hold
5
5
5
5
5
5
5
5
BUS LOCK
BUS LOCK
M/
IO
30
30
25
25
25
20
23
23
20
20
20
20
R/
W
AS0:AS3, AK0:AK3, D/
I
TC(ST)X
M/ , R/ , AS0:AS3, AK0:AK3, D/
0
0
0
0
IO
W
I
TC(SA)H
STRBA
22
22
17
17
16
16
16
16
TC(SA)L
TSAL(IBA)X
TRAV(C)
Address Hold from STRBA(L)
RDYA - Setup
5
5
5
5
5
5
5
5
5
5
5
5
TC(RA)X
RDYA - Hold
TC(SDW)L
TC(SD)H
22
22
22
17
17
17
16
16
16
14
14
14
STRBD
TFC(SDR)L
TIBDX(SDR)H
TSDWH(IBD)X
TSDL(SD)H(Write)
TRD(RD)X
TC(RD)X
0
30
40
5
0
25
26
5
0
21
23
5
0
17
20
5
RDYD - Setup
RDYD - Hold
IB0:IB15
5
5
5
5
TC(IBA)V
30
25
23
20
TFC(IBA)X
TIBDRV(C)
TC(IBD)X(Read)
TC(IBD)X(Write)
TFC(IBD)V
TC(SNW)
0
5
5
0
0
5
5
0
0
5
5
0
0
5
5
0
- Setup
- Hold
DATAVALID (OUT)
30
30
30
40
40
40
60
50
25
26
26
35
35
35
50
40
23
24
24
33
33
33
47
35
20
22
22
30
30
30
45
30
SNEW
TFC(TGO)
TRSTL(DMA EN)L
TC(DME)
TRIGO RST
DMA ENABLE
TFC(NPU)
TC(ER)
NORMAL POWER-UP
CLK TO MAJER (UNRCV ER)
RESET
TRSTL(NPU)
TREQV(C)
TC(REQ)X
TFV(BB)H
0
10
5
0
10
5
0
10
5
0
10
5
CON REQ
LEVEL SENSITIVEFAULTS
TBBH(F)X
5
5
5
5
TIRV(C)
IOL 1/2 INT. USR
(0:5) - Setup
0
0
0
0
INT
TC(IR)X
PWRDN INT, LEVEL SENSITIVE- HOLD
RESET PULSE WIDTH
10
25
10
20
10
18
10
15
TRSTL(TRSTH)
TC(XX)Z
CLK TO TRI-STATE
22
17
15
13
Note 1: Units = ns
Do c um e nt # MICRO-10 REV B
Pa g e 8 o f 34
PACE 1757 M/ME
40 MHz
SIGNAL PROPAGATION DELAYS (cont'd)
20 MHz
30 MHz
35 MHz
Symbol
TD/I(EXT ADR)V
TSTRBD(EXT ADR ER) External Address Error
TIBDV(EDC GEN)V
TC(GNT)
Description
MMU Cache Hit
MIN
MAX MIN MAX MIN
MAX
23
18
24
22
21
28
43
18
20
42
33
33
20
27
25
23
12.5
19
20
21
15
15
18
18
18
23
MIN
MAX
23
16
23
18
17
25
40
16
18
40
30
30
20
23
25
21
11.5
16
19
20
12
12
15
15
15
20
25
25
30
35
30
34
50
25
25
40
40
25
25
32
30
28
16
28
29
31
24
24
26
26
26
30
23
20
25
25
25
30
45
20
22
45
35
35
20
30
25
24
13
22
21
22
18
18
20
20
20
25
Error Correction Write Cycle
Arbiter Priority Transition
Address Ready
TC(RDYA)
TIBDIN(MEM PAR ER) Parity Mode
TC(MEM PRT ER)
Memory Protect Error
T
Write Protect Cache Hit
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT Address Valid (Miss)
Clock to EXT Address Valid (Miss)
Ready Data
Ready Data
Ready Data
Address Valid
Address Valid
Read Strobes
Read Strobes
Write Strobes
Write Strobes
Start-Up ROM
Timer Clock
Extended Address Set-Up
Edge Sensitive Pulse Width
Clock Rise and Fall Time
STRBD (WR PROT)
TC(WR PROT)I
TD/I(PROT FLAG)
TD/I(PROT FLAG)
TC(PROT FLAG)
TC(PROT FLAG)
TC(EXT ADR)V
TFC(IB OUT)V
T
(RDYD)
(RDYD)
EX RDY1
T
EX RDY
TC (RDYD)V
TSTRBAh(A)V
TIBAV(A)V
TFC (R)L
TSTRBDH(R)H
TSTRBDH(W)L
TSTRBDL(W)H
TSTRBD(STRTROM)
TC(TIMCLK)
TEXT AD(FC B3)
TF(F), TI(I)
10
5
10
5
10
5
10
5
tr, tf
5
5
5
5
Units = ns
Note
All timing parameters are composed of Three elements. The first "T" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "E" or the fallingedge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Do c um e nt # MICRO-10 REV B
Pa g e 9 o f 34
PACE 1757 M/ME
MINIMUM WRITE BUS CYCLE TIMING DIAGRAM
Do c um e nt # MICRO-10 REV B
Pa g e 10 o f 34
PACE 1757 M/ME
MINIMUM READ BUS CYCLE TIMING DIAGRAM
Do c um e nt # MICRO-10 REV B
Pa g e 11 o f 34
PACE 1757 M/ME
MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM
Do c um e nt # MICRO-10 REV B
Pa g e 12 o f 34
PACE 1757 M/ME
ADDRESS BUS AND STROBES
Note:
All time measurements on active signals relative to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 13 o f 34
PACE 1757 M/ME
RDYD TIMING
1
TEST END TIMING
Notes:
1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the IOW bus cycle, the
XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the
processor. As from the end of STRBD in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two
fetch cycles from the "old PC" (from addresses XXXX & XXXX +1). The data will be taken from system memory (because TEST END is
asserted) but both the address and data are irrelevant. Following that, IC will start filling the pipe from address 0000 hex and 0001 hex, now
from the system memory to start user's program execution.
2. All time measurements on active signals relate to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 14 o f 34
PACE 1757 M/ME
STRT ROM
IB Bus Output (0:15)
Extended Addresses (0:1)
EX AD ER
Memory Protect Error
Error Correction (Write Cycle)
Error Correction (Read Cycle)
Ready Address
Note:
All time measurements on active signals relative to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 15 o f 34
PACE 1757 M/ME
MMU Cache Hit
External Address Error
Note:
All time measurements on active signals relative to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 16 o f 34
PACE 1757 M/ME
MMU Cache Miss Cycle (WA = 0)
MMU Cache Miss Cycle (WA > 0)
* The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT GLAG. (See BPU Description). T = 1 Clock Period.
Note: All time measurements on active signals relate to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 17 o f 34
PACE 1757 M/ME
TRIGO RST Discrete Timing
DMA EN Discrete Timing
Normal Power Up Discrete Timing
XIO Operations
SNEW Discrete Timing
Do c um e nt # MICRO-10 REV B
Pa g e 18 o f 34
PACE 1757 M/ME
External Faults and Interrupts Timing
Edge-sensitive interrupts and faults (SYSFLT ,
Level-sensitive interrupts
0
SYSFLT ) min. pulse width
1
Note: tC(IR)X max = 35 clocks
Level-sensitive faults
CON REQ
Note:
All time measurements on active signals relative to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 19 o f 34
PACE 1757 M/ME
Low Priority to High Priority Transition
Bus Arbitrator High Priority to Low Priority Transition
Note:
All time measurements on active signals relative to 1.5V levels.
Do c um e nt # MICRO-10 REV B
Pa g e 20 o f 34
PACE 1757 M/ME
BUS ACQUISITION
Note:
A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is asserted and the BUS is not locked (BUS
LOCK is HIGH).
SWITCHING TIME TEST CIRCUITS
Standard Output (Non-Three-State)
Parameter
V
V
MEA
O
t
≥ 3V
0.5V
V – 0.5V
CC
PLZ
t
t
t
0V
PHZ
PXL
PXH
V /2
CC
1.5V
1.5V
V /2
CC
Do c um e nt # MICRO-10 REV B
Pa g e 21 o f 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
Description
CPU CLK
CPU clock
Asinglephaseinputclocksignal(0-40MHz,40percentto60percentduty
cycle. This is a common input to all 3 devices.
RESET
Reset
An active LOW input that initializes the device. Input to the P1750A/AE,
P1753 and P1754.
CON REQ
Console request
An active LOW input that initiates console operations after completion of
the current instruction. Input to the CPU.
INTERRUPT INPUTS
Mnemonic
Name
Description
PWRDN INT
Power down interrupt An interrupt request input that cannot be masked or disabled. This signal
is active on the positive going edge or the high level, according to the
interrupt mode bit in the configuration register of the P1750A/AE.
USR INT -
User interrupt
Interrupt request input signals that are active on the positive going edge
edgeorthehighlevel,accordingtotheinterruptmodebitintheconfiguration
register of the P1750A/AE.
0
USR INT
5
IOL INT -
I/O Level Interrupts
Active HIGH interrupt requests that can be used to expand the number
of user interrupts. Inputs to the P1750A/AE interrupt register.
1
IOL INT
2
ERROR CONTROL
Mnemonic
Name
Description
UNRCV ER
Unrecoverable error
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable. A signal from the CPU.
MAJ ER
Major error
An active HIGH output that indicates the occurrence of an error classified
as major. A signal from the CPU.
DISCRETE CONTROL
Mnemonic
Name
Description
NML PWRUP
Normal power up
An active HIGH output that is set when the CPU has successfully
completedthebuilt-inselftestintheinitializationsequence. Itcanbereset
by the I/O command RNS.
SNEW
Start new
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle. This signal is issued by the CPU.
TRIGO RST
Trigger-go reset
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
STRT ROM
Start Up Rom
An output follow the execution of the ESUR and DSUR, I/O commands as
defined in MIL-STD-1750A. It will be at the logical level "1" after executing
ESURandatthelogical"0"levelafterexecutingDSUR. Initially,itdefaults
to a "1" on the P1754.
DMA EN
Direct memory
Access enable
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
Do c um e nt # MICRO-10 REV B
Pa g e 22 o f 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
BUS CONTROL
Mnemonic
Name
Description
TEST ON
System Test Enable
An active-LOW input, used to enable the execution of the System Test
builtinto theP1754, immediatelyaftercompletetionofthePACE1750A/
AE initialization and before fetching any instructions from the user's
program.
TEST END
System Test End
An active-HIGH output indicating whether the PACE 1754 System Test
hasbeencompleted. WhenevertheSystemTestisdisabledbytheTEST
ON signal, the TEST END output will be at a logical "1" immediately after
reset is removed.
SC -SC
System Configuration Inputs which are buffered onto IB0-IB4 when executing an I/O Read
0
4
Inputs
from I/O address 8410 (hex).
D/I
Data or instruction
Anoutputsignalthatindicateswhetherthecurrentbuscycleaccessisfor
Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not
assigned to the CPU. This line can be used as an additional memory
address bit for systems that require separate data and program memory.
R/W
M/IO
Read or write
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOWindicatesawriteoroutputoperation. Thesignalisthree-stateduring
bus cycles not assigned to the CPU.
Memory or I/O
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to the CPU.
RDYA_IN
Address ready In
An active HIGH input to the CPU that can be used to extend the address
phase of a bus cycle. When RDYA_IN is not active, wait states are
insertedbytheP1750A/AEtoaccomodateslowermemoryorI/Odevices.
ThislineisusuallyconnectedtoRDYA_OUTunlessthememoryinterface
logic requires the two RDYA signals remain discrete as an input and
output.
RDYA_OUT
RDYD
Address Ready Out
Data ready
An active HIGH output from the COMBO that indicates that there are no
wait states requested when STRBA is active. Wait states are inserted
whenthissignalbecomesinactiveduringSTRBA. Upto3waitstatescan
be inserted by programming an internal register. Three wait states are
inserted after reset (default).
An active HIGH signal to the CPU from the PIC that extends the data
phase of a bus cycle. When RDYD is not active, wait states are inserted
by the P1750A/AE to accomodate slower memory or I/O devices.
Do c um e nt # MICRO-10 REV B
Pa g e 23 o f 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
BUS ARBITRATION
Mnemonic
Name
Description
BUS REQ
Bus request
An active LOW output that indicates the CPU requires the bus. It
becomes inactive when the CPU has acquired the bus and started the
bus cycle.
BUS GNT
Bus grant
An active LOW input from an external arbiter that indicates the CPU
currently has the highest priority bus request. If the bus is not used and
not locked, the CPU may begin a bus cycle, commencing with the next
CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), three-
stating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA,
STRBD), and all the other lines that go three-state when this CPU does
not have the bus.
BUS BUSY
Bus busy
An active LOW, bidirectional signal used to establish the beginning and
end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used
for sampling bits into the fault register. It is three-state in bus cycles not
assigned to this CPU. However, the CPU monitors the BUS BUSY line
for latching non-CPU bus cycle faults into the fault register.
BUSLOCK
Bus lock
An active low, bi-directional signal used to lock the bus for successive
buscycles. Duringnon-lockedbuscycles,theBUSLOCK signalmimics
the BUS BUSY signal. It is three-state during bus cycles not assigned to
the CPU. The following instructions will lock the bus: INCM, DECM, SB,
RB, TSB, SRM, STUB and STLB.
BUS GNT -
Bus Grant
Bus Request
Active-LOW outputs from the PIC indicating which master was granted
the BUS. It remains active during BUS LOCK unless a higher master
request occurs, which resets it. However, the higher master will be
granted the BUS only after the current master's BUS LOCK releases the
BUS.
0
BUS GNT
3
BUS REQ -
Active-LOW inputs to the PIC that indicate a requirement for the BUS
0
BUS REQ
from the 4 masters on the bus. The master assigned to pin BUS REQ
3
0
has the highest priority. The master assigned to pin BUS REQ has the
3
lowest priority.
Do c um e nt # MICRO-10 REV B
Pa g e 24 o f 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
FAULTS AND FLAGS
Mnemonic
Name
Description
MEM PRT ER
Memory Protect Error An active-LOW input generated by the MMU or BPU, or both, during
attempted writes to protected memory. It is sampled by the BUS BUSY
signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus
cycle). The error is generated in one of the following conditions: a
mismatchintheaccesskeysintheMMUpage,anaccesstoanexecution
protected page during instruction cycles, an access to a write protected
page during data cycles or an access to a page write protected by the
BPU.
MEM PAR ER
Memory Parity Error
An active LOW signal which is sampled by the BUS BUSY signal into bit
2 of the CPU's Fault Register. It signals an error on the Data Bus during
amemorycycle. Twodetectionmodescanbeselectedbyprogramming
thecontrolregisteroftheMMU/COMBO:EDACmode(6Hammingcode
parity bits) or single bit parity mode (even or odd parity). The signal is
inactivewhennoneoftheabovemodesareselected(defaultafterreset).
EXT ADR ER IN External Address
An active-LOW input sampled by the BUS BUSY signal into the CPU
Error In
Fault Register (bit 5 or 8) depending on the cycle (memory or I/O).
EXT ADR ER OUT External Address
An active LOW output which signals to the CPU and memory interface
logic that an unimplemented memory or illegal I/O access has taken
place.
Error Out
SYSFLT -
System Fault 0,
System Fault 1
Asynchronous, positive edge sensitive inputs that set bit 7 (SYSFLT )
0
0
SYSFLT
or bits 13 and 15 (SYSFLT ) in the P1750A/AE Fault Register.
1
1
EX AD ER /
Illegal Address Error / An active LOW output from the PIC indicating an illegal address error
SING ERR
Single Error
whenreferencingmemoryorI/O. ItbecomesanactiveHIGHinputcalled
SINGLE ERROR for handshaking with the P1753 when the PIC is
programmedtosupportEDAC. Defaultstateafterresetishighimpedance.
WR PROT /
Write Protected /
Protection Flag
Either an active LOW output (WR PROT, following STRBD timing)
duringlegalmemorywritecycleswhennoprotectionoccurs,oranactive
high (PROT FLAG) signal indicating a protection error in a write cycle.
Either mode can be selected by programming the COMBO control
register. Default mode after reset is Write Protected.
PROT FLAG
ME PA ER /
Memory Parity Error
Terminal Count
An active LOW output indicating a Parity error when reading from
memory. It becomes an active HIGH output called RAM DISABLE for
handshaking with the P1753 when the PIC is programmed to support
EDAC.
RAMDIS
TC
An active HIGH output from the PIC indicating a bus time out or a
watchdog trigger.
Do c um e nt # MICRO-10 REV B
Pa g e 25 o f 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
STATUS BUS
Mnemonic
Name
Description
AK - AK
Access key
ActiveHIGHoutputscorrespondingtotheAKfieldoftheprocessorstatus
word used to match the Access Lock in the MMU for memory accesses
(a mismatch will cause the MMU to pull the MEM PRT ER signal LOW),
and also indicate the processor state (PS). Priveledged instructions can
beexecutedwithPS=0only. Thesesignalsaretri-stateforbuscyclesnot
assigned to this CPU
0
3
AS - AS
Address state
ActiveHIGHoutputscorrespondingtotheASfieldoftheprocessorstatus
wordthatselectsthepageregistergroupintheMMU. IntheDMAphysical
demultiplexedmode,AS(0:1)willreceivethe9thand10thmostsignificant
bitsofthephysicaladdressforuseintheBPUfunction. Thesesignalsare
tri-state in bus cycles not assigned to this CPU.
0
3
INFORMATION BUS
Mnemonic Name
IB - IB
Description
Information bus
A bi-directional time-multiplexed address/data BUS. IB is the most
0
15
0
significant bit.
EDC -EDC
Error Detection /
Correction Bus
An active HIGH output BUS used for detection of errors on the data BUS
0
5
(IB -IB ) and correction of single errors. When working in parity mode
0
15
EDC is the parity bit. EDC -EDC are undefined in this case.
0
1
5
A(0:1) /
Address Bus
An active HIGH output BUS from the PIC. Contains the address of the
currentbuscycleaslatchedbytheendofSTRBA. Insystemconfigurations
including the MMU function, the only active lines during memory cycles
are A(4:15). In this example, A(2:3) are high impedance (don't care) and
A(0:1) turn into inputs called Extended Addresses, EXT AD (0:1). In this
situation,thesetwolines,suppliedbytheMMU,willbeusedtooperatethe
programmable ready generation during bus cycles.
EXT ADR(0:1)
A(2:15)
EXT ADR -
Extended Address
Bus
A bi-directionaly active HIGH BUS. In CPU cycles, it is an output BUS
that is used to select one of 256 pages, 4K words each, expanding the
direct addressing space to 1M word. In DMA cycles, indicated by DMA-
ACK being active, it is also an output BUS except when programmed for
the physical demultiplexed DMA mode. In this example, it becomes an
inputtoreceivetheeightmostsignificantbitsoftheDMAphysicaladdress
for use in the BPU function.
0
EXT ADR
7
Do c um e nt # MICRO-10 REV B
Pa g e 26 o f 34
PACE 1757 M/ME
SIGNAL DESCRIPTIONS (Continued)
BUS STROBES AND QUALIFIERS
Mnemonic
Name
Description
STRBA (note 1) Address Strobe
An active HIGH output that can be used to externally latch the contents
of IB(0:15) into the address latches of the PIC and MMU at the HIGH to
LOW transition of the strobe. The signal is tristate during bus cycles not
assigned to this CPU. It is issued by the CPU and input to the MMU and
PIC.
STRBD (note 2) Data Strobe
An active LOW output used to read or write data from the PIC as well as
to strobe data in memory and XIO cycles. This signal is tri-state during
bus cycles not assigned to this CPU. It is interconnected in the same
manner as STRBA.
MEMW
Memory Write
Strobe
An active LOW output produced in memory write cycles by the PIC.
MEMR
IOW
Memory Read Strobe An active LOW output produced by the P1754 in memory read cycles.
I/O Write Strobe
I/O Read Strobe
Strobe Enable
An active LOW output produced by the P1754 in output write cycles.
An active LOW output produced by the P1754 during input read cycles.
IOR
STRB EN
An active LOW input, enabling the active state of the address outputs of
the P1754 and the MEMR, MEMW, IOR and IOW outputs. When a logic
"1" (if enabled by bits EST and EAD of the control register) it will
correspondingly tri-state the above signals.
INTA
Interrupt Acknowledge An active LOW output produced during any interrupt sequence
Strobe
corresponding to an output write to address 1000 (Hex).
DMA ACK
DMA Acknowledge
An active HIGH input from the DMA controller to the P1753 which
indicates a DMA cycle. Used to select the DMA table in the BPU memory
for protection. For example, this could allow the DMA channel to update
the program which could be write protected from the processor. In the
physical DMA mose, it will cause the Extended Address Liones (EXT
ADR )tobecomeinputsprovidingBPUprotectionoftheDMAtransfers.
0-7
EX RDY
External Data Ready
An active HIGH output from the MMU that indicates no wait states are
requested. It becomes inactive for one clock (inserting one wait state)
wheneveramemorypagedifferentthanthecurrentoneisaccessed(e.g.
a cache miss).
EX RDY1
External Data
Ready 1
An active LOW input to the PIC from the memory interface logic which at
a logical "1" overrides the internal RDYD generation and forces it to a
logical "0".
Note 1: One internal pulldown resistor is provided at the STRBA input. The nominal value is 40K Ohm and the maximum range is 20K Ohm to
80K Ohm. In designs with TTL devices loading STRBA, an additional external resistor may be required.
Note 2: One internal pullup is provided at the STRBD input. The nominal value is 40K Ohms and the maximum range is 20K-80K Ohms.
Do c um e nt # MICRO-10 REV B
Pa g e 27 o f 34
PACE 1757 M/ME
COMBO REGISTER MAP
CONTROL REGISTER (1F50/9F50)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QR1 QR2 QR3 QR4 ODD EEI EED EPR SPD WPT EB1 EB2 EIO GPT DMX DLP
CONTROL REGISTER 1 (1F51/9F51)
0
1
2
3
4
5
6
7
8
8
8
8
9
9
9
9
10
11
12
13
13
13
13
14
14
14
14
14
14
14
14
15
15
15
15
15
15
15
15
WA0 WA1 SPI RES* PEG
IDL
RESERVED
UNIMPLEMENTED MEMORY REGISTER 1 (1F55/9F55)
0
1
2
3
4
5
6
7
10
10
10
11
12
BL1 LO
BL1 HI
UNIMPLEMENTED MEMORY REGISTER 2 (1F56/9F56)
0
1
2
3
4
5
6
7
11
12
12
BL2 LO
BL2 HI
FIRST UNIMPLEMENTED OUTPUT COMMAND (1F57/9F57)
0
1
2
3
4
5
6
7
11
X
X
X
X
X
X
LAST SEQUENTIAL PIO OUTPUT COMMAND
FIRST UNIMPLEMENTED INPUT COMMAND (1F58/9F58)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
X
X
X
X
X
X
LAST SEQUENTIAL PIO INPUT COMMAND
FIRST FAILING ADDRESS REGISTER (9F59)
0
1
2
3
4
5
6
7
8
9
10
11
12
12
12
13
13
13
FIRST FAILING PHYSICAL ADDRESS - PADR (4:19)
FIRST FAILING DATA REGISTER (9F5A)
0
1
2
3
4
5
6
7
8
9
10
10
11
FIRST FAILING DATA WORD
MEMORY FAULT STATUS REGISTER (A00D)
0
1
2
3
4
5
6
7
8
9
11
ID
LPA
RESERVED
AS
* Reserved
Do c um e nt # MICRO-10 REV B
Pa g e 28 o f 34
PACE 1757 M/ME
COMBO REGISTER MAP DEFINITIONS
CONTROL REGISTER (1F50/9F50)
CONTROL REGISTER 1 (1F51)
(Default = 00C6H)
(Default = C3FFH)
QR1
QR2
QR3
QR4
Enable error detection/correction or parity
checking/generation for memory addresses
00000H-3FFFFH.
Enable error detection/correction or parity
checking/generation for memory addresses
40000H-7FFFFH
Enable error detection/correction or parity
checking/generation for memory addresses
80000H-BFFFFH.
Enable error detection/correction or parity
checking/generation for memory addresses
C0000H-FFFFFH.
WA0/ Number of WAIT STATES on RDYA
WA1
SPI
Enable illegal PIO detection for MIL-
STD1750A spare I/O spaces.
PEG Determines what is generated when both
EDAC and parity checks are disabled.
IDL
Enables/disables the genertion of an idle
cycle betwee BUS REQ and BUS GNT,
during read cycles, allowing for one
additional clock cycle to release the IB.
UNIMPLEMENTED MEMORY REGISTER 1 (1F55)
ODD Enable odd parity, 1 = ODD, 0 = EVEN
EEI
BL1 LO Low boundary of unimplemented block 1 of
Enable error detection/correction (EDAC) on
instruction fetch only.
Enable error detection/correction (EDAC) on
operand (data) fetch only.
Enable parity detection function. (If both
EPR and either EEI or EED are enabled, EEI
or EED will take preference.)
Enable 1 wait state on MMU cache miss
cycle (1 = 1 WAIT, 0 = NO WAIT).
memory.
BL1 HI High boundary of unimplemente block 1 of
memory.
EED
EPR
UNIMPLEMENTED MEMORY REGISTER 2 (1F56)
BL2 LO Low boundary of unimplemented block 2 of
SPD
memory.
BL2 HI High boundary of unimplemented block 2 of
memory.
WPT Enable protected write strobe (WR PROT
PIN).
1: WR PROT = write protected strobe
0: WR PROT = write protect level
(1 = write protect memory)
Enable block 1 of unimplemented memory
(as defined in unimplemented memory
register 1).
FIRST UNIMPLMENTED OUTPUT COMMAND
REGISTER (1F57)
BITS 0:5
Not used.
EB1
EB2
EIO
GPT
BITS 6:15
First unused sequential PIO output
command.
Enable block 2 of unimplementd memory (as
defined in unimplemented memory register
2).
Enable illegal PIO detection (as defined in
last implemented input and output registers,
and MIL-STD-1750A reserved I/O space).
Enable global memory protect (Set by
RESET, and reset by I/O command 4003).
FIRST UNIMPLMENTED INPUT COMMAND
REGISTER (1F58)
BITS 0:5
BITS 0:6
Not used.
First unused sequential PIO input
command.
FIRST FAILING ADDRESS REGISTER (1F59)
DMX Demultiplexed Address/data Bus in DMA
cycles.
PADR (4:19) 16 LSB of the physical address of the
first failure.
DLP
Logical/Physical DMA (1 = LOGICAL, 0 =
Physical).
FIRST FAILING DATA REGISTER (1F5B)
BITS 0:15
"1" indicates the position of the wrong/
corrected bit in the data word.
MEMORY FAULT STATUS REGISTER (A00D)
LPA
ID
Page address within the group.
Instruction/data
AS
Group address.
Do c um e nt # MICRO-10 REV B
Pa g e 29 o f 34
PACE 1757 M/ME
PIC REGISTER MAP
CONTROL REGISTER (1F40, 9F40)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
PR1 PR2 PR3 PR4 ODD EST EAD EXR
SPI CNF EB1 EB2 EIO
LIO
LME
STATUS REGISTER (9F41)
0
1
2
3
4
5
6
7
8
9
10
10
11
12
13
14
14
14
15
CPU CMB PIC RESERVED STB ADR TWD TBT
RESERVED
IFL
MEMORY READY PROGRAM REGISTER (1F42, 9F42)
0
1
2
3
4
5
6
7
7
7
8
8
8
9
11
11
11
11
11
11
12
12
12
13
15
15
15
15
15
15
15
15
MEM Q1
MEM Q2
MEM Q3
MEM Q4
I/O READY PROGRAM REGISTER (1F43, 9F43)
0
1
2
3
4
5
5
5
6
9
10
IOQ3
13
IO Q1
IO Q2
IO Q4
PROGRAM REGISTER (1F44, 9F44)
0
1
2
3
4
6
9
10
10
10
13
14
14
14
CLOCK FREQUENCY (MHZ)
EBT SBT EWD SWD
RESERVED
WATCH DOG TIMER (1F45, 9F45)
0
1
2
3
4
6
7
8
9
12
12
12
13
13
13
WATCHDOG SETUP COUNT
UNIMPLEMENTED MEMORY REGISTER (1F46, 9F46)
0
1
2
3
4
5
6
7
8
9
BL1 LO
BL1 HI
BL2 LO
BL2 HI
FIRST UNIMPLEMENTED OUTPUT COMMAND (1F47, 9F47)
0
1
2
3
4
5
6
7
8
9
10
14
14
14
X
X
X
X
X
X
FIRST UNIMPLEMENTED OUTPUT COMMAND
FIRST UNIMPLEMENTED INPUT COMMAND (1F48, 9F48)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
X
X
X
X
X
X
FIRST UNIMPLEMENTED INPUT COMMAND
FIRST FAILING ADDRESS REGISTER (9F49)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
FIRST FAILING ADDRESS
Do c um e nt # MICRO-10 REV B
Pa g e 30 o f 34
PACE 1757 M/ME
PIC REGISTER MAP DEFINITIONS
CONTROL REGISTER (Default = 0000)
I/O READY PROGRAM REGISTER
PR1
PR2
PR3
PR4
Enable Parity Checking/Generation for
Memory Addresses 0000-3FFF.
Enable Parity Checking/Generation for
Memory Addresses 4000-7FFF.
Enable Parity Checking/Generation for
Memory Addresses 8000-BFFF.
Enable Parity Checking/Generation for
Memory Addresses C000-FFFF.
(Default = Undefined)
IO Q1
IO Q2
IO Q3
IO Q4
Lower section number of wait states.
Second section number of wait states.
Third section number of wait states.
Upper section number of wait states.
PROGRAM REGISTER (Default = 0000)
CFB
EBT
SBT
0:5, Clock Frequency Bits (MHz).
Enable Bus Time-out Function.
Select Bus Time-out Limit; 1 = 128
Cycles, 0 = 64 Cycles.
ODD Enable ODD Parity.
EST
Enable Three State Control on PIC
Generated Strobes: IOR, IOW, MEMR,
MEMW.
EWD
SWD
Enable Watch Dog Function.
Select Watch Dog Clock, 1 = 1KHz, 0 =
1MHz.
EAD
EXR
SPI
Enable Three State Control on PIC
Generated Address: A -A .
0
15
Extends ready generation over the full I/O
space when = 1. (Default = 0)
Enables IILEGAL PIO detection for MIL-STD-
1750A spare I/O spaces. 1 = Spare I/O legal,
0 = Default = spare I/O illegal.
EDAC Function on MMU/COMBO; 1 = used,
0 = not used.
Enable Block 1 of Unimplemented Memory,
as Defined in the Unimplemented Memory
Register.
Enable Block 2 of Unimplemented Memory,
as Defined in the Unimplemented Memory
Register
Enable illegal PIO Detection, as defined in
Last Implemented Input and Output
Registers.
Enable Long I/O Ready Generation, 1ms to
15ms, I/O Addresses 0000-00FF, 8000-
80FF.
Enable Long Memory Ready Generation,
1ms to 15ms, Addresses 0000-3FFF.
WATCH DOG TIMER REGISTER (Default = 0000)
BITS 0:15, Watch Dog set-up Count.
UNIMPLEMENTED MEMORY REGISTER
(Default = Undefined)
CNF
EB1
BL1 LO
BL1 HI
BL2 LO
BL2 HI
Low boundary of unimplemented block
1 of memory.
High boundary of unimplemented block
1 of memory.
Low boundary of unimplemented block
2 of memory.
High boundary of unimplemented block
2 of memory.
EB2
EIO
LIO
FIRST UNIMPLEMENTED OUTPUT COMMAND
REGISTER (Default = Undefined)
BITS 0:5
Not used.
BITS 6:15 First unused sequential PIO output
command.
LME
FIRST UNIMPLEMENTED INPUT COMMAND
REGISTER (Default = Undefined)
STATUS REGISTER (Default = 0000)
CPU CPU Passed PIC System Test.
CMB COMBO Chip Passed PIC System Test.
BITS 0:5
Not used.
BITS 6:15 First unused sequential PIO input
command.
PIC
STB
PIC Chip Passed PIC System Test.
Reserved.
FIRST FAILING REGISTER (Default = Undefined)
BITS 0:15 16 LSB of the physical address of the
first failure.
ADR Reserved.
TWD Watch Dog reached terminal count.
TBT
IFL
Bus Time-out reached terminal count.
Interrupt Flag-Shows the last interrupt I/O
command implemented in the software.
MEMORY READY PROGRAM REGISTER
(Default = FFFF)
MEM Q1
MEM Q2
MEM Q3
MEM Q4
Lower Block number of wait states.
Second Block number of wait states.
Third Block number of wait states.
Upper Block number of wait states.
Do c um e nt # MICRO-10 REV B
Pa g e 31 o f 34
PACE 1757 M/ME
PACKAGE OUTLINE
Do c um e nt # MICRO-10 REV B
Pa g e 32 o f 34
PACE 1757 M/ME
1757M/ME 144-LEAD QUAD FLATPACK OUTLINE
Straight Leads
Gullwing Leads
130 ± 10
N/A
175 ± 20
25 ± 5
A
A1
b
8
6
± 2
± 2
8
6
± 2
± 1
c
1750 ± 15
1150 ± 12
875 REF
1750 ± 5
1150 ± 12
875 REF
N/A
1450 ± 10
1150 ± 12
875 REF
1450 ± 10
1150 ± 12
875 REF
75 ± 15
25 ± 5
D
D1
D2
E
E1
E2
L1
L2
L
N/A
300 ± 5
N/A
150 ± 10
25 ± 2
R1
R2
O1
O2
G
N/A
25 ± 2
N/A ± 4
N/A
0° 7°
0° 7°
8
8
± 4
144
144
N
ORDERING INFO
Do c um e nt # MICRO-10 REV B
Pa g e 33 o f 34
PACE 1757 M/ME
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
MICRO-10
PACE1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM
ISSUE
REV.
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
DATE
ORIG
A
May-89
Jul-04
RKK
New Data Sheet
JDB
JDB
Added Pyramid logo
B
Sep-05
Re-created electronic version
Do c um e nt # MICRO-10 REV B
Pa g e 34 o f 34
相关型号：
©2020 ICPDF网 联系我们和版权申明