概述
数据手册P3C1011-35JM 概述
HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM 高速128K ×16 （ 2 MEG ）静态CMOS RAM
P3C1011-35JM 数据手册
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PDF下载P3C1011
HIGH SPEED 128K x 16 (2 MEG)
STATIC CMOS RAM
FEATURES
2.0V Data Retention
Easy Memory Expansion Using CE and OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down when deselected
Packages
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
— 20/25/35 (Military)
Low Power
— 360 mW (max.)
Single 3.3V ± 0.3V Power Supply
—44-Pin SOJ, TSOP II
DESCRIPTION
The P3C1011 is a 131,072 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 3.3V ± 0.3V tolerance power
supply.
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either CE or OE is HIGH or WE is
LOW.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C1011
is a member of a family of PACE RAM™ products offer-
ing fast access times.
For both reading and writing, the Byte Enable control lines
(BLE for I/O0-7 and BHE for I/O8-15) allow for the selection
of only 8 of the 16 I/O lines if desired. When a Byte
Enable control line is HIGH, the corresponding I/Os are
active.
The P3C1011 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pinsA0 toA17. Reading is
Package options for the P3C1011 include 44-pin SOJ and
TSOP packages.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
SOJ
TSOPII
Document # SRAM131 REV OR
Revised March 2006
1
P3C1011
MAXIMUMRATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +4.6
V
TBIAS
TemperatureUnder
Bias
–55 to +125
°C
TerminalVoltagewith
Respect to GND
–0.5 to
VCC +0.5
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–65 to +150
20
°C
VTERM
TA
V
mA
OperatingTemperature
–55 to +125 °C
CAPACITANCES(4)
VCC = 3.3V, TA = 25°C, f = 1.0MHz
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
Grade(2)
VSS
Parameter
Typ.
VCC
Symbol
Conditions
Unit
VIN = 0V
pF
pF
CIN
Input Capacitance
I/OCapacitance
8
8
Industrial
–40°C to +85°C
0V
0V
0V
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
Commercial 0°C to +70°C
Military -55°Cto+125°C
VOUT = 0V
COUT
DC ELECTRICAL CHARACTERISTICS
Overrecommendedoperatingtemperatureandsupplyvoltage(2)
P3C1011
Symbol
Parameter
Test Conditions
Unit
Min
Max
VIH
VIL
2.0
VCC +0.3
0.8
Input High Voltage
Input Low Voltage
V
V
–0.3(3)
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
0.4
V
VOH
Output High Voltage
(TTL Load)
2.4
-1
V
+1
+1
µA
VCC = Max.
ILI
Input Leakage Current
Output Leakage Current
VIN = GND to VCC
µA
-1
VCC = Max.,
ILO
CE = VIH,
VOUT = GND to VCC
___
40
10
mA
CE ≥ VIH
Standby Power Supply
Current (TTL Input Levels)
VCC= Max,
ISB
f = Max., Outputs Open
VIN ≥ VIH orVIN ≤ VIL
___
mA
CE ≥ VCC - 0.2V
VCC= Max,
Standby Power Supply
Current
(CMOS Input Levels)
ISB1
f = 0, Outputs Open
VIN ≥ VCC - 0.3V or
VIN ≤ 0.3V
Document # SRAM131 REV OR
Page 2 of 10
P3C1011
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
–12 –15 –20
–25
–35
–10
Commercial
75
85
70
65
90
85
95
80
90
mA
mA
ICC
80
95
75
90
N/A
N/A
Dynamic Operating Current* Industrial
Military
100
N/A N/A
mA
*VCC = 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 3.3V ± 0.3V, All Temperature Ranges)(2)
-12
-25
-35
-10
-15
-20
Sym.
Parameter
Unit
Min
Max
Min Max Min Max
Min Max
Max Min Max Min
tRC
tAA
12
10
15
ReadCycleTime
20
20
35
ns
ns
25
12
12
Address Access Time
10
10
15
15
35
35
25
25
tAC
20
ns
Chip Enable Access Time
OutputHoldfromAddressChange
Chip Enable to Output in Low Z
ns
ns
3
3
3
3
3
3
3
3
3
3
tOH
tLZ
tHZ
tOE
3
3
8
8
12
12
ns
ns
Chip Disable to Output in High Z
Output Enable Low to Data Valid
5
5
6
6
7
7
10
10
tOLZ
tOHZ
tPU
ns
ns
ns
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
0
0
0
0
0
0
0
8
0
0
0
0
0
5
6
7
10
12
Chip Disable to Power Down Time
Byte Enable to Data Valid
tPD
ns
ns
10
5
12
6
15
7
20
35
12
25
10
tBE
tLZBE
tHZBE
8
0
0
0
0
Byte Enable to Low Z
Byte Disable to High Z
0
0
ns
ns
6
6
7
8
10
12
Document # SRAM131 REV OR
Page 3 of 10
P3C1011
TIMING WAVEFORM OF READ CYCLE NO. 1
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL not more negative than –2.0V and
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESSmustbevalidpriorto,orcoincidentwithCE transitionLOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
VIH ≤ VCC + 0.5V, are permissible for pulse widths up to 20ns.
Document # SRAM131 REV OR
Page 4 of 10
P3C1011
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 3.3V ± 0.3V, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
Parameter
Unit
Sym.
Max
Min Max Min Max Min
Min Max Min Max Min Max
tWC
tCW
10
7
15
10
Write Cycle Time
12
8
20
10
35
15
25
12
ns
ns
Chip Enable Time to End of
Write
tAW
tAS
Address Valid to End of Write
7
8
10
10
12
15
ns
Address Set-up Time to Write
Start
0
7
0
5
0
8
0
6
0
10
0
0
10
0
0
12
0
0
15
0
ns
ns
ns
ns
tWP
tAH
tDW
Write Pulse Width
AddressHoldTime
Data Valid to End of Write
7
8
10
12
tDH
tWZ
DataHoldTime
0
0
0
0
0
0
ns
Write Enable to Output in High Z
5
6
7
8
10
12 ns
tOW
Output Active from End of Write
3
3
3
3
3
3
3
3
3
3
3
3
ns
ns
tLZWE WE High to Low Z
tBW Byte Enable to End of Write
7
8
10
10
15
ns
12
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (CE CONTROLLED)
Document # SRAM131 REV OR
Page 5 of 10
P3C1011
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (BLE OR BHE CONTROLLED)
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (WE CONTROLLED, OE LOW)
Document # SRAM131 REV OR
Page 6 of 10
P3C1011
AC TEST CONDITIONS
InputPulseLevels
VSS to 3.0V
Input Rise and Fall Times
InputTimingReferenceLevel
OutputTimingReferenceLevel
OutputLoad
3ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load
Figure2. TheveninEquivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1041, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
TRUTH TABLE
CE OE WE BLE BHE I/O0 - I/O7
I/O8 - I/O15
High Z
DOUT
Power
Standby
Mode
H
L
X
L
X
H
X
L
X
L
High Z
DOUT
Power-down
Read All Bits
Active
Active
Active
L
L
L
L
H
H
L
H
L
DOUT
High Z
DOUT
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
H
High Z
L
L
L
L
X
X
X
H
L
L
L
L
L
H
L
DIN
DIN
DIN
High Z
DIN
Active
Active
Active
Active
Write Lower Bits Only
L
H
X
High Z
High Z
Write Upper Bits Only
H
X
High Z
Selected, Outputs Disabled
Document # SRAM131 REV OR
Page 7 of 10
P3C1011
ORDERING INFORMATION
Document # SRAM131 REV OR
Page 8 of 10
P3C1011
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J8
# Pins
44 (400 mil)
Symbol
Min
Max
0.148
-
0.023
0.013
1.130
A
A1
b
C
D
0.128
0.082
0.013
0.007
1.120
e
0.050 BSC
E
0.435
0.395
0.370 BSC
0.445
0.405
E1
E2
Q
0.025
-
TSOP II THIN SMALL OUTLINE PACKAGE
Pkg #
T2
# Pins
44
Symbol
Min
Max
A
A2
b
D
E
0.039
0.033
0.012
0.396
0.721
0.047
0.045
0.016
0.404
0.729
e
0.0315 BSC
0.462 0.470
HD
Document # SRAM131 REV OR
Page 9 of 10
P3C1011
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM131
P3C1011 HIGH SPEED 128K x 16 (4 MEG) STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
DATE
REV.
DESCRIPTIONOFCHANGE
OR
Mar-06
JDB
NewDataSheet
Document # SRAM131 REV OR
Page 10 of 10
P3C1011-35JM 相关器件
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