P3C1024L55SC [PYRAMID]
ULTRA LOW POWER 128K x 8 CMOS STATIC RAM; 超低功耗128K ×8 CMOS静态RAM
| 型号： | P3C1024L55SC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA LOW POWER 128K x 8 CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P3C1024L
ULTRA LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
Common Data I/O
V
CC Current (Commercial/Industrial)
— Operating: 10mA/12mA
— CMOS Standby: 10µA/10µA
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Access Times
—55/70 (Commercial or Industrial)
Single 3.3 Volts ± 0.3V Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
Packages
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P3C1024Lis a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V ± 0.3V tolerance power
supply.
locations are specified on address pinsA0 toA16. Read-
ing is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE1 or OE is HIGH or WE or CE2 is LOW.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P3C1024L is packaged in a 32-pin TSOP and 445
mil SOP.
The P3C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM132 REV OR
Revised April 2006
1
P3C1024L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Supply Voltage
3.0V ≤ VCC ≤ 3.6V
3.0V ≤ VCC ≤ 3.6V
Industrial (-40°C to 85°C)
MAXIMUM RATINGS(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
VCC
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND
Operating Ambient Temperature
Storage Temperature
Min
-0.3
-0.3
Max
Unit
3.9
V
V
VTERM
TA
VCC + 0.3
-55
-65
125
150
20
°C
°C
STG
IOUT
ILAT
Output Current into Low Outputs
mA
Latch-up Current
>200
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Symbol
Test Conditions
Max
Unit
Parameter
Min
Output High Voltage
(I/O0 - I/O7)
VOH
IOH = –1mA, VCC = 3.3V
2.4
V
Output Low Voltage
(I/O0 - I/O7)
VOL
IOL = 2.1mA
0.4
V
Input High Voltage
Input Low Voltage
2.2
VCC + 0.3
0.8
V
V
VIH
VIL
-0.3
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC
Ind'l.
Com'l.
-2
-1
+2
+1
µA
Input Leakage Current
Output Leakage Current
ILI
Ind'l.
-2
-1
+2
+1
µA
ILO
CE1 ≥ VIH or CE2 ≤ VIL Com'l.
VCC Current
TTL Standby Current
(TTL Input Levels)
VCC = 3.6V, IOUT = 0 mA
ISB
3
mA
µA
CE1 = VIH or CE2 = VIL
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 5.5V, IOUT = 0 mA
ISB1
10
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V
Document # SRAM132 REV OR
Page 2 of 9
P3C1024L
CAPACITANCES(4)
(VCC = 3.3V, TA = 25°C, f = 1.0 MHz)
Unit
pF
Symbol
Parameter
Test Conditions
VIN = 0V
Max
8
CIN
Input Capacitance
VOUT = 0V
COUT
9
pF
Output Capacitance
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature Range
-55
-70
Unit
10
8
mA
Commercial
Industrial
ICC
Dynamic Operating Current
12
10
mA
Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-70
-55
Parameter
Unit
ns
Symbol
Max
Min
Max
Min
tRC
Read Cycle Time
Address Access Time
55
70
55
55
70
70
ns
tAA
Chip Enable Access
Time
tAC
tOH
ns
ns
ns
Output Hold from
Address Change
10
10
10
10
Chip Enable to
Output in Low Z
tLZ
Chip Disable to
Output in High Z
tHZ
ns
ns
25
35
20
25
Output Enable Low
to Data Valid
tOE
Output Enable Low to
Low Z
tOLZ
5
0
5
0
ns
ns
Output Enable High
to High Z
tOHZ
tPU
20
55
25
70
Chip Enable to Power
Up Time
ns
ns
Chip Disable to
Power Down Time
tPD
Document # SRAM132 REV OR
Page 3 of 9
P3C1024L
READ CYCLE NO. 1 (OE CONTROLLED)(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
4. Transition is measured ± 200 mV from steady state voltage prior
1. WE is HIGH for READ cycle.
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE1 transition LOW or CE2 transition HIGH.
Document # SRAM132 REV OR
Page 4 of 9
P3C1024L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-55
-70
Symbol
Parameter
Unit
Min
Max
Min
Max
55
70
ns
ns
tWC
tCW
tAW
tAS
tWP
tAH
Write Cycle Time
Chip Enable Time
to End of Write
40
40
60
60
Address Valid to
End of Write
ns
Address Set-up
Time
0
40
0
0
50
0
ns
ns
ns
Write Pulse Width
Address Hold
Time
Data Valid to End
of Write
tDW
25
0
30
0
ns
ns
tDH
tWZ
Data Hold Time
Write Enable to
Output in High Z
20
25
ns
ns
Output Active from
End of Write
tOW
10
10
WRITE CYCLE NO. 1 (WE CONTROLLED)(6)
Notes:
6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM132 REV OR
Page 5 of 9
P3C1024L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
TRUTH TABLE
AC TEST CONDITIONS
Mode
Standby
Standby
CE1 CE2 OE WE I/O
Power
Standby
Standby
Input Pulse Levels
GND to 3.0V
H
X
X
X
High Z
High Z
X
L
X
X
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
Output
Disabled
L
H
H
H
High Z
Active
See Fig. 1 and 2
DOUT
DIN
L
L
H
H
L
H
L
Read
Write
Active
Active
X
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.75V (Thevenin Voltage) at the comparator input, and a
595Ω resistor must be used in series with DOUT to match 645Ω
(Thevenin Resistance).
Because of the high speed of the P3C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance
leadsthatcausesupplybouncemustbeavoidedbybringingtheVCC
and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between VCC and ground.
Document # SRAM132 REV OR
Page 6 of 9
P3C1024L
DATA RETENTION
Symbol
Test Conditions
Min
Unit
Parameter
Max
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
(1)
ICCDR
VDR = 2.0V
10
µA
Chip Deselect to Data
Retention Time
tCDR
See Retention Waveform
0
ns
µs
Operating Recovery Time(2)
100
tR
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
2. VCC ramp from VDR to VCC (min) > 100 µs for full device operation.
LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED)
LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)
Document # SRAM132 REV OR
Page 7 of 9
P3C1024L
ORDERING INFORMATION
SELECTION GUIDE
The P3C1024L is available in the following temperature, speed and package options.
Speed
Temperature
Range
Package
-55
-70
Commercial
Plastic SOP (445 mil)
TSOP
-55SC
-55TC
-55SI
-55TI
-70SC
-70TC
-70SI
-70TI
Industrial
Plastic SOP (445 mil)
TSOP
TSOP PIN CONFIGURATION
Document # SRAM132 REV OR
Page 8 of 9
P3C1024L
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S12
# Pins
32 (445 Mil)
Symbol
Min
-
0.004
0.014
0.006
0.790
Max
0.118
-
0.020
0.012
0.820
A
A1
b2
C
D
e
0.050 BSC
E
H
h
0.435
0.546
0.010
0.023
0°
0.455
0.566
0.029
0.039
8°
L
α
TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm)
Pkg #
T3
32
All dimensions in inches except as noted
# Pins
Symbol
Min
-
Max
A
A2
b
D
E
0.048
0.042
0.011
0.729
0.323
0.037
0.006
0.720
0.307
e
0.50 mm BSC
0.779 0.796
HD
Document # SRAM132 REV OR
Page 9 of 9
P3C1024L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM132
P3C1024L LOW POWER 128K x 8 CMOS STATIC RAM
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
OR
Apr-06
JDB
New Data Sheet
Document # SRAM132 REV OR
Page 10 of 9
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