P4C1024-35C6M [PYRAMID]
Standard SRAM, 128KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32;型号: | P4C1024-35C6M |
厂家: | PYRAMID SEMICONDUCTOR CORPORATION |
描述: | Standard SRAM, 128KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32 CD 静态存储器 内存集成电路 |
文件: | 总14页 (文件大小:923K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
P4C1024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
FEATURES
Fast tOE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (450 x 550 mil)
—32-Pin LCC (400 x 820 mil) [Two-Sided]
—32-Pin Ceramic SOJ
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial/Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
DESCRIPTION
The P4C1024 device provides asynchronous operations
with matching access and cycle times. Memory loca-
tions are specified on address pins A0 to A16. Reading
is accomplished by device selection (CE1 low and CE2
high) and output enabling (OE) while write enable (WE)
remains HIGH. By presenting the address under these
conditions, the data in the addressed memory location
is presented on the data input/output pins. The input/
output pins stay in the HIGH Z state when either CE1 or
OE is HIGH or WE or CE2 is LOW.
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of PACE RAM™ products offer-
ing fast access times.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (P300, C10, C11),
SOJ (J300, J400, CJ1),
LCC (L1),
SOLDER SEAL
LCC (L6)
FLATPACK (FS-3) SIMILAR
Document # SRAM124 REV C
Revised December 2011
P4C1024
MAꢀIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
VTERM
V
1.0
IOUT
50
mA
TA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLꢁ VOLTAGE
Ambient
Temperature
Grade(2)
GND
Symbol
Parameter
Conditions Typ. Unit
VCC
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
0V
0V
0V
VIN = 0V
pF
pF
Input Capacitance
Output Capacitance
8
Industrial
COUT
VOUT = 0V
10
Commercial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C1024
P4C1024L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
2.2
VCC +0.5
2.2
VCC +0.5
VIH
VIL
Input High Voltage
Input Low Voltage
V
V
V
–0.5(3)
0.8
–0.5(3)
0.8
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
VHC
VLC
CMOS Input High Voltage
CMOS Input Low Voltage
–0.5(3)
0.2
–0.5(3)
0.2
V
V
VCD
VOL
–1.2
–1.2
VCC = Min., IIN = –18 mA
IOL = +8 mA, VCC = Min.
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
V
V
0.4
0.4
Output High Voltage
(TTL Load)
VOH
IOH = –4 mA, VCC = Min.
2.4
2.4
VCC = Max.
Mil.
–10
–5
+10
+5
–5
n/a
+5
n/a
ILI
Input Leakage Current
Output Leakage Current
µA
VIN = GND to VCC
Ind./Com’l.
Mil.
VCC = Max., CE = VIH,
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
ILO
VOUT = GND to VCC Ind./Com’l.
___
___
___
___
mA
CE1 ≥ VIH or
CE2 ≤VIL,
VCC= Max,
Mil.
Ind./Com’l.
35
30
25
n/a
Standby Power Supply
Current (TTL Input Levels)
ISB
f = Max., Outputs Open
___
___
___
___
25
20
2
n/a
mA
CE1 ≥ VHC or
CE2 ≤VLC,
VCC= Max,
Mil.
Ind./Com’l.
Standby Power Supply
Current
ISB1
(CMOS Input Levels)
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
Notes:
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAꢀIMꢁM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢀIMꢁM rating conditions for extended
Document # SRAM124 REV C
Page 2 of 14
P4C1024
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Range
Symbol
Parameter
-15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit
Commercial
190 160 150 145 N/A N/A N/A N/A N/A N/A mA
N/A 175 165 160 155 N/A N/A N/A N/A N/A mA
N/A 150 140 135 130 125 115 110 105 100 mA
Dynamic
Operating
Current*
ICC
Industrial
Military
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
DATA RETENTION CHARACTERISTICS (P4C1024L, Military Temperature Only)
Typ.*
VCC=
2.0V
Max
VCC=
2.0V
Symbol
Parameter
Test Condition
Min
Unit
3.0V
3.0V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
ICCDR
50
200
400
600
µA
CE1 ≥ VCC – 0.2V or
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V
tCDR
Chip Deselect to
ns
ns
0
Data Retention Time
Operation Recovery Time
†
§
tR
tRC
*TA = +25°C
§
tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM124 REV C
Page 3 of 14
P4C1024
AC ELECTRICAL CHARACTERISTICS—READ CꢁCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
-45
-55
-70
-85
-100
-120
Sym Parameter Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Read Cycle Time 15
20
25
35
45
55
70
85
100
120
ns
tRC
tAA
Address Access
Time
15
15
20
20
25
25
35
35
45
45
55
55
70
70
85
85
100
100
120 ns
Chip Enable
Access Time
120 ns
tAC
tOH
tLZ
Output Hold from
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
ns
ns
Address Change
Chip Enable to
3
Output in Low Z
Chip Disable to
Output in High Z
8
7
9
9
11
11
15
15
20
20
25
25
30
30
35
35
40
40
50
50
ns
ns
ns
ns
ns
ns
tHZ
tOE
tOLZ
tOHZ
tPU
Output Enable
Low to Data Valid
Output Enable
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Low to Low Z
Output Enable
High to High Z
7
9
11
20
15
20
20
25
25
30
30
35
35
40
40
45
50
50
Chip Enable to
0
Power Up Time
Chip Disable
to Power Down
Time
12
20
tPD
Document # SRAM124 REV C
Page 4 of 14
P4C1024
TIMING WAVEFORM OF READ CꢁCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CꢁCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CꢁCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
Notes:
5. WE is HIGH for READ cycle.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW and CE2 transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Document # SRAM124 REV C
Page 5 of 14
P4C1024
AC CHARACTERISTICS—WRITE CꢁCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
-45
-55
-70
-85
-100
-120
Symbol
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time
15
12
12
0
20
15
15
0
25
18
20
0
35
22
25
0
45
30
35
0
55
35
45
0
70
45
60
0
85
50
70
0
100
60
85
0
120
75
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Time
tCW
to End of Write
Address Valid to
tAW
End of Write
Address Set-up
Time
tAS
tWP Write Pulse Width
12
0
15
0
18
0
22
0
25
0
30
0
40
0
45
0
55
0
70
0
tAH Address Hold Time
Data Valid to End
of Write
tDW
7
8
10
0
15
0
20
0
25
0
30
0
35
0
45
0
60
0
tDH Date Hold Time
0
0
Write Enable to
tWZ
8
10
11
15
18
20
25
30
40
50
Output in High Z
Output Active from
End of Write
tOW
3
3
3
3
3
3
3
3
3
3
TIMING WAVEFORM OF WRITE CꢁCLE NO. 1 (WE CONTROLLED)(11)
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW
14. Write Cycle Time is measured from the last valid address to the first
.
transitioning address.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state.
Document # SRAM124 REV C
Page 6 of 14
P4C1024
TIMING WAVEFORM OF WRITE CꢁCLE NO. 2 (CE CONTROLLED)(11)
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
Mode
CE1 CE2 OE WE I/O
Power
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
H
ꢀ
ꢀ
High Z
High Z
Standby
Standby
ꢀ
ꢀ
ꢀ
Standby
Standby
1.5V
ꢀ
L
1.5V
L
H
H
H
High Z Active
DOUT Disabled
See Fig. 1 and 2
DOUT
L
L
H
H
L
H
L
Read
Write
Active
ꢀ
High Z Active
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for ex-
ample, a 50Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω
resistor must be used in series with DOUT to match 166Ω (Thevenin
Resistance).
Becauseoftheultra-highspeedoftheP4C1024,caremustbetaken
when testing this device; an inadequate setup can cause a normal
functioningparttoberejectedasfaulty. Longhigh-inductanceleads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
Document # SRAM124 REV C
Page 7 of 14
P4C1024
ORDERING INFORMATION
Document # SRAM124 REV C
Page 8 of 14
P4C1024
SOJ SMALL OUTLINE IC PACKAGE (300 mil)
Pkg #
J300
# Pins
32 (300 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.128
0.082
0.016
0.007
0.820
0.020
0.010
0.830
C
D
e
0.050 BSC
0.335 BSC
0.295 0.305
0.267 BSC
0.025
E
E1
E2
Q
-
SOJ SMALL OUTLINE IC PACKAGE (400 mil)
Pkg #
J400
# Pins
32 (400 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.128
0.082
0.015
0.007
0.820
0.020
0.013
0.830
C
D
e
0.050 BSC
E
0.435
0.395
0.445
0.405
E1
E2
Q
0.370 BSC
0.025
-
Document # SRAM124 REV C
Page 9 of 14
P4C1024
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P300
# Pins
32 (300 mil)
Symbol
Min
Max
A
A1
b
-
0.200
-
0.015
0.014
0.048
0.008
1.580
0.270
0.300
0.022
0.054
0.014
1.620
0.300
0.310
b2
C
D
E1
E
e
0.100 BSC
eB
0.320
0.120
0°
0.390
0.140
15°
L
α
SOLDER SEAL FLAT PACKAGE
Pkg #
FS-3
# Pins
32
Symbol
Min
0.097
0.015
0.003
-
Max
0.125
0.019
0.009
0.830
0.420
0.450
-
A
b
c
D
E
0.400
-
E1
E2
E3
e
0.180
0.030
-
0.050 BSC
L
0.250
0.370
0.045
0.045
-
Q
S
0.020
-
0.000
-
S1
M
N
0.002
32
Document # SRAM124 REV C
Page 10 of 14
P4C1024
SIDEBRAZED DUAL IN-LINE PACKAGE (600 mil)
Pkg #
C10
# Pins
32 (600 mil)
Symbol
Min
Max
A
b
-
0.225
0.026
0.065
0.018
1.680
0.620
0.014
0.045
0.008
-
b2
C
D
E
0.510
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.070
S1
S2
-
-
SIDEBRAZED DUAL IN-LINE PACKAGE (400 mil)
Pkg #
C11
32 (400 mil)
# Pins
Symbol
Min
Max
A
b
-
0.232
0.023
0.065
0.018
1.700
0.410
0.014
0.038
0.008
-
b2
C
D
E
0.350
eA
e
0.400 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.060
S1
S2
-
-
Document # SRAM124 REV C
Page 11 of 14
P4C1024
2-SIDED LEADLESS CHIP CARRIER
Pkg #
L1
# Pins
32
Symbol
Min
Max
0.100
0.028
0.022
-
A
b
0.080
0.022
0.006
0.040
0.820
0.392
b1
b2
D
0.840
0.400
E
e
0.050 BSC
0.012 REF
h
L
0.070
0.080
0.110
0.015
L1
L2
N
0.090
0.003
32
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
L6
# Pins
Symbol
A
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
0.558
-
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
L2
ND
NE
0.045
0.075
7
9
Document # SRAM124 REV C
Page 12 of 14
P4C1024
CERAMIC SOJ SMALL OUTLINE IC PACKAGE
Pkg #
# Pins
Symbol
A
CJ1
32
Min
0.120
0.088
0.070
0.010
0.030R
0.020
0.025
0.816
0.750
0.419
0.430
0.360
Max
0.165
0.120
REF
A1
A2
B
REF
B1
B2
B3
D
TYP
REF
0.045
0.838
REF
D1
E
0.431
0.445
0.380
E1
E2
e
0.050 BSC
e1
0.038
TYP
e2
0.005
0.005
0.030
0.020
j
TYP
0.040
TYP
S
S1
Document # SRAM124 REV C
Page 13 of 14
P4C1024
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM124
P4C1024 HIGH SPEED 128K x 8 DꢁAL CHIP ENABLE CMOS STATIC RAM
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
OR
1997
DAB
New Data Sheet
A
B
C
Oct-05
Jan-11
Dec-11
JDB
JDB
JDB
Change logo to Pyramid
Added L1 package, corrected data retention table
Removed Selection Guide, combined commercial and industrial temps in
features section
Document # SRAM124 REV C
Page 14 of 14
相关型号:
P4C1024-35C6MB
Standard SRAM, 128KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32
PYRAMID
P4C1024-35L32M
Standard SRAM, 128KX8, 35ns, CMOS, CQCC32, 0.450 X 0.550 INCH, HERMETIC SEALED, LCC-32
PYRAMID
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