P4C1049L-25CWMB [PYRAMID]
Standard SRAM, 512KX8, 25ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32;
| 型号： | P4C1049L-25CWMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 512KX8, 25ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32 CD 静态存储器 |
| 文件： | 总12页 (文件大小：878K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1049/P4C1049L
HIGH SPEED 512K x 8
STATIC CMOS RAM
FEaturES
Hꢀꢁh Speed (Eqꢂꢃꢄ aꢅꢅess ꢃꢆd cyꢅꢄe tꢀꢇes)
— 15/20/25 ꢆs (cꢈꢇꢇeꢉꢅꢀꢃꢄ)
— 20/25/35 ꢆs (iꢆdꢂsꢊꢉꢀꢃꢄ)
— 20/25/35/45/55/70 ꢆs (mꢀꢄꢀꢊꢃꢉy)
lꢈw Pꢈweꢉ
thꢉee-Sꢊꢃꢊe oꢂꢊpꢂꢊs
Fꢂꢄꢄy ttl cꢈꢇpꢃꢊꢀbꢄe iꢆpꢂꢊs ꢃꢆd oꢂꢊpꢂꢊs
advꢃꢆꢅed cmoS teꢅhꢆꢈꢄꢈꢁy
aꢂꢊꢈꢇꢃꢊꢀꢅ Pꢈweꢉ Dꢈwꢆ
Pꢃꢅꢋꢃꢁes
Sꢀꢆꢁꢄe 5V±10% Pꢈweꢉ Sꢂppꢄy
Eꢃsy meꢇꢈꢉy Expꢃꢆsꢀꢈꢆ usꢀꢆꢁ CE ꢃꢆd OE iꢆpꢂꢊs
cꢈꢇꢇꢈꢆ Dꢃꢊꢃ i/o
—36-Pꢀꢆ ceꢉꢃꢇꢀꢅ DiP (600 ꢇꢀꢄ)
—36-Pꢀꢆ SoJ (400 ꢇꢀꢄ)
—36-Pꢀꢆ FlatPack
—36-Pꢀꢆ lcc (452 ꢇꢀꢄ x 920 ꢇꢀꢄ)
DEScriPtion
The P4C1049 is a 4 Megabit high-speed CMOS static RAM
organized as 512Kx8. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle times.
Inputs are fully TTL-compatible. The RAM operates from
a single 5V±10% tolerance power supply.
The P4C1049 device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pinsA0 toA18. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Access times as fast as 15 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1049
is a member of a family of PACE RAM™ products offering
fast access times.
Functional Block Diagram
Pin conFigurationS
LCC (L11)
SOLDER-SEAL FLAT-
PACK (FS-4),
SOJ (J9, CJ2)
DIP PIꢀ-OꢁT IꢀSIDE DATASHEET
Document # SRAM128 REV C
Revised August 2011
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
maꢌimum ratingS(1)
rEcommEnDED oPErating conDitionS
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
Vꢃꢄꢂe
uꢆꢀꢊ
gꢉꢃde(2)
aꢇbꢀeꢆꢊ teꢇp
0°C to 70°C
gnD
0V
Vcc
Power Supply Pin with
VCC
Commercial
Industrial
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
-0.5 to +7
V
Respect to GꢀD
-40°C to +85°C
-55°C to +125°C
0V
Terminal Voltage with
VTERM Respect to GꢀD (up to
7.0V)
-0.5 to VCC + 0.5
V
0V
caPacitancES(4)
TA
Operating Temperature
-55 to +125
-55 to +125
-65 to +150
1.0
°C
°C
°C
W
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
TBIAS Temperature ꢁnder Bias
TSTG Storage Temperature
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
cꢈꢆdꢀꢊꢀꢈꢆs typ uꢆꢀꢊ
PT
Power Dissipation
CIꢀ
Input Capacitance
VIꢀ=0V
8
8
pF
pF
IOꢁT DC Output Current
50
mA
COꢁT
Output Capacitance
VOꢁT=0V
Dc ElEctrical cHaractEriSticS
(Over Recommended Operating Temperature & Supply Voltage)(2)
P4c1049
P4c1049l
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
tesꢊ cꢈꢆdꢀꢊꢀꢈꢆs
uꢆꢀꢊ
mꢀꢆ
2.2
mꢃx
mꢀꢆ
2.2
mꢃx
VIH Input High Voltage
VCC + 0.3
0.8
VCC + 0.3
0.8
V
V
V
V
VIL Input Low Voltage
-0.3(3)
-0.3(3)
VHC CMOS Input High Voltage
VLC CMOS Input Low Voltage
VCC - 0.2 VCC + 0.3 VCC - 0.2 VCC + 0.3
-0.3(3)
0.2
0.4
-0.3(3)
0.2
0.4
Output Low Voltage (TTL
Load)
VOL
IOL = +8 mA, VCC = Min
IOH = -4 mA, VCC = Min
V
V
Output High Voltage (TTL
Load)
VOH
2.4
-10
-5
2.4
-5
MIL
IꢀD/COM
MIL
+10
+5
+5
ꢀ/A
+5
VCC = Max,
VIꢀ = GꢀD to VCC
ILI
Input Leakage Current
µA
µA
ꢀ/A
-5
-10
-5
+10
+5
VCC = Max, CE = VIH,
VOꢁT = GꢀD to VCC
ILO Output Leakage Current
IꢀD/COM
MIL
ꢀ/A
—
ꢀ/A
40
—
45
CE ≥ VIH, VCC = Max, f = Max,
Standby Power Supply
ISB
mA
mA
Current (TTL Input Levels)
Outputs Open
IꢀD/COM
MIL
—
40
—
ꢀ/A
10
CE ≥ VHC, VCC = Max, f = 0,
Outputs Open
—
15
—
Standby Power Supply
ISB1 Current (CMOS Input
Levels)
IꢀD/COM
—
10
—
ꢀ/A
VIꢀ ≤ VLC or VIꢀ ≥ VHC
ꢀ/A = ꢀot applicable
Document # SRAM128 REV C
Page 2
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Data rEtEntion cHaractEriSticS (P4c1049l mꢀꢄꢀꢊꢃꢉy teꢇpeꢉꢃꢊꢂꢉe oꢆꢄy)
typ* Vcc
2.0V
=
mꢃx Vcc
2.0V
=
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
tesꢊ cꢈꢆdꢀꢊꢀꢈꢆs
mꢀꢆ
uꢆꢀꢊ
VDR VCC for Data Retention
ICCDR Data Retention Current
3.0
V
2
3
mA
ns
CE ≥ VCC -0.2V,
VIꢀ ≥ VCC -0.2V
or VIꢀ ≤ 0.2V
tCDR Chip Deselect to Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
ns
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
Data rEtEntion WaVEForm
PoWEr DiSSiPation cHaractEriSticS VS. SPEED
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
teꢇpeꢉꢃꢊꢂꢉe rꢃꢆꢁe
Commercial
Industrial
-15
220
ꢀ/A
ꢀ/A
-20
185
190
200
-25
180
185
195
-35
ꢀ/A
175
185
-45
ꢀ/A
ꢀ/A
175
-55
ꢀ/A
ꢀ/A
170
-70
ꢀ/A
ꢀ/A
165
uꢆꢀꢊ
mA
mA
mA
ICC
Dynamic Operating Current*
Military
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
Document # SRAM128 REV C
Page 3
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
ac ElEctrical cHaractEriSticS—rEaD cYclE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
-45
-55
-70
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
uꢆꢀꢊ
mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx
tRC Read Cycle Time
15
20
25
35
45
55
70
ns
ns
tAA Address Access Time
15
15
20
20
25
25
35
35
45
45
55
55
70
70
Chip Enable Access
Time
tAC
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Hold from Ad-
dress Change
tOH
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Chip Enable to Output in
Low Z
tLZ
Chip Disable to Output in
High Z
tHZ
8
7
9
9
11
10
15
15
20
20
25
25
30
30
Output Enable Low to
Data Valid
tOE
Output Enable Low to
Low Z
tOLZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Output Enable High to
High Z
tOHZ
7
9
10
25
15
35
20
45
25
55
30
70
Chip Enable to Power ꢁp
Time
tPꢁ
Chip Disable to Power
Down Time
tPD
15
20
timing WaVEForm oF rEaD cYclE no. 1 (OE controllED)(5)
timing WaVEForm oF rEaD cYclE no. 2 (aDDrESS controllED)(5,6)
Document # SRAM128 REV C
Page 4
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
timing WaVEForm oF rEaD cYclE no. 3 (CEcontrollED) (5, 7)
ac cHaractEriSticS—WritE cYclE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
-45
-55
-70
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
uꢆꢀꢊ
mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx mꢀꢆ mꢃx
tWC
tCW
tAW
tAS
Write Cycle Time
15
12
20
14
14
0
25
18
16
0
35
22
20
0
45
30
25
0
55
35
35
0
70
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Time to End of
Write
Address Valid to End of Write 12
Address Setup Time
Write Pulse Width
0
12
0
tWP
tAH
tDW
tDH
tWZ
tOW
14
0
16
0
22
0
25
0
30
0
35
0
Address Hold Time
Data Valid to End of Write
Data Hold Time
9
11
0
13
0
15
0
20
0
25
0
30
0
0
Write Enable to Output in
High Z
8
10
11
15
18
25
30
Output Active from End of
Write
3
3
3
5
5
5
5
nꢈꢊes:
1. Stresses greater than those listed under MAꢂIMꢁM RATIꢀGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢂIMꢁM rating conditions for extended
periods may affect reliability.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change,withloadingasspecifiedinFigure1. Thisparameterissampled
and not 100% tested.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
3. Transient inputs with VIL and IIL not more negative than –2.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
Document # SRAM128 REV C
Page 5
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
timing WaVEForm oF WritE cYclE no. 1 (WE controllED)(10,11)
timing WaVEForm oF WritE cYclE no. 2 (CE controllED)(10)
ac tESt conDitionS
Input Pulse Levels
trutH taBlE
GꢀD to 3.0V
mꢈde
CE
OE
ꢂ
WE
ꢂ
i/o
Pꢈweꢉ
Standby
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
Standby
DOꢁT Disabled
Read
H
L
L
L
High Z
High Z
DOꢁT
1.5V
H
L
H
1.5V
H
Active
See Figures 1 and 2
Write
ꢂ
L
High Z
Active
ꢀotes:
10. CE and WE must be LOW for WRITE cycle.
13. Write Cycle Time is measured from the last valid address to the first
11. OE is LOW for this WRITE cycle to show tWZ and tOW
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
.
transitioning address.
Document # SRAM128 REV C
Page 6
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Fꢀꢁꢂꢉe 1. oꢂꢊpꢂꢊ lꢈꢃd
Fꢀꢁꢂꢉe 2. theveꢆꢀꢆ Eqꢂꢀvꢃꢄeꢆꢊ
* including scope and test fixture.
nꢈꢊe:
Because of the ultra-high speed of the P4C1049/L, care must be taken
whentestingthisdevice;aninadequatesetupcancauseanormalfunction-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOꢁT to match 166Ω (Thevenin Resistance).
orDEring inFormation
Document # SRAM128 REV C
Page 7
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
32-Pin cEramic DiP Pin conFiguration
32-Pin DIP (C10)
Document # SRAM128 REV C
Page 8
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
SiDEBraZED Dual in-linE PackagE
Pkg #
c10
# Pins
32 (600 mil)
Symbol
mꢀꢆ
mꢃx
A
b
-
0.225
0.014 0.026
0.045 0.065
0.008 0.018
b2
C
D
-
1.680
E
0.510 0.620
0.600 BSC
eA
e
0.100 BSC
L
0.125 0.200
0.015 0.070
Q
S1
S2
0.005
0.005
-
-
SolDEr SEal FlatPack
Pkg #
FS-4
# Pins
36
Symbol
mꢀꢆ
mꢃx
A
b
0.089 0.125
0.015 0.019
0.003 0.007
0.910 0.930
0.505 0.515
c
D
E
E1
E2
E3
e
-
0.530
0.385 0.395
0.055 0.065
0.050 BSC
L
0.300 0.350
0.015 0.038
Q
S
-
-
0.045
0.002
M
ꢀ
36
Document # SRAM128 REV C
Page 9
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
SoJ Small outlinE ic PackagE
Pkg #
J9
# Pins
36
Symbol
mꢀꢆ
0.130 0.145
0.082
mꢃx
A
A1
b
-
0.015 0.020
0.007 0.013
0.920 0.930
0.050 BSC
C
D
e
E
0.435 0.445
0.395 0.405
0.370 BSC
E1
E2
Q
0.045 0.055
cEramic SoJ Small outlinE ic PackagE
Pkg #
# Pins
Symbol
A
cJ2
36
mꢀꢆ
mꢃx
0.120 0.165
0.030R TYP
0.020 REF
B1
B2
B3
0.025 0.045
0.816 0.838
0.419 0.431
0.360 0.380
0.050 BSC
D
E
E2
e
E1
0.430 0.454
Document # SRAM128 REV C
Page 10
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
rEctangular lEaDlESS cHiP carriEr
Pkg #
l11
# Pins
36
Symbol
mꢀꢆ
mꢃx
A
A1
B
0.080 0.100
0.054 0.066
0.022 0.028
0.910 0.930
0.840 0.860
0.445 0.460
.050 BSC
D
D1
E
e
L
.100 TYP
L2
P
0.115 0.135
-
0.006
R
.009 TYP
Document # SRAM128 REV C
Page 11
P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
rEViSionS
DocumEnt numBEr SRAM 128
DocumEnt titlE
P4C1049/P4C1049L - HIGH SPEED 512K ꢂ 8 STATIC CMOS RAM
rEV iSSuE DatE
originator DEScriPtion oF cHangE
OR
A
Oct-2005
Jan-2008
Mar-2009
Aug-2011
JDB
JDB
JDB
JDB
ꢀew Data Sheet
Added CJ2 Ceramic SOJ Package
Added C10 Ceramic DIP Package
Corrected typo in package list
B
C
Document # SRAM128 REV C
Page 12
相关型号：
P4C1049L-25L36M
Standard SRAM, 512KX8, 25ns, CMOS, CDSO36, 0.452 X 0.920 INCH, CERAMIC, LCC-36
PYRAMID
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