P4C1256-25PMLF [PYRAMID]
HIGH SPEED 32K x 8 STATIC CMOS RAM; 高速32K x 8静态CMOS RAM
| 型号： | P4C1256-25PMLF |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | HIGH SPEED 32K x 8 STATIC CMOS RAM |
| 文件： | 总17页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
—28-Pin 300 mil DIP, SOJ, TSOP
—28-Pin 300 mil Ceramic DIP
—28-Pin 600 mil Ceramic DIP
—28-Pin CERPACK
—28-Pin SOP
—28-Pin LCC (350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
Common Data I/O
Three-State Outputs
DESCRIPTION
The P4C1256 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A0 to A14. Reading
is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay
in the HIGH Z state when either CE or OE is HIGH or
WE is LOW.
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
Package options for the P4C1256 include 28-pin 300
mil DIP, SOJ and TSOP packages. For military tempera-
ture range, Ceramic DIP and LCC packages are avail-
able.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4) SIMILAR
See end of datasheet for LCC and TSOP
pin configurations.
Document # SRAM119 REV G
Revised June 2007
1
P4C1256
MAXIMUMRATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TBIAS
TemperatureUnder
Bias
–55 to +125
°C
TerminalVoltagewith
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
TSTG
PT
StorageTemperature
PowerDissipation
DCOutputCurrent
–65 to +150
°C
W
VTERM
TA
V
1.0
50
IOUT
mA
OperatingTemperature
–55 to +125 °C
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
VCC
Grade(2)
GND
Parameter
Typ.
Symbol
Conditions
Unit
Temperature
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
Input Capacitance
Output Capacitance
VIN = 0V
8
pF
pF
0V
0V
0V
Military
Industrial
Commercial
VOUT = 0V
COUT
10
DC ELECTRICAL CHARACTERISTICS
Overrecommendedoperatingtemperatureandsupplyvoltage(2)
P4C1256
P4C1256L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
VIH
2.2
VCC +0.5
Input High Voltage
VCC +0.5
2.2
V
V
V
–0.5(3)
–0.5(3)
0.8
VIL
VHC
VLC
Input Low Voltage
0.8
VCC –0.2
VCC +0.5
VCC –0.2
VCC +0.5
CMOS Input High Voltage
CMOS Input Low Voltage
–0.5(3)
0.2
0.4
–0.5(3)
0.2
0.4
V
V
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
VCC = Max.
2.4
2.4
V
–5
+5
µA
Mil. –10
+10
+5
ILI
Input Leakage Current
Output Leakage Current
n/a
n/a
VIN = GND to VCC
Ind./Com’l.
–5
µA
–5
+5
–10
–5
+10
+5
VCC = Max.,
Mil.
n/a
n/a
ILO
CE = VIH,
Ind./Com’l.
VOUT = GND to VCC
___
___
___
___
30
mA
CE ≥ VIH
Mil.
45
30
n/a
Standby Power Supply
Current (TTL Input Levels)
VCC= Max,
Ind./Com’l.
ISB
f = Max., Outputs Open
___
___
___
___
10
20
10
mA
CE ≥ VHC
Mil.
Ind./Com’l.
n/a
VCC= Max,
Standby Power Supply
Current
(CMOS Input Levels)
ISB1
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
N/A = Not Applicable
Document # SRAM119 REV G
Page 2 of 17
P4C1256
DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only)
Typ.*
VCC
2.0V
Max
VCC
2.0V
Symbol
Parameter
TestConditons
Min
Unit
=
3.0V
=
3.0V
V
VDR
VCC for Data Retention
DataRetentionCurrent
2.0
ICCDR
tCDR
10
15
100
200
µA
ns
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V
or VIN ≤ 0.2V
Chip Deselect to
DataRetentionTime
0
§
†
tR
OperationRecoveryTime
tRC
ns
*TA = +25°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
–15 –20 –25 –35 –45 –55 –70
–12
mA
160 155 150 N/A N/A mA
N/A N/A 170 165 160 155 150 150 mA
Commercial
150 145 N/A N/A N/A
170 160 155
ICC
Dynamic Operating Current*
N/A
Industrial
Military
170 165
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
Document # SRAM119 REV G
Page 3 of 17
P4C1256
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
-55
-70
Sym.
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC
tAA
20
25
35
55
ReadCycleTime 12
15
45
70
ns
45
45
Address Access
Time
12
12
15
15
20
20
25
25
35
35
55
55
70 ns
tAC
70 ns
ChipEnable
Access Time
OutputHoldfrom
2
AddressChange
ns
ns
2
2
2
2
3
3
3
3
3
3
3
3
3
3
tOH
tLZ
tHZ
tOE
Chip Enable to
Output in Low Z
2
30 ns
30 ns
Chip Disable to
Output in High Z
5
5
8
7
9
9
11
10
15
15
20
20
25
25
OutputEnable
Low to Data
Valid
tOLZ
0
0
0
0
0
0
ns
OutputEnable
Low to Low Z
0
0
0
0
0
0
0
0
0
0
tOHZ
30 ns
OutputEnable
High to High Z
5
7
9
11
20
15
20
20
25
25
30
Chip Enable to
PowerUpTime
tPU
tPD
ns
Chip Disable to
PowerDown
Time
12
15
20
35 ns
Document # SRAM119 REV G
Page 4 of 17
P4C1256
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESSmustbevalidpriorto,orcoincidentwithCE transitionLOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM119 REV G
Page 5 of 17
P4C1256
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
-55
-70
Parameter
Unit
Sym.
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC
tCW
20
15
25
18
35
22
55
35
Write Cycle Time 12
15
10
45
30
70
40
ns
ns
ChipEnable
Time to End of
Write
9
tAW
tAS
Address Valid to
End of Write
10
15
20
25
35
40
45
ns
9
0
9
0
8
AddressSet-up
Time
0
11
0
0
15
0
0
22
0
0
25
0
0
30
0
0
35
0
ns
ns
ns
ns
0
18
0
tWP
tAH
tDW
Write Pulse
Width
AddressHold
Time
Data Valid to
End of Write
11
13
15
25
9
20
30
tDH
tWZ
0
3
0
0
3
DateHoldTime
0
3
0
5
0
0
0
0
ns
Write Enable to
Output in High Z
7
8
10
11
15
18
25
30 ns
tOW
OutputActive
3
5
0
ns
from End of Write
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Document # SRAM119 REV G
Page 6 of 17
P4C1256
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
Notes:
10. CE and WE must be LOW for WRITE cycle.
in a high impedance state
11. OE is LOW for this WRITE cycle to show tWZ and tOW
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
.
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM119 REV G
Page 7 of 17
P4C1256
AC TEST CONDITIONS
TRUTH TABLE
InputPulseLevels
GND to 3.0V
Mode
CE O E W E
I/O
Power
Standby
Standby
Input Rise and Fall Times
InputTimingReferenceLevel
OutputTimingReferenceLevel
OutputLoad
3ns
1.5V
Standby
Standby
X
X
X
X
High Z
High Z
H
X
High Z
Active
1.5V
DOUT Disabled
L
H
H
See Figures 1 and 2
L
L
H
L
DOUT
Active
Active
L
Read
Write
X
High Z
Figure 1. Output Load
Figure2. TheveninEquivalent
* including scope and test fixture.
Note:
Becauseoftheultra-highspeedoftheP4C1256,caremustbetakenwhen
testingthisdevice;aninadequatesetupcancauseanormalfunctioningpart
to be rejected as faulty. Long high-inductance leads that cause supply
bouncemustbeavoidedbybringingtheVCC andgroundplanesdirectlyup
tothecontactorfingers. A0.01µFhighfrequencycapacitorisalsorequired
between VCC and ground. To avoid signal reflections, proper termination
mustbeused;forexample, a50Ω testenvironmentshouldbeterminated
into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input,
and a 116Ω resistor must be used in series with DOUT to match 166Ω
(Thevenin Resistance).
Document # SRAM119 REV G
Page 8 of 17
P4C1256
ORDERING INFORMATION
SELECTION GUIDE
The P4C1256 is available in the following temperature, speed and package options. The P4C1256L is available only
overthemilitarytemperaturerange. **
Speed
Temperature
Range
Package
12
15
20
25
35
45
55
70
Commercial
Plastic DIP
-12PC
-12JC
-15PC
-15JC
-20PC
-20JC
-25PC
-25JC
-35PC
-35JC
N/A
N/A
N/A
N/A
N/A
N/A
Plastic SOJ
Plastic TSOP
-12TC
-12SC
-15TC
-15SC
-20TC
-20SC
-25TC
-25SC
-35TC
-35SC
N/A
N/A
N/A
N/A
N/A
N/A
Plastic SOP (S11-1)
Plastic SOP (S11-3)
Plastic DIP
-12SSC
N/A
-15SSC
-15PI
-20SSC
-20PI
-25SSC
-25PI
-35SSC
-35PI
N/A
N/A
N/A
N/A
N/A
Industrial
-45PI
Plastic SOJ
N/A
-15JI
-20JI
-25JI
-35JI
-45JI
N/A
N/A
Plastic TSOP
N/A
N/A
N/A
-15TI
-15SI
-20TI
-20SI
-25TI
-25SI
-35TI
-35SI
-45TI
-45SI
N/A
N/A
N/A
N/A
N/A
N/A
Plastic SOP (S11-1)
Plastic SOP (S11-3)
-15SSI
-20SSI
-25SSI
-35SSI
-45SSI
* Military temperature range with MIL-STD-883, Class B processing.
** For RoHS compliant plastic products, the suffix "LF" (Lead Free) should be added to the part number.
N/A = Not Available
Document # SRAM119 REV G
Page 9 of 17
P4C1256
SELECTION GUIDE (CONTINUED)
Speed
35
Temperature
Package
Range
12
15
20
25
45
55
70
Military
Temperature
Side Brazed DIP (300 mil)
Side Brazed DIP (600 mil)
Ceramic DIP
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-20CM
-25CM
-35CM
-35CWM
-35DM
-45CM
-55CM
-70CM
-20CWM
-20DM
-25CWM
-25DM
-45CWM
-45DM
-55CWM
-55DM
-70CWM
-70DM
CERPACK
-20FM
-25FM
-35FM
-45FM
-55FM
-70FM
LCC (28-Pin)
-20L28M
-20L32M
-20CMB
-25L28M
-25L32M
-25CMB
-35L28M
-35L32M
-35CMB
-45L28M
-45L32M
-45CMB
-55L28M
-55L32M
-55CMB
-70L28M
-70L32M
-70CMB
LCC (32-Pin)
Military
Processed*
Side Brazed DIP (300 mil)
Side Brazed DIP (600 mil)
Ceramic DIP
-20CWMB -25CWMB -35CWMB -45CWMB -55CWMB -70CWMB
-20DMB
-20FMB
-25DMB
-25FMB
-35DMB
-35FMB
-45DMB
-45FMB
-55DMB
-55FMB
-70DMB
-70FMB
CERPACK
LCC (28-Pin)
-20L28MB -25L28MB -35L28MB -45L28MB -55L28MB -70L28MB
-20L32MB -25L32MB -35L32MB -45L32MB -55L32MB -70L32MB
LCC (32-Pin)
LCC PIN CONFIGURATIONS
28 LCC (L5)
32 LCC (L6)
TSOP(T1)
Document # SRAM119 REV G
Page 10 of 17
P4C1256
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (300 Mils)
Pkg #
C5
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (600 Mils)
Pkg #
C5-1
# Pins
28 (600 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.232
0.026
0.065
0.018
1.490
0.610
0.500
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.060
-
-
Document # SRAM119 REV G
Page 11 of 17
P4C1256
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D5-2
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
CERPACK CERAMIC FLAT PACKAGE
Pkg #
F4
# Pins
28
Symbol
Min
0.060
0.015
0.004
-
Max
A
b
c
D
E
e
0.090
0.022
0.009
0.730
0.380
0.330
0.050 BSC
k
L
Q
S
S1
0.005
0.018
0.370
0.045
0.085
-
0.250
0.026
-
0.005
Document # SRAM119 REV G
Page 12 of 17
P4C1256
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
0.020
0.011
0.730
A
A1
b
C
D
0.120
0.078
0.014
0.007
0.700
e
E
E1
E2
Q
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
0.025
-
RECTANGULAR LEADLESS CHIP CARRIER (28 Pins)
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
5
9
Document # SRAM119 REV G
Page 13 of 17
P4C1256
RECTANGULAR LEADLESS CHIP CARRIER (32 Pins)
Pkg #
L6
# Pins
Symbol
A
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
7
9
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
-
Max
0.210
-
0.023
0.070
0.014
1.400
0.300
0.380
A
A1
b
b2
C
D
E1
E
0.014
0.045
0.008
1.345
0.270
0.300
e
0.100 BSC
eB
L
α
-
0.430
0.150
15°
0.115
0°
Document # SRAM119 REV G
Page 14 of 17
P4C1256
TSOP THIN SMALL OUTLINE PACKAGE (8 x 13.4 mm)
Pkg #
T1
# Pins
28
Symbol
Min
Max
A
A2
b
D
E
0.039
0.036
0.007
0.461
0.311
0.047
0.040
0.011
0.469
0.319
e
0.022 BSC
0.520 0.535
HD
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S11-1
# Pins
28 (300 Mil)
Symbol
Min
Max
A
A1
b2
C
D
e
0.093
0.004
0.013
0.009
0.696
0.104
0.012
0.020
0.012
0.712
0.050 BSC
E
H
h
L
α
0.291
0.394
0.010
0.016
0°
0.299
0.419
0.029
0.050
8°
Document # SRAM119 REV G
Page 15 of 17
P4C1256
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S11-3
# Pins
28 (300 Mil)
Symbol
Min
Max
A
A1
B
C
D
e
0.094
0.002
0.014
0.008
0.702
0.110
0.014
0.020
0.012
0.710
0.050 BSC
E
H
h
L
α
0.291
0.463
0.010
0.020
0°
0.300
0.477
0.029
0.042
8°
Document # SRAM119 REV G
Page 16 of 17
P4C1256
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM119
HIGH SPEED 32K x 8 STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
DATE
REV.
DESCRIPTIONOFCHANGE
OR
A
1997
RKK
NewDataSheet
Oct-05
Oct-05
JDB
JDB
Change logo to Pyramid
Added SOP Package
B
C
D
Apr-06
JDB
JDB
AddedLead-Freeorderinginformation.
May-06
AddedPDIPtoOrderingInformationdiagram
E
F
Jun-06
Aug-06
JDB
JDB
AddedCeramicDIPpackage
UpdatedSOJpackageinformation
G
Jun-07
JDB
CorrectedSOPpackageinformation
Document # SRAM119 REV G
Page 17 of 17
相关型号：
P4C1256-25SSMBLF
Standard SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-28
PYRAMID
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