P4C1256L70PCLF [PYRAMID]
LOW POWER 32K x 8 STATIC CMOS RAM; 低功耗32K x 8静态CMOS RAM
| 型号： | P4C1256L70PCLF |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | LOW POWER 32K x 8 STATIC CMOS RAM |
| 文件： | 总11页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 600 mil DIP
—28-Pin 300 mil CERDIP
—28-Pin 300 mil Narrow Body SOP
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
DESCRIPTION
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
locations are specified on address pinsA0 toA14. Read-
ing is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay in
the HIGH Z state when either CE or OE is HIGH or WE
is LOW.
Access times of 55 ns and 70 ns are available. CMOS
is utilized to reduce power consumption to a low level.
Package options for the P4C1256L include 28-pin 600
mil DIP, 28-pin 300 mil CERDIP, and 28-pin 300 mil Nar-
row Body SOP packages.
The P4C1256L device provides asynchronous opera-
tion with matching access and cycle times. Memory
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (P6, D5-2), SOP (S11-3)
TOP VIEW
Document # SRAM121 REV E
Revised June 2007
1
P4C1256L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Supply Voltage
4.5V ≤ VCC ≤ 5.5V
4.5 ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
MAXIMUM RATINGS(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
VCC
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Min
-0.5
-0.5
Max
7.0
Unit
V
VTERM
TA
VCC + 0.5
V
-55
-65
125
150
°C
°C
STG
IOUT
ILAT
Output Current into Low Outputs
Latch-up Current
25
mA
mA
>200
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Max
Parameter
Unit
Min
Symbol
Test Conditions
Output High Voltage
(I/O0 - I/O7)
VOH
V
IOH = –1mA, VCC = 4.5V
2.4
Output Low Voltage
(I/O0 - I/O7)
VOL
IOL = 2.1mA
0.4
V
2.2
V
CC + 0.3
V
V
Input High Voltage
Input Low Voltage
VIH
VIL
-0.5(3)
0.8
GND ≤ VIN ≤ VCC
Ind'l.
-5
-2
+5
+2
µA
Input Leakage Current
Output Leakage Current
ILI
Com'l.
GND ≤ VOUT ≤ VCC
CE ≥ VIH
Ind'l.
Com'l.
-5
-2
+5
+2
µA
mA
µA
ILO
VCC Current
TTL Standby Current
(TTL Input Levels)
VCC = 5.5V, IOUT = 0 mA
3
ISB
CE = VIH
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 5.5V, IOUT = 0 mA
100
ISB1
CE ≥ VCC -0.2V
Document # SRAM121 REV E
Page 2 of 11
P4C1256L
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, F = 1.0 MHz)
Unit
Symbol
Parameter
Test Conditions
VIN = 0V
Max
CIN
Input Capacitance
7
pF
VOUT = 0V
9
COUT
Output Capacitance
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
*
**
Temperature
Parameter
Unit
Symbol
-55
15
-55
70
-70
Range
-70
15
Commercial
Industrial
70
85
mA
mA
ICC
Dynamic Operating Current
85
25
25
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-70
-55
Parameter
Unit
Symbol
Max
Min
Max
Min
tRC
Read Cycle Time
Address Access Time
55
70
ns
ns
55
55
tAA
tAC
tOH
70
70
Chip Enable Access
Time
ns
Output Hold from
Address Change
5
5
5
5
ns
ns
Chip Enable to
Output in Low Z
tLZ
Chip Disable to
Output in High Z
tHZ
20
30
25
35
ns
Output Enable Low
to Data Valid
tOE
tOLZ
tOHZ
tPU
ns
ns
Output Enable Low to
Low Z
5
0
5
0
Output Enable High
to High Z
25
70
20
55
ns
ns
Chip Enable to Power
Up Time
tPD
Chip Disable to
Power Down Time
ns
Document # SRAM121 REV E
Page 3 of 11
P4C1256L
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
Document # SRAM121 REV E
Page 4 of 11
P4C1256L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-55
-70
Symbol
tWC
Parameter
Unit
ns
Min
Max
Min
Max
Write Cycle Time
55
70
Chip Enable Time
to End of Write
tCW
50
50
0
60
60
0
ns
Address Valid to
End of Write
tAW
tAS
ns
ns
ns
ns
Address Set-up
Time
tWP
tAH
tDW
Write Pulse Width
40
0
50
0
Address Hold
Time
Data Valid to End
of Write
25
0
30
0
ns
ns
Data Hold Time
tDH
tWZ
Write Enable to
Output in High Z
25
30
ns
ns
Output Active from
End of Write
tOW
5
5
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM121 REV E
Page 5 of 11
P4C1256L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
Mode
CE OE WE I/O
Power
High Z Standby
High Z Standby
Input Rise and Fall Times
Standby
Standby
X
X
X
X
H
X
Input Timing Reference Level
1.5V
1.5V
Output Timing Reference Level
Output Load
High Z Active
DOUT Disabled
L
H
H
See Figures 1 and 2
L
L
H
L
DOUT
Active
L
Read
Write
X
High Z Active
Figure 1. Output Load
Figure 2. Thievenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P4C1256L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Document # SRAM121 REV E
Page 6 of 11
P4C1256L
DATA RETENTION CHARACTERISTICS
Typ.*
VCC
2.0V
Max
VCC
2.0V
Symbol
Parameter
Test Conditons
Min
Unit
=
3.0V
=
3.0V
V
VDR
VCC for Data Retention
2.0
ICCDR
tCDR
Data Retention Current
10
15
600
900
µA
ns
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V
or VIN ≤ 0.2V
Chip Deselect to
Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
ns
*TA = +25°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM121 REV E
Page 7 of 11
P4C1256L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1256L is available in the following temperature, speed and package options.
Speed (ns)
Temperature
Range
Package
55
70
Commercial
Plastic DIP, 600 mil
Ceramic DIP (CERDIP)
Plastic SOJ, 300 mil
Plastic DIP, 600 mil
Ceramic DIP (CERDIP)
Plastic SOJ, 300 mil
-55PC
-55DC
-55SNC
-55PI
-70PC
-70DC
-70SNC
-70PI
Industrial
-55DI
-70DI
-55SNI
-70SNI
Document # SRAM121 REV E
Page 8 of 11
P4C1256L
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D5-2
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P6
# Pins
28 (600 mil)
Symbol
Min
Max
A
A1
b
b2
C
D
E1
E
0.090
0.000
0.014
0.015
0.008
1.380
0.485
0.600
0.200
0.070
0.020
0.065
0.012
1.480
0.550
0.625
e
eB
L
α
0.100 BSC
0.600 TYP
0.100 0.200
0° 15°
Document # SRAM121 REV E
Page 9 of 11
P4C1256L
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S11-3
# Pins
28 (300 Mil)
Symbol
Min
Max
A
A1
B
C
D
e
0.094
0.002
0.014
0.008
0.702
0.110
0.014
0.020
0.012
0.710
0.050 BSC
E
H
h
L
α
0.291
0.463
0.010
0.020
0°
0.300
0.477
0.029
0.042
8°
Document # SRAM121 REV E
Page 10 of 11
P4C1256L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM121
P4C1256L LOW POWER 32K x 8 STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
OR
1997
DAB
New Data Sheet
A
B
Oct-05
Jun-06
JDB
JDB
Change logo to Pyramid
Added 28-pin ceramic DIP
C
D
Aug-06
Mar-07
JDB
JDB
Added Lead Free Designation
Corrected Narrow SOP width in Ordering Information and Selection
Guide
E
Jun-07
JDB
Corrected Narrow SOP package dimensions
Document # SRAM121 REV E
Page 11 of 11
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