P4C1281-25LC [PYRAMID]
ULTRA HIGH SPEED 64K X 4 cmos STATIC RAMS;
| 型号： | P4C1281-25LC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 64K X 4 cmos STATIC RAMS 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1281/P4C1282
ULTRA HIGH SPEED 64K X 4
cmoS STATIc RAmS
FEATURES
Full CMOS, 6T Cell
Separate Inputs and Outputs
ꢀ High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Industrial)
– P4C1281 Input Data at Outputs during Write
– P4C1282 Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
– 20/25/35/45 ns (Military)
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
Low Power Operation
5V ± 10% Power Supply
DESCRIPTIOꢀ
The P4C1281 and P4C1282 are 262,144-bit (64Kx4) ultra
high-speed static RAMs similar to the P4C1258, but with
separate data I/O pins. The P4C1281 features a transpar-
ent write operation; the outputs of the P4C1282 are in high
impedanceduringthewritecycle. TheRAMsoperatefrom
a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C1281 and P4C1282 are available in 28-pin 300
mil DIP and SOJ, and a 28-pin 350x550 mil LCC providing
excellent board level densities.
FUꢀCTIOꢀAL BLOCk DIAꢁRAM
PIꢀ COꢀFIꢁURATIOꢀS
DIP (P5, C5, D5-2), SOJ (J5)
LCC (L5)
Document # SRAM136 REV OR
Revised July 2009
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
MAꢂIMUM RATIꢀꢁS(1)
RECOMMEꢀDED OPERATIꢀꢁ COꢀDITIOꢀS
Sym Parameter
Value
Unit
ꢁrade(2)
Ambient Temp
0°C to 70°C
ꢁꢀD
0V
VCC
Power Supply Pin with
VCC
Commercial
Industrial
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
-0.5 to +7
V
Respect to GND
-40°C to +85°C
-55°C to +125°C
0V
Terminal Voltage with
VTERM Respect to GND (up to
7.0V)
-0.5 to VCC + 0.5
V
0V
CAPACITAꢀCES(4)
TA
Operating Temperature
-55 to +125
-55 to +125
-65 to +150
1.0
°C
°C
°C
W
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
TBIAS Temperature Under Bias
TSTG Storage Temperature
Sym Parameter
Conditions Typ Unit
PT
Power Dissipation
CIN
Input Capacitance
Output Capacitance
VIN=0V
8
pF
pF
IOUT DC Output Current
50
mA
COUT
VOUT=0V
10
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
P4C1281/1282
Sym Parameter
Test Conditions
Unit
Min
2.2
Max
VCC + 0.5
0.8
VIH Input High Voltage
V
V
V
V
V
V
V
VIL Input Low Voltage
-0.5(3)
VHC CMOS Input High Voltage
VLC CMOS Input Low Voltage
VCD Input Clamp Diode Voltage
VOL Output Low Voltage (TTL Load)
VOH Output High Voltage (TTL Load)
VCC - 0.2 VCC + 0.5
-0.5(3)
0.2
-1.2
0.4
VCC = Min, IIN = -18 mA
IOL = +8 mA, VCC = Min
IOH = -4 mA, VCC = Min
2.4
-10
MIL
IND/COM
MIL
+10
+5
VCC = Max,
VIN = GND to VCC
ILI
Input Leakage Current
µA
µA
-5
-10
-5
+10
+5
VCC = Max, CE = VIH,
VOUT = GND to VCC
ILO Output Leakage Current
IND/COM
MIL
—
—
—
—
40
CE ≥ VIH, VCC = Max, f = Max,
Standby Power Supply Current
(TTL Input Levels)
ISB
mA
mA
Outputs Open
IND/COM
MIL
35
CE ≥ VHC, VCC = Max, f = 0,
Outputs Open
20
Standby Power Supply Current
(CMOS Input Levels)
ISB1
IND/COM
15
VIN ≤ VLC or VIN ≥ VHC
N/A = Not applicable
Document # SRAM136 REV OR
Page 2
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
POWER DISSIPATIOꢀ CHARACTERISTICS VS. SPEED
Sym Parameter
Temperature Range
Commercial
Industrial
-12
170
N/A
N/A
-15
160
170
N/A
-20
155
160
160
-25
150
155
155
-35
N/A
150
150
-45
N/A
N/A
145
Unit
mA
mA
mA
ICC
Dynamic Operating Current*
Military
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
Sym Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
tRC
tAA
tAC
tOH
tLZ
Read Cycle Time
12
15
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
12
12
15
15
20
20
25
25
35
35
45
45
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Chip Enable to Power Up Time
Chip Disable to Power Down
2
2
2
2
2
2
2
2
2
2
2
2
tHZ
tPU
tPD
7
8
10
20
10
25
15
25
15
30
0
0
0
0
0
0
12
15
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 1 (ADDRESS COꢀTROLLED) (5,6)
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 2 (CECOꢀTROLLED) (5,7,8)
Document # SRAM136 REV OR
Page 3
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
Sym Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time
12
8
13
10
10
0
15
15
15
0
20
20
20
0
30
30
25
0
40
35
35
0
ns
ns
ns
ns
ns
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Setup Time
8
0
tWP Write Pulse Width
9
10
15
20
25
35
Address Hold Time from End of
Write
tAH
0
0
0
0
0
0
ns
tDW Data Valid to End of Write
tDH Data Hold Time
6
0
7
0
10
0
13
0
15
0
20
0
ns
ns
ns
ns
tWZ Write Enable to Output in High Z
tOW Output Active from End of Write
6
7
8
10
10
15
2
2
2
2
2
2
Write Enable to Data-out Valid
(P4C1281)
tAWE
12
12
13
13
18
18
20
20
30
30
35
35
ns
ns
Data-in Valid to Data-out Valid
(P4C1281)
tADV
ꢀotes:
1. Stresses greater than those listed under MAꢀIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢀIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
9. Transition is measured ± 200 mV from steady state voltage prior to
change,withloadingasspecifiedinFigure1. Thisparameterissampled
and not 100% tested.
Document # SRAM136 REV OR
Page 4
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 1 (WE COꢀTROLLED) (10, 11, 12)
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 2 (CE COꢀTROLLED) (10, 11, 12)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM136 REV OR
Page 5
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
AC TEST COꢀDITIOꢀS
Input Pulse Levels
TRUTH TABLE
P4C1281 (P4C1282)
GND to 3.0V
Mode
Standby
Read
CE
WE
ꢀ
I/O
Power
Standby
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
H
L
L
High Z
DOUT
H
1.5V
Write
L
DIN (High Z)
Active
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
ꢀote:
Because of the ultra-high speed of the P4C1281 and P4C1282, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC
and ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signalreflections,properterminationmustbeused;forexample,a50Ωtest
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM136 REV OR
Page 6
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
ORDERIꢀꢁ IꢀFORMATIOꢀ
Document # SRAM136 REV OR
Page 7
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
SIDEBRAZED DUAL Iꢀ-LIꢀE PACkAꢁE
Pkg #
C5
# Pins
28 (300 mil)
Symbol
Min
-
Max
A
b
0.225
0.026
0.065
0.018
1.485
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.070
S1
S2
-
-
CERDIP DUAL Iꢀ-LIꢀE PACkAꢁE
Pkg #
D5-2
# Pins
28 (300 mil)
Symbol
Min
-
Max
0.225
0.026
0.065
0.018
1.485
0.310
A
b
0.014
0.045
0.008
-
b2
C
D
E
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM136 REV OR
Page 8
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
SOJ SMALL OUTLIꢀE IC PACkAꢁE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.120
0.078
0.014
0.007
0.700
0.020
0.011
0.730
C
D
e
0.050 BSC
E
0.292
0.335
0.262
0.025
0.300
0.347
0.272
-
E1
E2
Q
RECTAꢀꢁULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
0.045
0.075
L2
ND
NE
5
9
Document # SRAM136 REV OR
Page 9
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
PLASTIC DUAL Iꢀ-LIꢀE PACkAꢁE
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
Max
0.210
-
A
A1
b
-
0.014
0.045
0.008
1.345
0.270
0.300
0.023
0.070
0.014
1.400
0.300
0.380
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
Document # SRAM136 REV OR
Page 10
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
REVISIOꢀS
DOCUMEꢀT ꢀUMBER SRAM136
DOCUMEꢀT TITLE
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
REV ISSUE DATE
ORIꢁIꢀATOR DESCRIPTIOꢀ OF CHAꢀꢁE
JDB New Data Sheet
OR
July 10, 2009
Document # SRAM136 REV OR
Page 11
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