P4C1298-35JC [PYRAMID]
ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM; 超高速64K ×4的静态CMOS RAM
| 型号： | P4C1298-35JC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM |
| 文件： | 总11页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1298/P4C1298L
ULTRA HIGH SPEED 64K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
Data Retention with 2.0V Supply
Three-StateOutputs
High Speed (Equal Access and Cycle Times)
–15/20/25/35ns(Commercial/Industrial)
–15/20/25/35/45ns(Military)
TTL/CMOSCompatibleOutputs
Fully TTL Compatible Inputs
Low Power
Single 5V±10% Power Supply
StandardPinout(JEDECApproved)
– 28-Pin 300 mil DIP, SOJ
Output Enable & Chip Enable control functions
– 28-Pin 350x550 mil LCC
DESCRIPTION
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
TheP4C1298/Larea262,144-bitultrahighspeedstaticRAM
organizedas64Kx4.TheCMOSmemoryrequiresnoclock
orrefreshingandhasequalaccessandcycletimes. Inputs
and outputs are fully TTL-compatible. The RAM operates
fromasingle5V±10%tolerancepowersupply.Withbattery
backup,dataintegrityismaintainedforsupplyvoltagesdown
to 2.0V. Current drain is typically 10 µA from a 2.0V supply.
TheP4C1298is availableina28-pin300milDIPorSOJ,as
well as a 28-pin 350x500 mil LCC package, providing
excellentboardleveldensities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP(P5,C5)
SOJ (J5)
LCC (L5)
Document # SRAM135 REV OR
Revised April 2007
1
P4C1298/L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
VTERM
TA
V
1.0
50
IOUT
mA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
VCC = 5.0V, TA = 25°C, f = 1.0MHz
Grade(2)
VCC
GND
Symbol
Parameter
Conditions Typ. Unit
Temperature
-55°Cto+125°C
–40°C to +85°C
0°C to +70°C
Military
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
VIN = 0V
pF
pF
Input Capacitance
Output Capacitance
5
7
Industrial
COUT
VOUT = 0V
Commercial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C1298
P4C1298L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
Input High Voltage
2.2
VCC +0.5
2.2
VCC +0.5
V
V
V
V
V
VIH
VIL
–0.5(3)
0.8
–0.5(3)
0.8
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
VHC
VLC
VCD
–0.5(3)
0.2
–0.5(3)
0.2
VCC = Min., IIN = 18 mA
–1.2
–1.2
Output Low Voltage
(TTL Load)
VOL
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
0.4
0.4
V
V
Output High Voltage
(TTL Load)
2.4
–5
2.4
VOH
V
CC = Max.
Input Leakage Current
Output Leakage Current
µA
µA
ILI
+5
+5
–10
+10
+10
VIN = GND to VCC
VCC = Max., CE = VIH
–5
–10
ILO
VOUT = GND to VCC
___
___
___
___
CE ≥ VIH
Mil
40
20
20
mA
mA
Standby Power Supply
Current (TTL Input Levels)
ISB
VCC = Max ., f = Max., Outputs
Ind/Comm
N/A
Open
___
___
___
___
Standby Power Supply
Current
(CMOS Input Levels)
CE ≥ VHC
VCINC≤ VLC or VIN ≥ VHC
Mil
10
10
10
mA
mA
ISB1
V
= Max., f = 0, Outputs Open
N/A
Ind/Comm
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM135 REV OR
Page 2 of 11
P4C1298/L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
–15 –20 –25 –35
Unit
Range
mA
mA
mA
160 125 115 110
160 135 120 115
160 150 120 120
Commercial
ICC
Industrial
Military
Dynamic Operating Current*
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL
DATA RETENTION CHARACTERISTICS (P4C1298L ONLY)
Typ.*
VCC
2.0V
Max
VCC =
2.0V 3.0V
=
Symbol
Parameter
Test Conditions
Min
Unit
3.0V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
ICCDR
tCDR
10
15
1000 2000
µA
ns
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V or
VIN ≤ 0.2V
Chip Deselect to
Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
ns
*TA = +25°C
§tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM135 REV OR
Page 3 of 11
P4C1298/L
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-25
-35
-15
Max
-20
-45
Max
Sym.
Parameter
Unit
Min
Min Max Min Max
Min Max
Min
tRC
tAA
tAC
tOH
Read Cycle Time
25
20
35
35
ns
ns
15
45
15
15
45
45
Address Access Time
20
20
25
25
ns
ns
35
Chip Enable Access Time
3
3
3
3
3
3
3
3
3
3
OutputHoldfromAddressChange
ns
ns
tLZ
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
tHZ
8
8
15
20
30
15
15
10
10
tOE
ns
ns
25
tOLZ Output Enable Low to Low Z
0
0
0
0
0
0
0
0
0
tOHZ
9
9
15
25
20
20
45
ns
ns
ns
Output Enable High to High Z
tPU
tPD
Chip Enable to Power Up Time
0
Chip Disable to Power Down Time
15
20
35
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
Document # SRAM135 REV OR
Page 4 of 11
P4C1298/L
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,6)
Notes:
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM135 REV OR
Page 5 of 11
P4C1298/L
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
-45
Sym
Parameter
Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time
15
10
10
0
20
15
15
0
25
20
20
0
35
25
25
0
45
30
30
0
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Set-up Time
tWP Write Pulse Width
10
0
15
0
20
0
25
0
30
0
tAH Address Hold Time from End of Write
tDW Data Valid to End of Write
tDH Data Hold Time
9
10
0
15
0
20
0
20
0
0
tWZ Write Enable to Output in High Z
tOW Output Active from End of Write
7
10
15
20
20
0
0
0
0
0
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9)
Notes:
12. Write Cycle Time is measured from the last valid address to the first
transition address.
9. CE and WE must be LOW for WRITE cycle.
10. OE is LOW for this WRITE cycle.
13. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
11. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
Document # SRAM135 REV OR
Page 6 of 11
P4C1298/L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9,10)
AC TEST CONDITIONS
TRUTH TABLE
Mode
Standby
Read
CE
H
L
WE
X
Output
High Z
DOUT
Power
Standby
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
H
Write
L
L
DIN
Active
1.5V
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Because of the ultra-high speed of the P4C1298, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Document # SRAM135 REV OR
Page 7 of 11
P4C1298/L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1298 is available in the following temperature, speed and package options.
Speed
Temperature
Range
Package
15
20
25
35
Commercial
Industrial
Plastic SOJ, 300 mil
Plastic SOJ, 300 mil
Ceramic DIP, 300 mil
28-Pin Ceramic LCC
Ceramic DIP, 300 mil
28-Pin Ceramic LCC
-15J3C
-15J3I
-20J3C
-20J3I
-25J3C
-25J3I
-35J3C
-35J3I
Military
Temperature
-15CM
-20CM
-20L28M
-20CMB
-25CM
-35CM
-15L28M
-15CMB
-15L28MB
-25L28M
-25CMB
-25L28MB
-25L28M
-35CMB
-25L28MB
Military
Processeed*
-20L28MB
Document # SRAM135 REV OR
Page 8 of 11
P4C1298/L
Pkg #
SOJ SMALL OUTLINE IC PACKAGE
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
0.020
0.011
0.730
A
A1
b
C
D
0.120
0.078
0.014
0.007
0.700
e
E
E1
E2
Q
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
0.025
-
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
-
Max
0.210
-
0.023
0.070
0.014
1.400
0.300
0.380
A
A1
b
b2
C
D
E1
E
0.014
0.045
0.008
1.345
0.270
0.300
e
0.100 BSC
eB
L
α
-
0.430
0.150
15°
0.115
0°
Document # SRAM135 REV OR
Page 9 of 11
P4C1298/L
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
L5
# Pins
Symbol
A
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
5
9
SIDEBRAZED DUAL IN-LINE PACKAGE
Pkg #
C5
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
Document # SRAM135 REV OR
Page 10 of 11
P4C1298/L
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM135
P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
DATE
REV.
DESCRIPTIONOFCHANGE
OR
Apr-07
JDB
NewDataSheet
Document # SRAM135 REV OR
Page 11 of 11
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