P4C150-12DC [PYRAMID]
ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM; 超高速1K ×4 RESETTABLE静态CMOS RAM
| 型号： | P4C150-12DC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM |
| 文件： | 总11页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C150
ULTRA HIGH SPEED 1K X 4
RESETTABLE STATIC CMOS RAM
FEATURES
Separate Input and Output Ports
Full CMOS, 6T Cell
Three-StateOutputs
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Military)
Fully TTL Compatible Inputs and Outputs
StandardPinout(JEDECApproved)
– 24-Pin 300 mil DIP
Chip Clear Function
– 24-Pin 300 mil SOIC
– 28-Pin LCC (350 x 550 mils)
– 24-Pin CERPACK
Low Power Operation
Single 5V ± 10% Power Supply
DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM
organized as 1K x 4 for high speed cache applications.
The RAM features a reset control to enable clearing all
wordstozerowithintwocycletimes.TheCMOSmemory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs and outputs are fully TTL-
compatible. The RAM operates from a single 5V ± 10%
tolerance power supply.
Time required to reset is only 20 ns for the 10 ns SRAM.
CMOS is used to reduce power consumption to a low
level.
TheP4C150isavailablein24-pin300milDIPandSOIC
packages providing excellent board level densities.
The device is also available in a 28-pin LCC package as
well as a 24-pin FLATPACK for military applications.
Access times as fast as 10 nanoseconds are available
permitting greatly enhanced system operating speeds.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P4, C4, D4), SOIC (S4)
CERPACK (F3) SIMILAR
LCC(L5)
Document # SRAM105 REV A
Revised October 2005
1
P4C150
MAXIMUMRATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125 °C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
IOUT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150 °C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VTERM
TA
VCC +0.5
V
1.0
50
W
mA
Operating Temperature –55 to +125 °C
RECOMMENDED OPERATING
CONDITIONS
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Commercial
Military
Ambient Temp
Gnd
VCC
Symbol
CIN
Parameter
Input Capacitance VIN = 0V
Conditions Typ. Unit
5
pF
0°C to 70°C
0V 5.0V ± 10%
0V 5.0V ± 10%
-55°C to +125°C
COUT
Output Capacitance VOUT= 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
P4C150
Unit
Symbol
Test Conditions
IOH = –4 mA, VCC = Min.
IOL = +8 mA, VCC = Min
Parameter
Max.
Min.
VOH
Output High Voltage
(TTL Load)
V
2.4
VOL
Output Low Voltage
(TTL Load)
V
0.4
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
V
CC =+0.5
0.8
V
V
–0.5(3)
ILI
µA
µA
V
CC = Max., VIN = GND to VCC
–5
–5
+5
+5
Input Leakage Current
Output Leakage Current
ILO
VCC = Max., CS = VIH, VOUT = GND to VCC
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
-35
N/A
120
-10
-12 -15
-20
-25
100
125
Unit
Range
130 130
N/A N/A
120 115
145 135
mA
mA
Commercial
ICC
Dynamic Operating Current
Military
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V and IIL not more negative than –3.0V and
–100mA, respectively, IaL re permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to MAXIMUM rating condi-
tions for extended periods may affect reliability.
Document # SRAM105 REV A
Page 2 of 11
P4C150
ACCHARACTERISTICS—READCYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-20
-25
-35
-10
Min Max
-15
Sym.
Parameter
Unit
Max
Max
Max
Max Max
Min
Min
Min
Min
Min
tRC
tAA
tAC
Read Cycle Time
Address Access Time
Chip Select Access Time
10
10
8
12
15
20
25
35
ns
ns
ns
12
10
15
12
20
14
25
15
35
35
Output Hold from
Address Change
tOH
tLZ
tHZ
tOE
tOLZ
tOHZ
2
2
4
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
6
9
8
10
14
13
15
15
20
Output Enable to
Data Valid
7
10
ns
Output Enable to
Output in Low Z
2
2
2
2
2
2
ns
ns
Output Disable to
Output in High Z
5
7
9
11
13
16
TIMINGWAVEFORMOFREADCYCLENO.1(5,6)
TIMINGWAVEFORMOFREADCYCLENO. 2(CS CONTROLLED)(5,7)
Notes:
5.WE is HIGH for READ cycle.
8. Transitionismeasured±200mVfromsteadystatevoltage
priortochange,withloadingasspecifiedinFigure1.
9. ReadCycleTimeismeasuredfromthelastvalidaddressto
thefirsttransitioningaddress.
6.CS and OE are LOW for READ cycle.
7.ADDRESSmustbevalidpriorto, orconcidentwith, CS transition
LOW, tAA must still be met.
Document # SRAM105 REV A
Page 3 of 11
P4C150
TIMING WAVEFORM OF READ CYCLE NO. 3 (OE Controlled)(5)
AC CHARACTERISTICS—RESET CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
Min Max
40
-25
-35
-10
Min Max
Parameter
Unit
Symbol
Min Max Min Max
Min Max Min Max
tRRC
tWER
ns
ns
Reset Cycle Time
24
0
30
0
50
0
70
0
20
0
Write Enable High to
Beginning of Reset
0
tCR
Chip Select Low to
Beginning of Reset
0
0
0
0
0
0
ns
tRP
tHCR
Reset Pulse Width
10
0
12
0
15
0
20
0
25
0
30
0
ns
ns
Chip Select Hold
after End of Reset
Write Enable Hold
after End of Reset
tHWR
tRLZ
tRHZ
10
0
12
0
15
0
20
0
25
0
35
0
ns
ns
ns
Reset High to
Output in Low Z
Reset Low to
0
8
0
10
0
12
0
16
0
20
0
Output in High Z
TIMING WAVEFORM OF RESET CYCLE
Document # SRAM105 REV A
Page 4 of 11
P4C150
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-25
-12
-15
-20
-35
Unit
Sym.
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time
10
12
15
20
25
35
ns
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Set-up Time
8
8
0
8
10
10
1
11
13
1
13
16
1
15
20
2
20
25
2
ns
ns
ns
ns
tWP Write Pulse Width
10
11
13
15
20
Address Hold Time from
tAH
0
1
1
1
2
ns
2
End of Write
tDW Data Valid to End of Write
tDH Data Hold Time
5
0
8
1
11
1
13
1
15
2
20
2
ns
ns
ns
ns
Write Enable to Output in High Z
Output Active from End of Write
8
25
tWZ
tOW
5
12
15
20
2
2
2
3
3
3
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED)(10)
Notes:
12. Write Cycle Time is measured from the last valid address to the first
transition address.
10. CS and WE must be LOW for WRITE cycle.
11. If CS goes HIGH simultaneously with WE high, the output remains
in a high impedance state.
Document # SRAM105 REV A
Page 5 of 11
P4C150
AC TEST CONDITIONS
TRUTH TABLE
Mode
Not Selected
RESET
Output Disabled
READ
RS
CS OE WE
Output
High Z
High Z
High Z
DOUT
Input Pulse Levels
GND to 3.0V
X
H
X
X
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
L
H
H
L
L
L
X
H
L
H
H
H
See Figures 1 and 2
WRITE
H
X
L
High Z
L
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Duetotheultra-highspeedoftheP4C150,caremustbetakenwhentesting
thisdevice;aninadequatesetupcancauseanormalfunctioningparttobe
rejectedasfaulty. Longhigh-inductanceleadsthatcausesupplybounce
must be avoided by bringing the VCC and ground planes directly up to the
contactor fingers. A 0.01 µF high frequency capacitor is also required
between V and ground. To avoid signal reflections, proper termination
mustbeusCeCd;forexample,a50Ω testenvironmentshouldbeterminated
intoa50Ω loadwith1.73V(TheveninVoltage)atthecomparatorinput,and
a116Ω resistormustbeusedinserieswithDOUT tomatch166Ω (Thevenin
Resistance).
Document # SRAM105 REV A
Page 6 of 11
P4C150
ORDERING INFORMATION
SELECTION GUIDE
The P4C150 is available in the following temperature, speed and package options.
Speed (ns)
Temperature
Range
Package
10
-10PC
-10SC
N/A
N/A
N/A
12
-12PC
-12SC
N/A
N/A
N/A
15
20
25
35
Plastic DIP
-15PC
-15SC
-15CM
-15DM
-15FM
-20PC
-20SC
-20CM
-20DM
-20FM
-20LM
-25PC
-25SC
-25CM
-25DM
-25FM
-25LM
N/A
N/A
-35CM
-35DM
-35FM
-35LM
Commercial
Temperature
Plastic SOIC
Side Brazed DIP
CERDIP
CERPACK
LCC
Military
Temperature
N/A
N/A
-15LM
Side Brazed DIP
CERDIP
CERPACK
LCC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-15CMB
-15DMB
-15FMB
-15LMB
-20CMB
-20DMB
-20FMB
-20LMB
-25CMB
-25DMB
-25FMB
-25LMB
-35CMB
-35DMB
-35FMB
-35LMB
Military
Processed*
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM105 REV A
Page 7 of 11
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C4
# Pins
24 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.280
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.060
-
-
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D4
# Pins
24 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.280
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM105 REV A
Page 8 of 11
P4C150
CERPACK CERAMIC FLAT PACKAGE
Pkg #
F3
# Pins
24
Symbol
Min
0.060
0.015
0.004
-
Max
A
0.090
0.022
0.009
0.630
0.380
b
c
D
E
e
0.330
0.050 BSC
k
L
Q
S
S1
0.008
0.015
0.370
0.045
0.085
-
0.250
0.026
-
0.005
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.045
0.075
0.055
0.055
0.095
L1
L2
ND
NE
5
9
Document # SRAM105 REV A
Page 9 of 11
P4C150
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P4
# Pins
24 (300 Mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
1.280
0.280
0.325
A
A1
b
0.015
0.014
0.045
0.008
1.230
0.240
0.300
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S4
# Pins
24 (300 Mil)
Symbol
Min
Max
A
A1
b2
C
D
e
0.093
0.004
0.013
0.009
0.598
0.104
0.012
0.020
0.012
0.614
0.050 BSC
E
0.291
0.394
0.010
0.016
0°
0.299
0.419
0.029
0.050
8°
H
h
L
α
Document # SRAM105 REV A
Page 10 of 11
P4C150
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM105
P4C150 ULTRA HIGH SPEED 1K x 4 RESETTABLE STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTIONOFCHANGE
DATE
OR
A
1997
DAB
NewDataSheet
Oct-05
JDB
Change logo to Pyramid
Document # SRAM105 REV A
Page 11 of 11
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