P4C170-15JM [PYRAMID]
ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS; 超高速4K ×4的静态CMOS RAMS
| 型号： | P4C170-15JM |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS |
| 文件： | 总15页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C168, P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Fully TTL Compatible, Common I/O Ports
Three Options
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35ns (Commercial)
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
– 20/25/35/45/55/70ns (P4C168 Military)
Low Power Operation (Commercial)
– 715 mW Active
Standard Pinout (JEDEC Approved)
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
– P4C168: 20-pin DIP, SOJ, LCC, SOIC,
CERPACK, and Flat Pack
Single 5V±10% Power Supply
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
DESCRIPTION
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOSisusedtoreducepowerconsumptiontoalow715
mW active, 193 mW standby.
The P4C168, P4C169 and P4C170 are a family of
16,384-bitultrahigh-speedstaticRAMsorganizedas4K
x4. Allthreedeviceshavecommoninput/outputports.The
P4C168 enters the standby mode when the chip enable
(CE) control goes HIGH; with CMOS input levels, power
consumptionisonly83mWinthismode.BoththeP4C169
and the P4C170 offer a fast chip select access time that
is only 67% of the address access time. In addition, the
P4C170 includes an output enable (OE) control to elimi-
nate data bus contention. The RAMs operate from a
single 5V ± 10% tolerance power supply.
TheP4C168andP4C169areavailablein20-pin(P4C170
in 22-pin) 300 mil DIP packages providing excellent
boardleveldensities. TheP4C168isalsoavailablein20-
pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack
packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
P4C170
P4C168
P4C169
DIP (P2)
SOIC (S2)
DIP (P3)
DIP (P2, C6, D2)
SOIC (S2)
SOJ (J2)
CERPACK (F2)
SOLDER SEAL FLAT PACK (FS-2)
Document # SRAM107 REV A
Revised October 2005
1
P4C168, P4C169, P4C170
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125 °C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
IOUT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150 °C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VTERM
TA
VCC +0.5
V
1.0
50
W
mA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
RECOMMENDED OPERATING CONDITIONS
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Commercial
Ambient Temp
0°C to 70°C
Gnd
0V 5.0V ± 10%
VCC
Symbol
CIN
Parameter
Input Capacitance VIN = 0V
Conditions Typ. Unit
5
pF
–55°C to +125°C
Military
0V 5.0V ± 10%
COUT
Output Capacitance VOUT= 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
P4C168/169/170
Symbol
Parameter
Unit
Test Conditions
Min
2.2
–0.5(3)
Max
VCC +0.5
0.8
VIH
VIL
Input High Voltage
Input Low Voltage
V
V
V
V
V
V
VHC
VLC
VCD
VOL
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output Low Voltage
(CMOS Load)
Output High Voltage
(TTL Load)
V
CC –0.2
VCC +0.5
–0.5(3)
0.2
–1.2
0.4
VCC = Min., IIN = –18 mA
IOL = +8 mA, VCC = Min.
IOLC = +100 µA, VCC = Min.
IOH = –4 mA, VCC = Min.
IOHC = –100 µA, VCC = Min.
VOLC
VOH
0.2
V
V
V
2.4
VOHC
Output High Voltage
(CMOS Load)
V
CC –0.2
–10
–5
+10
+5
Mil.
Input Leakage Current
VCC = Max., VIN = GND to VCC
µA
ILI
Comm’l
Mil.
–10
+10
VCC = Max., CS = VIH,
ILO
Output Leakage Current
µA
mA
mA
Comm’l
–5
+5
VOUT = GND to VCC
___
___
Dynamic Operating
Current
Standby Power Supply
Current (TTL Input Levels)
P4C168 only
VCC = Max., f = Max., Outputs Open
130
35
ICC
ISB
CE ≥ V , VCC = Max., f = Max.,
OutputIsH Open
___
ISB1
CE ≥ V , V = Max., f = 0,
OutputHsCOpCeCn
15
Standby Power
Supply Current
(CMOS Input Levels)
P4C168 only
mA
VIN ≤ VLC or VIN ≥ VHC
Document # SRAM107 REV A
Page 2 of 15
P4C168, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
Sym
tRC
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
12
15
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tAC
tAC
Address Access Time
12
12
8
15
15
9
20
20
12
25
25
15
35
35
20
§
‡
Chip Enable Access Time
Chip Select Access Time
tOH
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Data Valid
Output Enable to Output in Low Z
Output Disable to Output in High Z
Read Command Setup Time
Read Command Hold Time
2
2
2
2
2
2
2
2
2
2
‡
tLZ
†
†
tHZ
tOE
7
8
8
9
10
15
15
15
10
12
†
tOLZ
0
0
0
0
0
†
tOHZ
tRCS
6
7
9
11
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
tRCH
§
tPU
Chip Enable to Power Up Time
Chip Disable to Power Down Time
§
tPD
12
15
20
25
35
AC CHARACTERISTICS—READ CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-45
-55
-70
Sym
Parameter
Unit
Min Max Min Max Min Max
tRC
tAA
Read Cycle Time
45
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
45
45
55
55
70
70
§
tAC
Chip Enable Access Time
tOH
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
2
2
2
2
2
2
‡
tLZ
†
tHZ
25
45
25
55
30
70
tRCS
tRCH
0
0
0
0
0
0
0
0
0
§
tPU
§
tPD
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
Document # SRAM107 REV A
Page 3 of 15
P4C168, P4C169, P4C170
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6)
Notes:
5. WE is HIGH for READ cycle.
6. CE/CS and OE are LOW for READ cycle.
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE/CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE CONTROLLED)(5)
Notes:
7. ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, tAA must still be met.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
Document # SRAM107 REV A
Page 4 of 15
P4C168, P4C169, P4C170
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
Sym
tWC
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max
Write Cycle Time
12
12
12
0
15
15
15
0
18
18
18
0
20
20
20
0
30
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcw
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
tAW
tAS
tWP
tAH
tDW
tDH
tWZ
tOW
Write Pulse Width
12
0
15
0
18
0
20
0
30
0
Address Hold Time
Data Valid to End of Write
Data Hold Time
7
8
10
0
10
0
15
0
0
0
Write Enable to Output in High Z
Output Active from End of Write
4
5
6
7
13
0
0
0
0
0
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-45
-55
-70
Sym
tWC
Parameter
Unit
Min Max Min Max Min Max
Write Cycle Time
45
40
40
0
55
50
50
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcw
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
tAW
tAS
tWP
tAH
tDW
tDH
tWZ
tOW
Write Pulse Width
40
0
50
0
60
0
Address Hold Time
Data Valid to End of Write
Data Hold Time
20
3
20
3
25
3
Write Enable to Output in High Z
Output Active from End of Write
20
25
30
0
0
0
Document # SRAM107 REV A
Page 5 of 15
P4C168, P4C169, P4C170
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10)
Notes:
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE/CS CONTROLLED)(10)
TRUTH TABLES
P4C168 (P4C169)
P4C170
Mode
Deselect
Read
Output Inhibit
Write
CE
H
L
WE
X
H
OE
X
L
Output
High Z
DOUT
Mode
Standby (Deselect)
Read
CE (CS)
WE
X
H
Output
High Z
DOUT
H
L
L
L
L
H
L
H
X
High Z
High Z
Write
L
High Z
Document # SRAM107 REV A
Page 6 of 15
P4C168, P4C169, P4C170
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long high-
inductance leads that cause supply bounce must be avoided by bringing
the VCC and ground planes directly up to the contactor fingers. A high
frequency capacitor of 0.01 µF is also required between VCC andground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω
resistor must be used in series with DOUT to match 166Ω (Thevenin
Resistance).
LCC PIN CONFIGURATION
LCC (L9)
Document # SRAM107 REV A
Page 7 of 15
P4C168, P4C169, P4C170
ORDERING INFORMATION
SELECTION GUIDE
The P4C168, P4C169 and P4C170 are available in the following temperature, speed and package options.
Speed
Temperature
Range
Package
Plastic DIP
Plastic SOIC†
Plastic SOJ††
LCC
12
-12PC
-12SC
-12JC
N/A
15
-15PC
-15SC
-15JC
20
-20PC
-20SC
-20JC
25
35
-25PC
N/A
Commercial
Temperature
-25SC
N/A
-25JC
N/A
-15LM
-20LM
-25LM
-35LM
-35DM
-35CM
-35FM
-35FSM
-35LMB
-35DMB
-35CMB
-35FMB
-35FSMB
CERDIP
Side Brazed DIP
CERPACK
N/A
N/A
N/A
-15DM
-15CM
-15FM
-20DM
-20CM
-20FM
-25DM
-25CM
-25FM
-25FSM
-25LMB
-25DMB
-25CMB
-25FMB
-25FSMB
Military
Temperature
(P4C168 only)
Solder Seal Flat Pack
LCC
CERDIP
Side Brazed DIP
CERPACK
Solder Seal Flat Pack
N/A
N/A
N/A
N/A
N/A
N/A
-15FSM
-15LMB
-15DMB
-15CMB
-15FMB
-15FSMB
-20FSM
-20LMB
-20DMB
-20CMB
-20FMB
-20FSMB
Military
Processed*
(P4C168 only)
† P4C168 and P4C169 only.
†† P4C168
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Document # SRAM107 REV A
Page 8 of 15
P4C168, P4C169, P4C170
SELECTION GUIDE (CONTINUED)
Temperature
Package
Range
Speed
45
55
70
LCC
-45LM
-55LM
-70LM
CERDIP
Side Brazed DIP
CERPACK
-45DM
-45CM
-45FM
-55DM
-55CM
-55FM
-70DM
-70CM
-70FM
Military
Temperature
(P4C168 only)
Solder Seal Flat Pack
LCC
CERDIP
Side Brazed DIP
CERPACK
Solder Seal Flat Pack
-45FSM
-45LMB
-45DMB
-45CMB
-45FMB
-55FSMB
-55FSM
-55LMB
-55DMB
-55CMB
-55FMB
-55FSMB
-70FSM
-70LMB
-70DMB
-70CMB
-70FMB
-70FSMB
Military
Processed*
(P4C168 only)
* Military temperature range with MIL-STD-883, Class B processing.
Document # SRAM107 REV A
Page 9 of 15
P4C168, P4C169, P4C170
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C6
# Pins
20 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.060
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
CERPACK CERAMIC FLAT PACKAGE
Pkg #
# Pins
Symbol
F2
20
Min
0.060
0.015
0.004
-
Max
A
0.090
0.022
0.009
0.530
0.355
b
c
D
E
e
0.305
0.050 BSC
k
L
Q
S
S1
0.005
0.018
0.370
0.045
0.085
-
0.250
0.026
-
0.005
Document # SRAM107 REV A
Page 10 of 15
P4C168, P4C169, P4C170
SOLDER SEAL FLAT PACKAGE
Pkg #
FS-2
# Pins
20
Symbol
Min
Max
0.115
0.022
0.019
0.009
0.006
0.540
0.300
0.330
-
A
b
0.045
0.015
0.015
0.004
0.004
-
b1
c
c1
D
E
0.245
-
E1
E2
E3
e
0.130
0.030
-
0.050 BSC
k
L
Q
S1
M
N
0.008
0.250
0.026
0.000
-
0.015
0.370
0.045
-
0.0015
20
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
# Pins
Symbol
J2
20 (300 mil)
Min
Max
0.140
-
0.020
0.013
0.512
A
A1
b
0.120
0.080
0.014
0.008
0.496
C
D
e
0.050 BSC
E
0.335
0.292
0.347
0.300
E1
E2
Q
0.267 BSC
0.025
-
Document # SRAM107 REV A
Page 11 of 15
P4C168, P4C169, P4C170
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
L9
# Pins
Symbol
A
20
Min
Max
0.060
0.050
0.022
0.280
0.075
0.066
0.028
0.305
A1
B1
D
D1
D2
D3
E
0.150 BSC
0.075 BSC
-
0.305
0.440
0.420
E1
E2
E3
e
0.250 BSC
0.125 BSC
-
0.440
0.050 BSC
0.020 REF
0.010 REF
h
j
L
0.045
0.045
0.075
0.055
0.055
0.098
L1
L2
ND
NE
4
6
PLASTIC DUAL IN-LINE PACKAGE (P4C168, P4C169)
Pkg #
P2
# Pins
20 (300 mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
1.060
0.280
0.325
A
A1
b
0.015
0.014
0.045
0.008
0.980
0.240
0.300
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM107 REV A
Page 12 of 15
P4C168, P4C169, P4C170
PLASTIC DUAL IN-LINE PACKAGE (P4C170)
Pkg #
P3
# Pins
22 (300 Mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
1.165
0.280
0.325
A
A1
b
0.015
0.014
0.045
0.008
1.145
0.240
0.300
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S2
# Pins
20 (300 mil)
Symbol
Min
Max
A
A1
b2
C
D
e
0.093
0.004
0.013
0.009
0.496
0.104
0.012
0.020
0.012
0.511
0.050 BSC
E
0.291
0.394
0.010
0.016
0°
0.299
0.419
0.029
0.050
8°
H
h
L
α
Document # SRAM107 REV A
Page 13 of 15
P4C168, P4C169, P4C170
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D2
# Pins
20 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.060
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.070
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM107 REV A
Page 14 of 15
P4C168, P4C169, P4C170
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM107
P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
OR
A
1997
DAB
New Data Sheet
Oct-05
JDB
Change logo to Pyramid
Document # SRAM107 REV A
Page 15 of 15
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