P4C198-35PMB [PYRAMID]
ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS; 超高速16K ×4的静态CMOS RAMS
| 型号： | P4C198-35PMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| 文件： | 总13页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C198/P4C198L, P4C198A/P4C198AL
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
FEATURES
Output Enable & Chip Enable Control Functions
Full CMOS, 6T Cell
– Single Chip Enable P4C198
– Dual Chip Enable P4C198A
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
Common Inputs and Outputs
– 15/20/25/35/45 ns (Military)
Fully TTL Compatible Inputs and Outputs
Low Power Operation (Commercial/Military)
5V ± 10% Power Supply
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 28-Pin 350 x 550 mil LCC
Data Retention, 10 µA Typical Current from 2.0V
P4C198L/198AL(Military)
DESCRIPTION
TheP4C198/LandP4C198A/Lare65,536-bitultrahigh-
speed static RAMs organized as 16K x 4. Each device
featuresanactivelowOutputEnablecontroltoeliminate
data bus contention. The P4C198/L also have an active
lowChipEnable(theP4C198A/LhavetwoChipEnables,
both active low) for easy system expansion. The CMOS
memoriesrequirenoclocksorrefreshingandhaveequal
access and cycle times. Inputs are fully TTL-compatible.
The RAMs operate from a single 5V ± 10% tolerance
power supply. Data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOSisusedtoreducepowerconsumptiontoalow715
mW active, 193 mW standby.
The P4C198/L and P4C198A/L are available in 24-pin
300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC
packages providing excellent board level densities.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (P4, C4, D4),
LCC (L5)
SOJ (J4)
P4C198 (P4C198A)
P4C198(P4C198A)
Document # SRAM113 REV A
Revised October 2005
1
P4C198/198L, P4C198A/198AL
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
IOUT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
mA
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VTERM
TA
VCC +0.5
V
1.0
50
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
RECOMMENDED OPERATING
VCC = 5.0V, TA = 25°C, f = 1.0MHz
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Symbol
Parameter
Conditions Typ. Unit
VCC
Grade(2)
GND
Temperature
CIN
COUT
VIN = 0V
VOUT = 0V
pF
pF
Military
Commercial
Industrial
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
Input Capacitance
Output Capacitance
5
7
–55°C to +125°C
0°C to +70°C
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C198 / 198A
P4C198L / 198AL
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
VIH
VIL
VHC
VLC
VCD
2.2
–0.5(3)
VCC +0.5
2.2
–0.5(3)
VCC +0.5
V
V
V
V
V
Input High Voltage
0.8
0.8
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
–0.5(3)
0.2
–0.5(3)
0.2
VCC = Min., IIN = –18 mA
–1.2
–1.2
Input Clamp Diode Voltage
Output Low Voltage
IOL = +10 mA, VCC = Min.
V
V
0.5
2.4
0.5
2.4
VOL
(TTL Load)
IOL = +8 mA, VCC = Min.
0.4
0.4
Output High Voltage
(TTL Load)
VOH
V
IOH = –4 mA, VCC = Min.
VCC = Max.
Mil.
–10
–5
+10
+5
–5
+5
µA
ILI
Input Leakage Current
Output Leakage Current
n/a
n/a
VIN = GND to VCC
VCC = Max., CE = VIH,
Ind./Com’l.
Mil.
–10
–5
+10
+5
–5
+5
µA
ILO
n/a
n/a
VOUT = GND to VCC Ind./Com’l.
___
___
___
___
CE1, CE2 ≥ V
Mil.
40
35
40
mA
VCC = Max ., IH
Ind./Com’l.
n/a
Standby Power Supply
ISB
Current (TTL Input Levels)
f = Max., Outputs Open
___
___
___
___
20
15
1.5
n/a
mA
CE1, CE2 ≥ VIH
Mil.
Ind./Com’l.
Standby Power Supply
Current
VCC = Max.,
ISB1
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
(CMOS Input Levels)
n/a = Not Applicable
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM ratingconditions for extended
periods may affect reliability.
Document # SRAM113 REV A
Page 2 of 13
P4C198/198L, P4C198A/198AL
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
–10 –12 –15 –20 –25 –35 –45
180 170 160 155 150 N/A N/A
Commercial
mA
Dynamic Operating Current*
ICC
N/A 180 170 160 155 150 N/A mA
N/A N/A 170 160 155 150 145 mA
Industrial
Military
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
198: CE = VIL, OE = VIH
198A: CE1 = VIL, CE2 = VIL. OE = VIH
DATA RETENTION CHARACTERISTICS (P4C198L/P4C198AL Military Temperature Only)
Typ.*
VCC=
Max
2.0VCC 3.0V
Symbol
Parameter
Test Condition
Min
V =
Unit
2.0V
3.0V
VDR
ICCDR
VCC for Data Retention
Data Retention Current
2.0
V
µA
10
15
600
900
tCDR
Chip Deselect to
CE ≥VCC – 0.2V,
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
0
ns
ns
Data Retention Time
†
§
tR
Operation Recovery Time
tRC
*TA = +25°C
§
tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM113 REV A
Page 3 of 13
P4C198/198L, P4C198A/198AL
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
Sym.
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC Read Cycle Time 10
tAA Address Access
Time
tAC Chip Enable
Access Time
12
15
20
25
35
45
ns
ns
10
10
12
12
15
15
20
20
25
25
35
35
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOH Output Hold from
Address Change
tLZ Chip Enable to
Output in Low Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
tHZ Chip Disable to
Output in High Z
tOE Output Enable
Low to Data Valid
6
6
7
7
8
9
10
12
10
15
14
25
15
30
tOLZ Output Enable to
Output in Low Z
tOHZ Output Disable to
Output in High Z
tPU Chip Enable to
Power Up Time
2
0
2
0
2
0
2
0
2
0
2
0
2
0
6
7
9
9
10
25
14
35
15
45
tPD Chip Disable to
Power Down Time
10
12
15
20
READ CYCLE NO.1 (OE controlled)(5)
Notes:
5. WE is HIGH for READ cycle.
Document # SRAM113 REV A
Page 4 of 13
P4C198/198L, P4C198A/198AL
READ CYCLE NO. 2 (ADDRESS Controlled)(5,6)
READ CYCLE NO. 3 (CE(12) Controlled)(5,7,8)
Notes:
10. Read Cycle Time is measured from the last valid address
to the first transitioning address.
6. CE (CE1 CE2 for P4C198A/L) and OE are LOW READ cycle.
7. OE is LOW for the cycle.
11. Transitions caused by a chip enable control have similar
delays irrespective of whether CE1 or CE2 causes them
(P4C198A/L).
8. ADDRESS must be valid prior to, or coincident with CE (CE1
and CE2 for P4C198A/L) transition LOW.
9. Transition is measured ± 200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
12. CE1, CE2 for P4C198A/L.
Document # SRAM113 REV A
Page 5 of 13
P4C198/198L, P4C198A/198AL
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
Sym.
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time 10
12
8
13
10
15
15
20
20
30
30
40
35
ns
ns
tCW Chip Enable Time
to End of Write
7
8
0
8
0
tAW Address Valid to
End of Write
8
0
9
0
10
0
15
0
20
0
25
0
35
0
ns
ns
ns
ns
tAS Address Set-up
Time
tWP Write Pulse
Width
10
0
12
0
20
0
25
0
35
0
tAH Address Hold
Time from End
of Write
tDW Data Valid to End
of Write
tDH Data Hold Time
tWZ Write Enable to
Output in High Z
7
0
6
0
7
0
10
0
13
0
15
0
20
0
ns
ns
ns
7
6
7
8
10
10
15
tOW Output Active
from End of Write
3
3
3
3
3
3
3
ns
WRITE CYCLE NO. 1 (With OE high)
Document # SRAM113 REV A
Page 6 of 13
P4C198/198L, P4C198A/198AL
WRITE CYCLE NO. 2 (WE CONTROLLED)(13,14)
WRITE CYCLE NO. 3 (CE(12) CONTROLLED)(13,14)
Notes:
15. If CE (CE1 or CE2 for P4C198A/L) goes HIGH simultaneously with WE
HIGH, the output remains in a high impedance state.
16. Write Cycle Time is measured from the last valid address to the first
transitioning address.
13. CE (CE1, CE2 for P4C198A/L) and WE must be LOW for WRITE
cycle.
14. OE is LOW for this WRITE cycle.
Document # SRAM113 REV A
Page 7 of 13
P4C198/198L, P4C198A/198AL
TRUTH TABLES
P4C198/L
P4C198A/L
CE WE
OE
X
H
L
Mode
Standby
Output Inhibit
READ
Output
High Z
High Z
DOUT
CE1 CE2 WE
OE
X
X
H
L
X
Mode
Standby
Standby
Output Inhibit
READ
Output
High Z
High Z
High Z
DOUT
H
L
L
L
X
H
H
L
H
X
L
L
L
X
H
L
L
L
X
X
H
H
L
X
WRITE
DIN
WRITE
DIN
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
frequency capacitor is also required between V and ground. To avoid
signal reflections, proper termination must be uCsCed; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Because of the ultra-high speed of the P4C198/L and P4C198A/L, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Document # SRAM113 REV A
Page 8 of 13
P4C198/198L, P4C198A/198AL
ORDERING INFORMATION
SELECTION GUIDE
The P4C198 and P4C198A are available in the following temperature, speed and package options.
Speed (ns)
Temperature
Range
Commercial
Package
Plastic DIP
Plastic SOJ
Plastic DIP
Plastic SOJ
Side Brazed DIP
CERDIP
10
-10PC
-10JC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12
-12PC
-12JC
-12PI
-12JI
N/A
N/A
N/A
N/A
N/A
15
-15PC
-15JC
-15PI
-15JI
-15CM
-15DM
-15LM
-15CMB
-15DMB
-15LMB
20
-20PC
-20JC
-20PI
-20JI
-20CM
-20DM
-20LM
-20CMB
-20DMB
-20LMB
25
-25PC
-25JC
35
N/A
N/A
45
N/A
N/A
Industrial
-25PI
-35PI
N/A
-25JI
-35JI
N/A
Military
Temperature
-25CM
-25DM
-25LM
-25CMB
-25DMB
-25LMB
-35CM
-35DM
-35LM
-35CMB
-35DMB
-35LMB
-45CM
-45DM
-45LM
-45CMB
-45DMB
-45LMB
LCC
Side Brazed DIP
CERDIP
Military
Processed*
LCC
N/A
N/A
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Document # SRAM113 REV A
Page 9 of 13
P4C198/198L, P4C198A/198AL
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C4
# Pins
24 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.280
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.060
-
-
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D4
# Pins
24 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.280
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM113 REV A
Page 10 of 13
P4C198/198L, P4C198A/198AL
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
# Pins
Symbol
J4
24 (300 mil)
Min
Max
0.148
-
0.020
0.010
0.630
A
A1
b
0.128
0.082
0.016
0.007
0.620
C
D
e
0.050 BSC
0.335 BSC
0.292 0.300
E
E1
E2
Q
0.267 BSC
0.025
-
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.045
0.075
0.055
0.055
0.095
L1
L2
ND
NE
5
9
Document # SRAM113 REV A
Page 11 of 13
P4C198/198L, P4C198A/198AL
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P4
# Pins
24 (300 Mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
1.280
0.280
0.325
A
A1
b
0.015
0.014
0.045
0.008
1.230
0.240
0.300
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM113 REV A
Page 12 of 13
P4C198/198L, P4C198A/198AL
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM113
P4C198 / P4C198L, P4C198A / P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS
RAMS
ORIG. OF
ISSUE
REV.
DESCRIPTIONOFCHANGE
NewDataSheet
DATE
CHANGE
OR
A
1997
DAB
Oct-05
JDB
Change logo to Pyramid
Document # SRAM113 REV A
Page 13 of 13
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