P4C422-25CC [PYRAMID]
HIGH SPEED 256 x 4 STATIC CMOS RAM; HIGH SPEED 256 ×4的静态CMOS RAM
| 型号： | P4C422-25CC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | HIGH SPEED 256 x 4 STATIC CMOS RAM |
| 文件： | 总10页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C422
HIGH SPEED 256 x 4
STATIC CMOS RAM
FEATURES
Separate I/O
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
Fully TTL Compatible Inputs and Outputs
Resistant to single event upset and latchup
resulting from advanced process and design
improvements
CMOS for Low Power
– 495 mW Max. – 10/12/15/20/25 (Commercial)
– 495 mW Max. – 15/20/25/35 (Military)
Standard 22-pin 400 mil DIP, 24-pin 300 mil
SOIC, 24-pin square LCC package and 24-pin
CERPACK package
Single 5V±10% Power Supply
DESCRIPTION
The P4C422 is a 1,024-bit high-speed (10ns) Static
RAM with a 256 x 4 organization. The memory requires
no clocks or refreshing and has equal access and cycle
times. Inputs and outputs are fully TTL compatible.
Operation is from a single 5 Volt supply. Easy memory
expansion is provided by an active LOW chip select one
(CS1) and active HIGH chip select two (CS2) as well as
3-state outputs.
In addition to high performance and high density, the
device features latch-up protection, single event and
upset protection. The P4C422 is offered in several
packages: 22-pin 400 mil DIP (plastic and ceramic), 24-
pin 300 mil SOIC, 24-pin square LCC and 24-pin
CERPACK. Devicesareofferedinbothcommercialand
military temperature ranges.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
SOIC (S4)
DIP (P3-1, C3-1, D3-1)
LCC (L4)
CERPACK (F3) SIMILAR
Document # SRAM101 REV. A
Revised October 2005
1
P4C422
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TBIAS
Temperature Under
Bias
–55 to +125 °C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150 °C
VTERM
TA
V
20
mA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
RECOMMENDED OPERATING CONDITIONS
(2)
Symbol
CIN
Parameter
Conditions Typ. Unit
Grade
Commercial
Military
Ambient Temp
0°C to 70°C
Gnd
Vcc
Input Capacitance VIN = 0V
Output Capacitance VOUT = 0V
5
7
pF
pF
0V 5.0V ±10%
0V 5.0V ±10%
–55°C to 125°C
COUT
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C422
Symbol
Parameter
Test Conditions
Unit
Min
Max
VOH
VOL
VIH
VIL
VCL
IIX
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
IOH = –5.2 mA, VCC = Min.2.4
IOL = +8 mA, VCC = Min.
V
0.4
V
V
2.1
0.8
V
Input Clamp Diode Voltage IIN = –10 mA
–1.5
–10
–10
V
Input Load Current
GND≤ VIN ≤ VCC
OL ≤ VOUT ≤ VOH , Output Disabled
VCC= Max., VOUT = GND
10
10
90
µA
µA
mA
IOZ
IOS
Output Current (High Z)
V
Output Short Circuit
Current(3)
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
-12
-15
-20
-25
-35
Range
-10
ICC
Dynamic Operating Current
Commercial
Military
90
N/A
90
N/A
90
90
90
90
65
90
65
90
mA
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. This parameter is sampled and not 100% tested.
5. Transition time is ≤ 3ns for 10, 12, and 15 ns products and ≤ 5ns for
20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input
and output levels of 1.5V. The output loading is equivalent to the
specified IOL/IOH with a load capacitance of 15 pF (10, 12) or 30 pF (15,
20, 25, 35) as in Fig. 1a and 1b respectively.
6. Transition time is ≤ 3ns for 10, 12, and 15 ns products and ≤ 5ns for
20, 25, and 35 ns products, see Fig 1d. Transition is measured at
steady state HIGH level -500mV or steady state LOW level +500mV
on the output from a level on the input with load shown in Fig. 1c.
7. tW is measured at tWSA = min.; tWSA is measured at tW = min.
Document # SRAM101 REV. A
Page 2 of 10
P4C422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When the chip select
one(CS1)andthewriteenable(WE)areLOWandthechip
select two (CS2) is HIGH, the information on data inputs
(D0 throughD3)iswrittenintotheaddressedmemoryword
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Readingisperformedwithchipselctone (CS1)LOW, chip
select two (CS2) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O0 through O3). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS1) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTH TABLE
Notes:
Mode
CS2 CS1 WE OE
Output
High Z
High Z
High Z
DOUT
H
L
X
= HIGH
= Low
= Don't Care
Standby
Standby
DOUT Disabled
Read
L
X
H
H
H
X
H
L
X
X
X
H
L
X
X
H
L
HIGH Z = Implies outputs are disabled or off. This condition
is defined as high impedance state for the
P4C422.
L
Write
L
X
High Z
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10% except as noted, All Temperature Ranges)(2)
-12
-25
-20
-10*
-15
-35
Max
Parameter
Read Cycle Time (5)
Sym.
tRC
Unit
Max
Max Min Max
Min
Min Max Min Max Min
Min
35
12
12
15
20
25
ns
tACS
Chip Select Time (5)
8
15
12
7.5
8
25 ns
30 ns
Chip Select to High-Z (6)
Output Enable Time
tZRCS
tAOS
tZROS
tAA
8
7.5
8
10
8
12
8
15
12
15
20
20
15
20
25
25
30
ns
ns
Output Enable to High-Z(6)
Address Access Time (5)
10
12
12
15
10
35
ns
*VCC = 5V ± 5%
TIMING WAVEFORM OF READ CYCLE
Document # SRAM101 REV. A
Page 3 of 10
P4C422
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10% except as noted, All Temperature Ranges)(2)
-15
-20
-25
-35
-10*
-12
Parameter
Write Cycle Time(5)
Sym.
Unit
Min
Max Min Max
Max
Min Max
Min
Max
Min Max Min
tWC
tZWS
tWR
10
12
15
25
35
20
ns
ns
Write Enable to High-Z (6)
8
15
12
30
25
10
10
20
20
15
12
Write Recovery Time
8
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width (5,7)
tW
8
0
9
0
11
0
13
2
15
5
20
5
Data Setup Time Prior to Write (5)
Data Hold Time (5)
tWSD
tWHD
tWSA
tWHA
2
0
2
0
2
2
0
4
0
2
5
2
0
2
0
2
5
5
5
5
5
5
Address Setup Time (5,7)
Address Hold Time(5)
2
5
5
5
Chip Select Setup Time (5)
Chip Select Hold Time(5)
2
5
tWSCS
tWHCS
5
5
*VCC = 5V ± 5%
TIMING WAVEFORM OF WRITE CYCLE
Document # SRAM101 REV. A
Page 4 of 10
P4C422
AC TEST LOADS & WAVEFORMS
Figure 1a
Figure 1b
Figure 1d
Figure 1c
Document # SRAM101 REV. A
Page 5 of 10
P4C422
ORDERING INFORMATION
SELECTION GUIDE
The P4C422 is available in the following temperature range, speed, and package options.
Speed (ns)
Temperature
Range
Package
Plastic DIP
10
-10PC
-10SC
N/A
12
-12PC
-12SC
N/A
15
20
25
35
-15PC
-15SC
-20PC
-20SC
-20CM
-20DM
-20LM
-25PC
-25SC
-25CM
-25DM
-25LM
-35PC
-35SC
-35CM
-35DM
-35LM
Commercial
Temperature
SOIC
Side Brazed DIP
CERDIP
-15CM
-15DM
-15LM
N/A
N/A
Military
Temperature
LCC
N/A
N/A
CERPACK
Side Brazed DIP
CERDIP
N/A
N/A
-15FM
-20FM
-20CMB
-20DMB
-20LMB
-20FMB
-25FM
-25CMB
-25DMB
-25LMB
-25FMB
-35FM
-35CMB
-35DMB
-35LMB
-35FMB
N/A
N/A
-15CMB
-15DMB
-15LMB
-15FMB
N/A
N/A
Military
Processed*
LCC
N/A
N/A
CERPACK
N/A
N/A
*Military temperature range with MIL-STD-883, Class B compliance.
N/A = Not Available
Document # SRAM101 REV. A
Page 6 of 10
P4C422
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C3-1
# Pins
22 (400 Mil)
Symbol
Min
-
0.014
0.035
0.008
-
Max
A
b
b2
C
D
E
0.200
0.026
0.060
0.015
1.100
0.410
0.360
eA
e
0.400 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.060
-
-
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D3-1
# Pins
22 (400 Mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.111
0.410
0.350
eA
e
0.400 BSC
0.100 BSC
L
0.125
0.200
0.070
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM101 REV. A
Page 7 of 10
P4C422
CERPACK CERAMIC FLAT PACKAGE
Pkg #
F3
# Pins
24
Symbol
Min
0.060
0.015
0.004
-
Max
A
b
c
D
E
e
0.090
0.022
0.009
0.630
0.380
0.330
0.050 BSC
k
L
Q
S
S1
0.008
0.015
0.370
0.045
0.085
-
0.250
0.026
-
0.005
SQUARE LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L4
24
Min
Max
0.060
0.050
0.022
0.395
0.075
0.065
0.028
0.410
A1
B1
D/E
D1/E1
D2/E2
D3/E3
e
0.250 BSC
0.125 BSC
-
0.410
0.050 BSC
0.040 REF
0.020 REF
h
j
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
6
6
Document # SRAM101 REV. A
Page 8 of 10
P4C422
PLASTIC DUAL IN-LINE PACK-
AGE
Pkg #
P3-1
22 (400 Mil)
# Pins
Symbol
Min
-
Max
0.210
-
0.022
0.065
0.015
1.120
0.390
0.425
A
A1
b
b2
C
D
E1
E
0.015
0.014
0.045
0.009
1.065
0.330
0.390
e
0.100 BSC
eB
L
α
-
0.500
0.160
15°
0.115
0°
SMALL OUTLINE IC PLASTIC PACKAGE
Pkg #
S4
# Pins
24 (300 Mil)
Symbol
Min
Max
A
A1
b2
C
D
e
0.093
0.004
0.013
0.009
0.598
0.104
0.012
0.020
0.012
0.614
0.050 BSC
E
H
h
L
α
0.291
0.394
0.010
0.016
0°
0.299
0.419
0.029
0.050
8°
Document # SRAM101 REV. A
Page 9 of 10
P4C422
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM101
P4C422 HIGH SPEED 256 x 4 Static CMOS RAM
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
OR
A
1997
DAB
New Data Sheet
Oct-05
JDB
Change logo to Pyramid
Document # SRAM101 REV. A
Page 10 of 10
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