PYA28C010-20FSMB [PYRAMID]
Access Times of 120, 150, 200, and 250ns Single 5V±10% Power Supply;
| 型号： | PYA28C010-20FSMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Access Times of 120, 150, 200, and 250ns Single 5V±10% Power Supply |
| 文件： | 总15页 (文件大小：904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PYA28C010
128K x 8 EEPROM
FEATURES
Access Times of 120, 150, 200, and 250ns
Single 5V±10% Power Supply
Software Data Protection
Fully TTL Compatible Inputs and Outputs
Endurance:
- 10,000 Cycles/byte
- 100,000 Cycles/page
Simple Byte and Page Write
Low Power CMOS:
- 60 mA Active Current
- 500 µA Standby Current
Data Retention: 100 Years
Available in the following package:
– 32-Pin 600 mil Ceramic DIP
Fast Write Cycle Times
– 32-Pin Ceramic LCC (450x550 mils)
– 32-Pin Solder Seal Flatpack
– 44-Pin Ceramic LCC (650x650 mils)
DESCRIPTIOꢀ
The PYA28C010 is a 5 Volt 128Kx8 EEPROM using float-
ing gate CMOS Technology. The device supports 64-byte
pagewriteoperation. ThePYA28C010featuresDATAand
Toggle Bit Polling as well as a system software scheme
used to indicate early completion of a Write Cycle. The
devicealsoincludesuser-optionalsoftwaredataprotection.
Data Retention is 100 Years. The device is available in
a 32-Pin 600 mil wide Ceramic DIP, 32-Pin LCC, 32-Pin
Solder Seal Flatpack and 44-Pin Ceramic LCC.
FUꢀCTIOꢀAL BLOCꢁ DIAꢂRAM
PIꢀ COꢀFIꢂURATIOꢀ
DIP (C10)
LCC (L6)
Document # EEPROM103 REV 03
Revised July 2014
PYA28C010 - 128K x 8 EEPROM
OPERATIOꢀ
READ
DATA POLLIꢀꢂ
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning HIGH.
This two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
The PYA28C010 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the PYA28C010, eliminating additional
interrupts or external hardware. During the internal program-
ming cycle, any attempt to read the last byte written will produce
the complement of that data on I/O7 (i.e., write data=0xxx xxxx,
read data=1xxx xxxx). Once the programming cycle is com-
plete, I/O7 will reflect true data. Note: If the PYA28C010 is in
the protected state and an illegal write operation is attempted,
DATA Polling will not operate.
WRITE
Write operations are initiated when both CE and WE are LOW
and OE is HIGH. The PYA28C010 supports both a CE and WE
controlled write cycle. That is, the address is latched by the fall-
ing edge of either CE or WE, whichever occurs last. Similarly,
the data is latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation, once initi-
ated, will automatically continue to completion, typically within
5 ms.
TOꢂꢂLE BIT
The PYA28C010 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle, I/O6 will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the device
will be accessible for addtional read or write operations.
PAꢂE WRITE
The page write feature of the AS28C010 allows the entire
memory to be written in 5 seconds. Page write allows two to
two hundred fifty-six bytes of data to be consecutively written
to the PYA28C010 prior to the commencement of the internal
programming cycle. The host can fetch data from another de-
vice within the system during a page write operation (change the
source address), but the page address (A8 through A16) for each
subsequent valid write cycle to the part during this operation
must be the same as the initial page address.
DATA PROTECTIOꢀ
Pyramid Semiconductor has incorporated both hardware and
software features that will protect the memory against inadver-
tent writes during transitions of the host system power supply.
HARDWARE PROTECTIOꢀ
Hardware features protect against inadvertent writes to the PY-
A28C010 in the following ways: (a) VCC sense - if VCC is below
3.8V (typical) the write function is inhibited; (b) VCC power-on
delay - once VCC has reached 3.8V the device will automatically
time out 5 ms (typical) before allowing a write; (c) write inhibit
- holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
The page write mode can be initiated during any write opera-
tion. Following the initial byte write cycle, the host can write an
additional one to two hundred fifty-six bytes in the same manner
as the first byte was written. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within 100µs, the
internal automatic programming cycle will commence. There
is no page write window limitation. Effectively the page write
window is infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
SOFTWARE DATA PROTECTIOꢀ
A software controlled data protection feature has been imple-
mented on the PYA28C010. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP fea-
ture may be enabled or disabled by the user; the PYA28C010 is
shipped from Pyramid Semiconductor with SDP disabled.
WRITE
The PYA28C010 provides the user two write operation status
bits. These can be used to optimize a system write cycle time.
The status bits are mapped onto the I/O bus as shown below.
SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after
tWC the entire PYA28C010 will be protected against inadvertent
write operations. It should be noted, that once protected the
host may still perform a byte or page write to the PYA28C010.
This is done by preceding the data to be written by the same
3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command
sequence is issued. Power transitions do not disable SDP and
SDP will protect the PYA28C010 during power-up and power-
down conditions. All command sequences must conform to the
page write timing specifications. The data in the enable and
disable command sequences is not written to the device and the
memory addresses used in the sequence may be written with
data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the
Document # EEPROM103 REV 03
Page 2
PYA28C010 - 128K x 8 EEPROM
3-byte command sequence will start the internal write timers.
No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
DEVICE IDEꢀTIFICATIOꢀ
An extra 128-bytes of EEPROM memory are available to the
user for device identification. By raising A9 to 12V ± 0.5V and
using address locations 1FF80H to 1FFFFH the bytes may be
written to or read from in the same manner as the regular mem-
ory array.
OPTIOꢀAL CHIP ERASE MODE
The entire device can be erased using a 6-byte software
code. Please see "Software Chip Erase" application note
at the end of this datasheet for details.
Document # EEPROM103 REV 03
Page 3
PYA28C010 - 128K x 8 EEPROM
MAꢃIMUM RATIꢀꢂS(1)
RECOMMEꢀDED OPERATIꢀꢂ COꢀDITIOꢀS
ꢂrade(2)
Ambient Temp
ꢂꢀD
VCC
Sym Parameter
Value
Unit
Power Supply Pin with
VCC
Military
-55°C to +125°C
0V
5.0V ± 10%
-0.3 to +6.25
V
Respect to GND
Terminal Voltage with
VTERM Respect to GND (up to
6.25V)
-0.5 to +6.25
V
TA
Operating Temperature
-55 to +125
-55 to +125
-65 to +150
1.0
°C
°C
°C
W
CAPACITAꢀCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
TBIAS Temperature Under Bias
TSTG Storage Temperature
Sym Parameter
Conditions Typ Unit
PT
Power Dissipation
CIN
Input Capacitance
VIN = 0V
10
10
pF
pF
IOUT DC Output Current
50
mA
COUT
Output Capacitance
VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
PYA28C010
Sym Parameter
Test Conditions
Unit
Min
2.0
Max
VIH Input High Voltage
VCC + 0.3
0.8
V
V
V
V
V
V
VIL Input Low Voltage
-0.5(3)
VHC CMOS Input High Voltage
VLC CMOS Input Low Voltage
VOL Output Low Voltage (TTL Load)
VOH Output High Voltage (TTL Load)
VCC - 0.2 VCC + 0.5
-0.5(3)
0.2
IOL = +2.1 mA, VCC = Min
IOH = -0.4 mA, VCC = Min
0.45
2.4
-10
VCC = Max
ILI
Input Leakage Current
+10
+10
µA
µA
VIN = GND to VCC
VCC = Max, CE = VIH,
VOUT = GND to VCC
CE ≥ VIH, OE = VIL,
VCC = Max,
-10
—
ILO Output Leakage Current
ISB Standby Power Supply Current (TTL Input Levels)
3
mA
µA
f = Max, Outputs Open
CE ≥ VHC,
VCC = Max,
—
—
ISB1 Standby Power Supply Current (CMOS Input Levels)
300
f = Max, Outputs Open,
VIN ≤ VLC or VIN ≥ VHC
CE = OE = VIL,
WE = VIH,
ICC Supply Current
60
µA
All I/O's = Open,
Inputs = VCC = 5.5V
ꢀotes:
1. Stresses greater than those listed under MAꢀIMꢁM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢀIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3.TransientinputswithVIL andIIL notmorenegativethan-3.0Vand-100mA,
respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
Document # EEPROM103 REV 03
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PYA28C010 - 128K x 8 EEPROM
POWER-UP TIMIꢀꢂ
Symbol
Parameter
Max
100
5
Unit
µs
tPUR
Power-up to Read operation
Power-up to Write operation
tPUW
ms
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-120
-150
-200
-250
Unit
Sym Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tAVAV
Read Cycle Time
120
150
200
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV Address Access Time
120
120
50
150
150
50
200
200
50
250
250
50
tELQV Chip Enable Access Time
tOLQV Output Enable Access Time
tELQꢀ Chip Enable to Output in Low Z
tEHQZ Chip Disable to to Output in High Z
tOLQꢀ Output Enable to Output in Low Z
tOHQZ Output Disable to Output in High Z
tAVQꢀ Output Hold from Address Change
0
0
0
0
0
0
0
0
0
0
0
0
50
50
50
50
50
50
50
50
TIMIꢀꢂ WAVEFORM OF READ CYCLE
Document # EEPROM103 REV 03
Page 5
PYA28C010 - 128K x 8 EEPROM
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-120
-150
-200
-250
Unit
Symbol
Parameter
Min
Max
10
Min
Max
10
Min
Max
10
Min
Max
tWHWL1
tEHEL1
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
OE Setup Time
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
tAVEL
tAVWL
0
50
0
0
50
0
0
50
0
0
50
0
tELAꢀ
tWLAꢀ
tWLEL
tELWL
tWHEH
0
0
0
0
tOHEL
tOHWL
10
10
100
50
0
10
10
100
50
0
10
10
100
50
0
10
10
100
50
0
tWHOL
OE Hold Time
tELEH
tWLWH
WE Pulse Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
CE Setup Time
tDVEH
tDVWH
tEHDꢀ
tWHDꢀ
tEHEL2
tWHWL2
0.2
1
100
0.2
1
100
0.2
1
100
0.2
1
100
tELWL
tOVHWL
tEHWH
tWHOH
Output Setup Time
CE Hold Time
1
1
1
1
1
1
1
1
OE Hold Time
1
1
1
1
Document # EEPROM103 REV 03
Page 6
PYA28C010 - 128K x 8 EEPROM
TIMIꢀꢂ WAVEFORM OF BYTE WRITE CYCLE (CE COꢀTROLLED)
TIMIꢀꢂ WAVEFORM OF BYTE WRITE CYCLE (WE COꢀTROLLED)
Document # EEPROM103 REV 03
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PYA28C010 - 128K x 8 EEPROM
TIMIꢀꢂ WAVEFORM OF PAꢂE WRITE CYCLE
ꢀOTES:
• For each successive write within the page write operation, A8-A16 should be the same. Otherwise, writes to an un-
known address could occur.
• Between successive byte writes within a page write operation, OE can be strobed LOW. For example, this can be
done with CE and WE HIGH to fetch data from another memory device within the system for the next write. Alterna-
tively, this can be done with WE HIGH and CE LOW, effectively performing a polling operation.
• The timings shown above are unique to page write operations. Individual byte load operations within the page write
must conform to either the CE or WE controlled write cycle timing.
Document # EEPROM103 REV 03
Page 8
PYA28C010 - 128K x 8 EEPROM
WRITE SEQUEꢀCE FOR SOFTWARE DATA
PROTECTIOꢀ
SOFTWARE SEQUEꢀCE TO DE-ACTIVATE
SOFTWARE DATA PROTECTIOꢀ
Document # EEPROM103 REV 03
Page 9
PYA28C010 - 128K x 8 EEPROM
AC TEST COꢀDITIOꢀS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
10ns
Mode
CE
OE
L
WE
H
I/O
DOUT
DIN
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
Read
L
L
1.5V
Write
H
L
L
1.5V
Write Inhibit
Write Inhibit
Standby
ꢀ
ꢀ
H
ꢀ
—
See Figure 1
ꢀ
H
—
ꢀ
ꢀ
High Z
Figure 1. Output Load
Document # EEPROM103 REV 03
Page 10
PYA28C010 - 128K x 8 EEPROM
APPLICATIOꢀ ꢀOTE - SOFTWARE CHIP ERASE
The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of
6-byte load commands to specific address locations with specific data patterns. Once the code has been entered, the
device will set each byte to the high state (FFH). After the software chip erase has been initiated, the device will inter-
nally time the erase operation so that no external clocks are required. The maximum time required to erase the whole
chip is tEC (20 ms). The software data protection is still enabled even after the software chip erase is performed.
CHIP ERASE CYCLE CHARACTERISTICS
Symbol Parameter
tEC
Chip Erase Cycle Time
20 ms Max
CHIP ERASE SOFTWARE ALꢂORITHM(1)(3)
ꢀotes:
1. Data Format: (Hex); Address Format: (Hex).
2. Afterloadingthe6-bytecode,nobyteloadsare
alloweduntilthecompletionoftheerasecycle.
The erase cycle will time itself to completion
in 20 ms (max).
3. The flow diagram shown is for a x8 part. For a
x16 part, the data should be 16 bits long (e.g.,
the data to be loaded should beAAAAfor step
1 in the algorithm).
CHIP ERASE CYCLE WAVEFORMS
Document # EEPROM103 REV 03
Page 11
PYA28C010 - 128K x 8 EEPROM
ORDERIꢀꢂ IꢀFORMATIOꢀ
Document # EEPROM103 REV 03
Page 12
PYA28C010 - 128K x 8 EEPROM
SIDE BRAZED DUAL Iꢀ-LIꢀE PACꢁAꢂE (600 mils)
Pkg #
C10
# Pins
32 (600 mil)
Symbol
Min
Max
A
b
-
0.225
0.026
0.065
0.018
1.680
0.620
0.014
0.045
0.008
-
b2
C
D
E
0.510
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.070
S1
S2
-
-
SOLDER SEAL FLAT PACꢁAꢂE
Pkg #
FS-3
# Pins
32
Symbol
Min
0.097
0.015
0.003
-
Max
0.125
0.019
0.009
0.830
0.420
0.450
-
A
b
c
D
E
0.400
-
E1
E2
E3
e
0.180
0.030
-
0.050 BSC
L
0.250
0.370
0.045
0.045
-
Q
S
0.020
-
0.000
-
S1
M
N
0.002
32
Document # EEPROM103 REV 03
Page 13
PYA28C010 - 128K x 8 EEPROM
RECTAꢀꢂULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L6
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
0.045
0.075
L2
ND
NE
7
9
SQUARE LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L14
44
Min
Max
0.070
0.060
0.022
0.640
0.088
0.075
0.028
0.660
A1
B1
D/E
D1/E1
D2/E2
D3/E3
e
0.500 BSC
0.250 BSC
0.662
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.090
L1
0.045
0.080
L2
ND
11
11
NE
Document # EEPROM103 REV 03
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PYA28C010 - 128K x 8 EEPROM
REVISIOꢀS
DOCUMEꢀT ꢀUMBER EEPROM103
DOCUMEꢀT TITLE
PYA28C010 - 128K x 8 EEPROM
REV ISSUE DATE
ORIꢂIꢀATOR DESCRIPTIOꢀ OF CHAꢀꢂE
OR
01
Oct 2009
Jun 2011
Oct 2011
JDB
JDB
JDB
New Data Sheet
Part number corrected throughout from "PYꢀ28C010" to "PYA28C010"
02
Added 32-pin flatpack and 44-pin LCC packages
Document # EEPROM103 REV 03
Page 15
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