PYA28C16 [PYRAMID]
Access Times of 150, 200, 250 and 350ns Single 5V±10% Power Supply;
| 型号： | PYA28C16 |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Access Times of 150, 200, 250 and 350ns Single 5V±10% Power Supply |
| 文件： | 总10页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PYA28C16
2K X 8 EEPROM
FEATURES
Access Times of 150, 200, 250 and 350ns
Single 5V±10% Power Supply
Endurance:
- 10,000 Write Cycles
- 100,000 Write Cycles (optional)
Fast Byte Write (200µs or 1 ms)
Data Retention: 10 Years
Available in the following package:
– 24-Pin 600 mil Ceramic DIP
– 32-Pin Ceramic LCC (450x550 mils)
Low Power CMOS:
- 60 mA Active Current
- 150 µA Standby Current
Fast Write Cycle Time - DATA Polling
CMOS & TTL Compatible Inputs and Outputs
PIN CONFIGURATIONS
DESCRIPTION
ThePYA28C16isa5Volt2Kx8EEPROM. ThePYA28C16
is a 16K memory organized as 2,048 words by 8 bits. Data
Retention is 10 Years. The device is available in a 24-Pin
600 mil wide Ceramic DIP and 32-Pin LCC.
DIP (C12)
FUNCTIONAL BLOCK DIAGRAM
LCC (L6)
Document # EEPROM108 REV A
Revised July 2012
PYA28C16 - 2K x 8 EEPROM
OPERATION
MAXIMUM RATINGS(1)
READ
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE re-
turning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Sym Parameter
Value
Unit
Power Supply Pin with
VCC
-0.3 to +6.25
V
Respect to GND
Terminal Voltage with
VTERM Respect to GND (up to
6.25V)
-0.5 to +6.25
V
BYTE WRITE
TA
Operating Temperature
-55 to +125
-55 to +125
-65 to +150
1.0
°C
°C
°C
W
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The PYA28C16 supports both a
CE and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first. A
byte write operation, once initiated, will automatically con-
tinue to completion.
TBIAS Temperature Under Bias
TSTG Storage Temperature
PT
Power Dissipation
IOUT DC Output Current
50
mA
RECOMMENDED OPERATING CONDITIONS
CHIP CLEAR
Grade(2)
Ambient Temp
GND
VCC
The contents of the entire memory of the PYA28C16 may
be set to the high state by the CHIP CLEAR operation.
By setting CE low and OE to 12 volts, the chip is cleared
when a 10 msec low pulse is applied to WE.
Military
-55°C to +125°C
0V
5.0V ± 10%
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
DEVICE IDENTIFICATION
An extra 32 bytes of EEPROM memory are available to
the user for device identification. By raising A9 to 12 ±
0.5V and using address locations 7E0H to 7FFH the ad-
ditional bytes may be written to or read from in the same
manner as the regular memory array.
Sym Parameter
Conditions Typ Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
10
10
pF
pF
COUT
VOUT = 0V
DATA POLLING
The PYA28C16 features DATA Polling as a method to in-
dicate to the host system that the byte write cycle has
completed. DATA Polling allows a simple bit test opera-
tion to determine the status of the PYA28C16, eliminat-
ing additional interrupts or external hardware. During the
internal programming cycle, any attempt to read the last
byte written will produce the complement of that data on
I/O7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx).
Once the programming cycle is complete, I/O7 will reflect
true data.
Document # EEPROM108 REV A
Page 2
PYA28C16 - 2K x 8 EEPROM
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
PYA28C16
Unit
Sym Parameter
Test Conditions
Min
Max
VCC + 0.3
0.8
VIH Input High Voltage
2.0
V
V
V
V
V
V
VIL Input Low Voltage
-0.5(3)
VHC CMOS Input High Voltage
VLC CMOS Input Low Voltage
VOL Output Low Voltage (TTL Load)
VOH Output High Voltage (TTL Load)
VCC - 0.2 VCC + 0.5
-0.5(3)
0.2
IOL = +2.1 mA, VCC = Min
IOH = -0.4 mA, VCC = Min
0.45
2.4
-10
VCC = Max
ILI
Input Leakage Current
+10
+10
µA
µA
VIN = GND to VCC
VCC = Max, CE = VIH,
VOUT = GND to VCC
CE ≥ VIH, OE = VIL,
VCC = Max,
-10
—
ILO Output Leakage Current
ISB Standby Power Supply Current (TTL Input Levels)
5
mA
µA
f = Max, Outputs Open
CE ≥ VHC,
VCC = Max,
—
—
ISB1 Standby Power Supply Current (CMOS Input Levels)
150
f = 0, Outputs Open,
VIN ≤ VLC or VIN ≥ VHC
CE = OE = VIL,
WE = VIH,
ICC Supply Current
60
mA
All I/O's = Open,
Inputs = VCC = 5.5V
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3.TransientinputswithVIL andIIL notmorenegativethan-3.0Vand-100mA,
respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
Document # EEPROM108 REV A
Page 3
PYA28C16 - 2K x 8 EEPROM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-150
-200
-250
-350
Unit
Sym Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tAVAV
Read Cycle Time
150
200
250
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV Address Access Time
150
150
80
200
200
100
250
250
100
350
350
100
tELQV Chip Enable Access Time
tOLQV Output Enable Access Time
tELQX Chip Enable to Output in Low Z
tEHQZ Chip Disable to to Output in High Z
tOLQX Output Enable to Output in Low Z
tOHQZ Output Disable to Output in High Z
tAVQX Output Hold from Address Change
0
0
0
0
0
0
0
0
0
0
0
0
55
55
60
60
65
65
70
70
TIMING WAVEFORM OF READ CYCLE
Document # EEPROM108 REV A
Page 4
PYA28C16 - 2K x 8 EEPROM
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
150 / 200 / 250 / 350
Symbol
Parameter
Unit
ms
ns
Min
Max
tELRH
tWLRH
Write Cycle Time
Address Setup Time
Address Hold Time
1
tAVEL
tAVWL
10
50
tELAX
tWLAX
ns
tWLEL
Write Setup Time
Write Hold Time
OE Setup Time
0
0
ns
ns
ns
tWHEH
tOHEL
tOHWL
10
tWHOL
tEHOL2
OE Hold Time
10
100
50
ns
ns
ns
ns
tELEH
tWLWH
WE Pulse Width
Data Setup Time
Data Hold Time
1000
tDVEH
tDVWH
tEHDX
tWHDX
10
tELWL
CE Setup Time
CE Hold Time
0
0
ns
ns
tEHWH
tEHRL
tWHRL
Time to device busy
50
ns
Document # EEPROM108 REV A
Page 5
PYA28C16 - 2K x 8 EEPROM
TIMING WAVEFORM OF BYTE WRITE CYCLE (CE CONTROLLED)
TIMING WAVEFORM OF BYTE WRITE CYCLE (WE CONTROLLED)
Document # EEPROM108 REV A
Page 6
PYA28C16 - 2K x 8 EEPROM
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
Mode
GND to 3.0V
10ns
CE
L
OE
L
WE
H
I/O
DOUT
DIN
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
Read
1.5V
Write
L
H
L
L
1.5V
Write Inhibit
Write Inhibit
Standby
X
X
H
X
X
—
See Figure 1
X
H
—
X
X
High Z
High Z
Output Disable
H
X
Figure 1. Output Load
Document # EEPROM108 REV A
Page 7
PYA28C16 - 2K x 8 EEPROM
ORDERING INFORMATION
Document # EEPROM108 REV A
Page 8
PYA28C16 - 2K x 8 EEPROM
SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils)
Pkg #
C12-1
# Pins
24 (600 mil)
Symbol
Min
-
Max
A
b
0.232
0.022
0.065
0.014
1.290
0.610
0.014
0.045
0.008
-
b2
C
D
E
0.500
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.060
S1
S2
-
-
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L6
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
0.045
0.075
L2
ND
NE
7
9
Document # EEPROM108 REV A
Page 9
PYA28C16 - 2K x 8 EEPROM
REVISIONS
DOCUMENT NUMBER EEPROM108
DOCUMENT TITLE
PYA28C16 - 2K x 8 EEPROM
REV ISSUE DATE
ORIGINATOR DESCRIPTION OF CHANGE
OR
A
Jun 2012
Jul 2012
JDB
JDB
New Data Sheet
Tightened package definition for 600-Mil Sidebrazed DIP
Document # EEPROM108 REV A
Page 10
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