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UT9Q512K32 UT9Q512K32 16Megabit SRAM MCM
型号:   UT9Q512K32
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描述:   UT9Q512K32 16Megabit SRAM MCM
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Standard Products
QCOTS
TM
UT9Q512K32 16Megabit SRAM MCM
Data Sheet
June, 2003
FEATURES
q
25ns maximum (5 volt supply) address access time
q
Asynchronous operation for compatible with industry
standard 512K x 8 SRAMs
q
TTL compatible inputs and output levels , three-state
bidirectional data bus
q
Typical radiation performance
- Total dose: 50krads
- SEL Immune >80 MeV-cm
2
/mg
- LET
TH
(0.25) = >10 MeV-cm
2
/mg
- Saturated Cross Section (cm
2
) per bit, 5.0E -9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
q
Packaging options:
- 68-lead dual cavity ceramic quad flatpack (CQFP) -
(weight 7.37 grams)
q
Standard Microcircuit Drawing 5962-01511
- QML T and Q compliant part
INTRODUCTION
The QCOTS
TM
UT9Q512K32 Quantified Commercial
Off-the-Shelf product is a high-performance 2M byte
(16Mbit) CMOS static RAM multi-chip module (MCM),
organized as four individual 524,288 x 8 bit SRAMs with a
common output enable. Memory expansion is provided by
an active LOW chip enable (En), an active LOW output
enable (G), and three-state drivers. This device has a power-
down feature that reduces power consumption by more than
90% when deselected.
Writing to each memory is accomplished by taking chip
enable (En) input LOW and write enable ( Wn) inputs LOW.
Data on the eight I/O pins (DQ
0
through DQ
7
) is then written
into the location specified on the address pins (A
0
through
A
18
). Reading from the device is accomplished by taking
chip enable (En) and output enable ( G) LOW while forcing
write enable (Wn) HIGH. Under these conditions, the
contents of the memory location specified by the address
pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state
when the device is deselected (En HIGH), the outputs are
disabled (G HIGH), or during a write operation (En LOW
and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by
making Wn along with En a common input to any
combination of the discrete memory die.
E3
A(18:0)
G
W3
E2
W2
E1
W1
W0
E0
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
DQ(7:0)
or
DQ0(7:0)
Figure 1. UT9Q512K32 SRAM Block Diagram
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