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ML65F16245CR 16-Bit Bidirectional Transceiver with 3-State Outputs
型号:   ML65F16245CR
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描述:   16-Bit Bidirectional Transceiver with 3-State Outputs
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品牌   MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
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June 1998
PRELIMINARY
ML65F16245*
16-Bit Bidirectional Transceiver with 3-State Outputs
GENERAL DESCRIPTION
The ML65F16245 is a BiCMOS, non-inverting 16-bit
transceiver with 3-state outputs. This device was
specifically designed for high speed bus applications. Its
16 channels support propagation delay of 2ns maximum,
and fast output enable and disable times of 5ns or less to
minimize datapath delay.
This device is designed to minimize undershoot,
overshoot, and ground bounce to decrease noise delays.
These transceivers implement a unique digital and analog
implementation to eliminate the delays and noise
inherent in traditional digital designs. The device offers a
new method for quickly charging up a bus load capacitor
to minimize bus settling times, or FastBus™ Charge.
FastBus Charge is a transition current, (specified as
I
DYNAMIC
) that injects between 60 to 200mA (depending
on output load) of current during the rise time and fall
time. This current is used to reduce the amount of time it
takes to charge up a heavily-capacitive loaded bus,
effectively reducing the bus settling times, and
improving data/clock margins in tight timing budgets.
Micro Linear’s solution is intended for applications for
critical bus timing designs that include minimizing
device propagation delay, bus settling time, and time
delays due to noise. Applications include; high speed
memory arrays, bus or backplane isolation, bus to bus
bridging, and sub-2ns propagation delay schemes.
The ML65F16245 follows the pinout and functionality of
the industry standard 2.7V to 3.6V-logic families.
FEATURES
s
Low propagation delays — 2ns maximum for 3.3V,
2.5ns maximum for 2.7V
Fast output enable/disable times of 5ns maximum
FastBus Charge current to minimize the bus settling
time during active capacitive loading
2.7V to 3.6V a V
CC
supply operation; LV-TTL
compatible input and output levels with 3-state
capability
Industry standard pinout compatible to FCT, ALV, LCX,
LVT, and other low voltage logic families
ESD protection exceeds 2000V
Full output swing for increased noise margin
Undershoot and overshoot protection to 400mV
typically
Low ground bounce design
s
s
s
s
s
s
s
s
*This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
V
CC
OE
AB
Bi
Bi
Ai
DIR
OE
OE
BA
GND
i=0 to 15
1
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