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UT7C139C55WCC 4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag
型号:   UT7C139C55WCC
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描述:   4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag
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Standard Products
UT7C138/139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
FEATURES
q
45ns and 55ns maximum address access time
q
Asynchronous operation for compatibility with industry-
standard 4K x 8/9 dual-port static RAM
q
CMOS compatible inputs, TTL/CMOS compatible output
levels
q
Three-state bidirectional data bus
q
Low operating and standby current
q
Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Memory Cell LET threshold: 85 MeV-cm
2
/mg
q
q
- Latchup immune (LET >100 MeV-cm
2
/mg)
QML Q and QML V compliant part
Packaging options:
- 68-lead Flatpack
- 68-pin PGA
5-volt operation
Standard Microcircuit Drawing 5962-96845
INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiation-
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.
Arbitration schemes are included on the UT7C138/139 to
handle situations when multiple processors access the same
memory location. Two ports provide independent,
asynchronous access for reads and writes to any location in
memory. The UT7C138/139 can be utilized as a stand-alone
32/36-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16/18-bit or wider master/
slave dual-port static RAM. For applications that require
depth expansion, the BUSY pin is open-collector allowing
for wired OR circuit configuration. An M/S pin is provided
for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications,
and status buffering.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable ( OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
R/ W
R
CE
R
OE
R
q
q
R/ W
L
CE
L
OE
L
A
11L
A
10L
I/O
8L
(7C139)
I/O
7L
I/O
0L
BUSY
L
A
9L
ROW
SELECT
MEMORY
ARRAY
ROW
SELECT
A
11R
A
10R
I/O
8R
(7C139)
COL
SEL
COLUMN
I/O
COLUMN
I/O
COL
SEL
I/O
7R
I/O
0R
BUSY
R
A
9R
A
0L
M/S
ARBITRATION
A
0R
Figure 1. Logic Block Diagram
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