电子元器件数据表 IC PDF查询
English 中文版
  品牌   我要上传
型号:  
描述:
P1330-122K  NT90PT16S  PF0006  P1330-332K  P1330-222K  NSD10-12D5  OPA1654  PX0407  P1330-394K  NST200F120-A  
UT54ACTS109 Radiation-Hardened Dual J-K Flip-Flops
型号:   UT54ACTS109
PDF文件: 下载PDF文件   鼠标右键选目标另存为
网页直接浏览   不需安装PDF阅读软件
在线打开PDF文件   需安装PDF阅读软件
描述:   Radiation-Hardened Dual J-K Flip-Flops
文件大小 :   55 K    6 页
Logo:   
品牌   AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
购买 :   
  浏览型号UT54ACTS109的Datasheet PDF文件第2页 浏览型号UT54ACTS109的Datasheet PDF文件第3页 浏览型号UT54ACTS109的Datasheet PDF文件第4页 浏览型号UT54ACTS109的Datasheet PDF文件第5页 浏览型号UT54ACTS109的Datasheet PDF文件第6页  
100%
UT54ACS109/UT54ACTS109
Radiation-Hardened
Dual J-K Flip-Flops
FEATURES
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
PINOUTS
16-Pin DIP
Top View
CLR1
J
K1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K posi-
tive triggered flip-flops. A low level at the preset or clear inputs
sets or resets the outputs regardless of the other input levels.
When preset and clear are inactive (high), data at the J and K
input meeting the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
L
CLK
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
OUTPUT
Q
H
L
H
1
L
Q
L
H
H
1
H
Toggle
No Change
H
L
16-Lead Flatpack
Top View
CLR1
J1
K1
CLK1
PRE1
Q1
Q1
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
LOGIC SYMBOL
PRE1
J1
CLK1
K1
CLR1
PRE2
J2
CLK2
(5)
(2)
(4)
(3)
(1)
(11)
(14)
(12)
(9)
Q2
(10)
Q2
S
J1
C1
K1
R
(6)
Q1
(7)
Q1
No Change
(13)
K2
(15)
CLR2
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for V
OH
if the lows at preset and clear are near V
IL
maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
61
RadHard MSI Logic
首页 - - 友情链接
Copyright© 2001 - 2014 ICPDF All Rights Reserved ICPDF.COM

粤公网安备 44030402000629号


粤ICP备13051289号-7