电子元器件数据表 IC PDF查询
English 中文版
  品牌   我要上传
型号:  
描述:
EXC30HREF  EXC35HRTN  EXC30HRYI  EXC35DRAH  EXC35DREN  M7S35TDJ-R  EXC30HREH  EXC35HREF  M7S38TDJ-R  EXC30HRXF  
ML2652CQ 10Base-T Physical Interface Chip
型号:   ML2652CQ
PDF文件: 下载PDF文件   鼠标右键选目标另存为
网页直接浏览   不需安装PDF阅读软件
在线打开PDF文件   需安装PDF阅读软件
描述:   10Base-T Physical Interface Chip
文件大小 :   289 K    23 页
Logo:   
品牌   MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
购买 :   
  浏览型号ML2652CQ的Datasheet PDF文件第2页 浏览型号ML2652CQ的Datasheet PDF文件第3页 浏览型号ML2652CQ的Datasheet PDF文件第4页 浏览型号ML2652CQ的Datasheet PDF文件第5页 浏览型号ML2652CQ的Datasheet PDF文件第6页 浏览型号ML2652CQ的Datasheet PDF文件第7页 浏览型号ML2652CQ的Datasheet PDF文件第8页 浏览型号ML2652CQ的Datasheet PDF文件第9页  
100%
July 2000
ML2652/ML2653
10Base-T Physical Interface Chip
GENERAL DESCRIPTION
The ML2652, 10BASE-T Physical Interface Chip, is a
complete physical interface for twisted pair and AUI
Ethernet applications. It combines a 10BASE-T MAU,
Manchester Encoder/Decoder, and Twisted Pair Interface
filters in one monolithic IC. A complete DTE interface for
twisted pair Ethernet can be implemented by combining
the ML2652, an Ethernet controller, and transformers.
The ML2652 can automatically select between an AUI and
twisted pair interface based on Link Pulses. Six LED
outputs provide complete status at the physical link. Link
pulse testing can be enabled or disabled through the
LTP
LED Pin.
The unique transmitter design uses a waveform generator
and low pass filter to meet the 10BASE-T transmitter
requirements without the need for an external filter. The
differential current driven output reduces common mode
which in turn results in very low EMI and RFI noise.
The ML2652 and ML2653 (28 pin version) are implemented
in a low power double polysilicon CMOS technology. The
ML2653 does not include the AUI interface.
FEATURES
s
s
s
s
s
s
Complete physical interface solution
Conforms to IEEE 802.3i–1990 (10Base-T)
On-chip transmit and receive filters
Automatic AUI/Twisted Pair selection (ML2652 only)
Power down mode
Pin selectable controller interface-(CS0 – CS2)
Intel 82586, 82596
NSC DP8390
Seeq 8003, 8005
AMD 7990
Automatic polarity correction
Pin selectable receive squelch levels
Status pins for: link detect, receive &
transmit activity, collision, jabber, AUI selection
Single supply 5V ±5%
s
s
s
s
ML2652 BLOCK DIAGRAM
CS0 CS1 CS2 FD V
CC
V
CC
GND
TxC
TxE
TxD
DATA MANCHESTER
ENCODER
ENABLE
COL
LPBK
RxC
RxE
RxD
CLK
ENABLE
CONTROLLER
INTERFACE
COLLISION
GND
JABDIS
JABBER
DETECT
LINK
PULSE
XMT
WAVEFORM
GEN & LPF
COLLISION
DETECT
RECEIVE
LPF
RECEIVER
RSL
DO+
DO–
AUI
CI+
CI–
DI+
DI–
CURRENT
DRIVEN XMT
OUTPUT
DRIVER
RTX
Tx+
Tx–
Rx+
Rx–
DATA MANCHESTER
DECODER
OSC
LEDS
RPOL
AUISEL
XMT
CLS
RCV
LTP
JAB
AUI/TP
1
首页 - - 友情链接
Copyright© 2001 - 2014 ICPDF All Rights Reserved ICPDF.COM

粤公网安备 44030402000629号


粤ICP备13051289号-7