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APL1750 PLL Module
型号:   APL1750
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描述:   PLL Module
文件大小 :   76 K    1 页
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品牌   ASB [ ADVANCED SEMICONDUCTOR BUSINESS INC. ]
购买 :   
   
100%
Plerow
TM
APL1750
PLL Module
Features
·
+2 dBm Output Level at 1750MHz
·
2nd Harmonic : < -20 dBc
·
Spurious Level : < -70 dBc
·
Lock Time : < 10ms
·
30 mA Current Consumption
Description
The plerow
TM
PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides ex-
ceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are avail-
able in a surface-mount type package.
Specifications
Parameter
Frequency Range
Output Power
Supply Voltage
Current Consumption
Channel Step Size
2nd Harmonics
Spurious Level
Lock Time
Reference Frequency
Reference Input Level
Phase Noise
(C / N)
@ 10 kHz
@ 100 kHz
Unit
MHz
dBm
V
mA
kHz
dBc
dBc
ms
MHz
dBm
dBc/Hz
Ω
°C
mm
-40
-5
-80
3
20
0
-103
-120
50
25
SMT, 19.0W×19.0L×5.8H
+85
5
Min.
1700
+0
4.75
Typical
1750
+2
5.00
23
100
-20
-70
10
Max.
1800
+4
5.25
30
Website: www.asb.co.kr
E-mail: sales@asb.co.kr
Tel: (82) 42-528-7223
Fax: (82) 42-528-7222
ASB Inc., 4th Fl. Venture Town
Bldg., 367-17 Goijeong-Dong,
Seo-Gu, Daejon 302-716, Korea
More Information
Output Impedance
Operating Temp. Range
Package Type & Size
1) Measurement conditions are as follows: T = 25°C, V
CC
= 5.0 V, Freq. = 1750MHz, 50 ohm system.
Outline Drawing
Top View
Bottom View
Pin Configuration
Dimension (mm)
A
19.0
B
19.0
C
5.8
D
1.5
E
0.5
F
1.75
G
1.35
H
15.0
I
0.9
Tolerance:
±
0.2
D
A
E
F
I
C
B
Side View
H
G
1
2
3
4
9
13
15
16
Others
CLOCK
DATA
ENABLE
OSC IN
VCC (VCO)
RF OUT
VCP (PLL)
LOCK DETECT
Ground
1/1
www.asb.co.kr
11/13/2006
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