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APL1983 PLL Module
型号:   APL1983
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描述:   PLL Module
文件大小 :   137 K    1 页
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品牌   ASB [ ADVANCED SEMICONDUCTOR BUSINESS INC. ]
购买 :   
   
100%
Plerow APL1983
PLL Module
Features
·
+2 dBm Output Level at 1983 MHz
·
Channel Step Size : 25 kHz
·
2
nd
Description
The plerow
TM
PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides ex-
ceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are avail-
able in a surface-mount type package.
Harmonic : < -25 dBc
·
Spurious Level : < -70 dBc
·
Lock Time : < 10 ms
·
35 mA Current Consumption
Specifications
Parameter
Frequency Range
Output Power
Supply Voltage
Current Consumption
Channel Step Size
2 Harmonics
Spurious Level
Lock Time
Reference Frequency
Reference Input Level
Phase Noise (C / N)
@ 1 kHz
@ 10 kHz
@ 100 kHz
Output Impedance
Operating Temp. Range
Package Type & Size
°C
mm
-40
dBc/Hz
-80
-103
-120
50
25
SMT, 19.0W×19.0L×5.8H
85
-70
-93
-110
nd
Unit
MHz
dBm
V
mA
kHz
dBc
dBc
ms
MHz
dBm
Min.
1947
0
4.75
Typical
1983
2
5.0
35
25
-25
-70
10
Max.
2019
4
5.25
45
-20
-60
10
Website: www.asb.co.kr
E-mail: sales@asb.co.kr
Tel: (82) 42-528-7220
Fax: (82) 42-528-7222
ASB Inc., 4th Fl. Venture Town
Bldg., 367-17 Goijeong-Dong,
Seo-Gu, Daejon 302-716, Korea
More Information
-5
0
5
1) Measurement conditions are as follows: T = 25°C, V
CC
= 5 V, Freq. = 1983 MHz, 50 ohm system.
Outline Drawing
Top View
Bottom View
Pin Configuration
Dimension (mm)
A
19.0
B
19.0
C
5.8
D
1.5
E
0.5
F
1.75
G
1.35
H
15.0
I
0.9
Tolerance:
±
0.2
D
A
E
F
I
C
B
Side View
1/1
www.asb.co.kr
H
G
1
2
3
4
9
13
15
16
Others
CLOCK
DATA
ENABLE
OSC IN
VCC (VCO)
RF OUT
VCP (PLL)
LOCK DETECT
Ground
March 2004
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