HYB18T1G160BC-2.5 [QIMONDA]
1-Gbit Double-Data-Rate-Two SDRAM; 1千兆位双数据速率- SDRAM双
| 型号： | HYB18T1G160BC-2.5 |
| 厂家： | 
QIMONDA AG |
| 描述： | 1-Gbit Double-Data-Rate-Two SDRAM |
| 文件： | 总74页 (文件大小：4044K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2007
HY[B/I]18T1G400B[F/C](L)
HY[B/I]18T1G800B[F/C](L)
HY[B/I]18T1G16[0/7]B[F/C](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.3
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
HY[B/I]18T1G400B[F/C](L), HY[B/I]18T1G16[0/7]B[F/C](L/V), HY[B/I]18T1G800B[F/C](L)
Revision History: 2007-07, Rev. 1.3
Page
Subjects (major changes since last revision)
All
Adapted internet edition
Added PG-TFBGA-92
HYB18T1G167BF-3.7, HYB18T1G167BF-3S, HYB18T1G167BF-3, HYB18T1G167BF-2.5,
HYB18T1G167BF-25F, HYB18T1G160BFV-3.7, HYB18T1G160BFV-3S
Previous Revision: 2007-05, Rev. 1.2
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21
03062006-ZNH8-HURV
2
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 1-Gbit Double-data-Rate SDRAM offers the following key features:
•
1.8 V ± 0.1 V Power Supply
•
Off-Chip-Driver impedance adjustment (OCD) and On-
Die-Termination (ODT) for better signal quality
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving Power-
Down modes
Average Refresh Period 7.8 µs at a TCASE lower than
85 °C, 3.9 µs between 85 °C and 95 °C
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
1.8 V ± 0.1 V (SSTL_18) compatible I/O
DRAM organizations with 4, 8 and 16 data in/outputs
Double Data Rate architecture: two data transfers per
clock cycle four internal banks for concurrent operation
Programmable CAS Latency: 3, 4, 5 and 6
Programmable Burst Length: 4 and 8
•
•
•
•
•
•
•
•
•
Differential clock inputs (CK and CK)
•
•
•
•
•
•
Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for better
command and data bus efficiency
Full and reduced Strength Data-Output Drivers
1K page size for ×4 & ×8, 2K page size for ×16
Package: P(G)-TFBGA-68 , P(G)-TFBGA-84
and PG-TFBGA-92
•
•
•
•
•
RoHS Compliant Products1)
All Speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
•
•
TABLE 1
Performance Tables for –2.5(F)
Product Type Speed Code
Speed Grade
–2.5F
–2.5
Unit
DDR2–800D 5–5–5
DDR2–800E 6–6–6
—
Max. Clock Frequency
@CL6 fCK6 400
@CL5 fCK5 400
400
333
266
200
15
MHz
MHz
MHz
MHz
ns
@CL4 fCK4 266
@CL3 fCK3 200
tRCD 12.5
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
tRP 12.5
15
ns
tRAS 45
45
ns
tRC 57.5
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.3, 2007-07
3
03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 2
Performance Table for –3(S)
Product Type Speed Code
Speed Grade
–3
–3S
Unit
DDR2–667C 4–4–4
DDR2–667D 5–5–5
—
Max. Clock Frequency
@CL5 fCK5 333
@CL4 fCK4 333
333
266
200
15
MHz
MHz
MHz
ns
@CL3 fCK3 200
tRCD 12
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
tRP 12
15
ns
tRAS 45
45
ns
tRC 57
60
ns
TABLE 3
Performance table for –3.7
Product Type Speed Code
–3.7
Unit
Speed Grade
DDR2–533C 4–4–4
—
Max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
tRCD
tRP
266
266
200
15
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
ns
tRAS
tRC
45
ns
60
ns
TABLE 4
Performance Table for –5
Product Type Speed Code
–5
Units
Speed Grade
DDR2–400B 3–3–3
—
Max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
tRCD
tRP
200
200
200
15
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
ns
tRAS
tRC
40
ns
55
ns
Rev. 1.3, 2007-07
4
03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
1.2
Description
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device, containing
1,073,741,824 bits and internally configured as anoctal
quadbank DRAM. The 1-Gbit device is organized as either
32 Mbit ×4 I/O ×8 banks, 16 Mbit ×8 I/O ×8 banks or 8 Mbit
×16 I/O ×8 banks chip. These devices achieve high speed
transfer rates starting at 400 Mb/sec/pin for general
applications.
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17-bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The device is designed to comply with all DDR2 SDRAM key
features:
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
3. Normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
The DDR2 SDRAM is available in P(G)-TFBGA-68 and P(G)-
TFBGA-84 packages.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
TABLE 5
Ordering Information for Lead-Free Products (RoHS Compliant)
Product Type
Org. Speed
CAS-RCD-RP Latencies1)2)3) Clock (MHz) Package
Note
Standard Temperature Range (0 °C - +70 °C)
4)
HYB18T1G400BF-2.5F
HYB18T1G800BF-2.5F
HYB18T1G160BF-2.5F
HYB18T1G167BF-2.5F
HYB18T1G400BF-2.5
HYB18T1G800BF-2.5
HYB18T1G160BF-2.5
HYB18T1G167BF-2.5
HYB18T1G400BF-3
HYB18T1G800BF-3
HYB18T1G160BF-3
HYB18T1G167BF-3
HYB18T1G400BF-3S
HYB18T1G400BFL-3S
HYB18T1G800BF-3S
HYB18T1G800BFL-3S
HYB18T1G160BF-3S
HYB18T1G160BFL-3S
HYB18T1G160BFV-3S
HYB18T1G167BF-3S
×4
DDR2-800D 5-5-5
400
400
333
333
PG-TFBGA-68
×8
×16
×16
×4
PG-TFBGA-84
PG-TFBGA-92
PG-TFBGA-68
DDR2-800E 6-6-6
DDR2-667C 4-4-4
DDR2-667D 5-5-5
×8
×16
×16
×4
PG-TFBGA-84
PG-TFBGA-92
PG-TFBGA-68
×8
×16
×16
×4
PG-TFBGA-84
PG-TFBGA-92
PG-TFBGA-68
×4
×8
×8
×16
×16
×16
×16
PG-TFBGA-84
PG-TFBGA-92
Rev. 1.3, 2007-07
5
03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Product Type
Org. Speed
CAS-RCD-RP Latencies1)2)3) Clock (MHz) Package
Note
HYB18T1G400BF-3.7
HYB18T1G400BFL-3.7
HYB18T1G800BF-3.7
HYB18T1G800BFL-3.7
HYB18T1G160BF-3.7
HYB18T1G160BFL-3.7
HYB18T1G160BFV-3.7
HYB18T1G167BF-3.7
HYB18T1G400BF-5
HYB18T1G400BFL-5
HYB18T1G800BF-5
HYB18T1G800BFL-5
HYB18T1G160BF-5
HYB18T1G160BFL-5
×4
DDR2-533C 4-4-4
266
PG-TFBGA-68
×4
×8
×8
×16
×16
×16
×16
×4
PG-TFBGA-84
PG-TFBGA-92
PG-TFBGA-68
DDR2-400B 3-3-3
200
×4
×8
×8
×16
×16
PG-TFBGA-84
PG-TFBGA-68
Industrial Temperature Range (–40 °C - +85 °C)
4)
HYI18T1G400BF-2.5F
HYI18T1G800BF-2.5F
HYI18T1G160BF-2.5F
HYI18T1G400BF-2.5
HYI18T1G800BF-2.5
HYI18T1G160BF-2.5
HYI18T1G400BF-3
HYI18T1G800BF-3
HYI18T1G160BF-3
HYI18T1G400BF-3S
HYI18T1G800BF-3S
HYI18T1G160BF-3S
HYI18T1G400BF-3.7
HYI18T1G800BF-3.7
HYI18T1G160BF-3.7
HYI18T1G400BF-5
HYI18T1G800BF-5
HYI18T1G160BF-5
×4
DDR2-800D 5-5-5
DDR2-800E 6-6-6
DDR2-667C 4-4-4
DDR2-667D 5-5-5
DDR2-533C 4-4-4
DDR2-400B 3-3-3
400
400
333
333
266
200
×8
×16
×4
PG-TFBGA-84
PG-TFBGA-68
×8
×16
×4
PG-TFBGA-84
PG-TFBGA-68
×8
×16
×4
PG-TFBGA-84
PG-TFBGA-68
×8
×16
×4
PG-TFBGA-84
PG-TFBGA-68
×8
×16
×4
PG-TFBGA-84
PG-TFBGA-68
×8
×16
PG-TFBGA-84
1) CAS: Column Address Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
4) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.3, 2007-07
6
03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 6
Ordering Information for Lead-Containing Products
Product Type
Org. Speed
CAS-RCD-RP Latencies1)2)3)
Clock (MHz)
Package
Standard Temperature Range (0 °C - +70 °C)
HYB18T1G400BC-2.5F
HYB18T1G800BC-2.5F
HYB18T1G160BC-2.5F
HYB18T1G400BC-2.5
HYB18T1G800BC-2.5
HYB18T1G160BC-2.5
HYB18T1G400BC-3
HYB18T1G800BC-3
HYB18T1G160BC-3
HYB18T1G400BC-3S
HYB18T1G800BC-3S
HYB18T1G160BC-3S
HYB18T1G400BC-3.7
HYB18T1G800BC-3.7
HYB18T1G160BC-3.7
HYB18T1G400BC-5
HYB18T1G800BC-5
HYB18T1G160BC-5
×4
DDR2-800D 5-5-5
400
P-TFBGA-68
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
DDR2-800E
6-6-6
400
333
333
266
200
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
DDR2-667C 4-4-4
DDR2-667D 5-5-5
DDR2-533C 4-4-4
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
DDR2-400B
3-3-3
×8
×16
P-TFBGA-84
P-TFBGA-68
Industrial Temperature Range (–40 °C - +85 °C)
HYI18T1G400BC-2.5F
HYI18T1G800BC-2.5F
HYI18T1G160BC-2.5F
HYI18T1G400BC-2.5
HYI18T1G800BC-2.5
HYI18T1G160BC-2.5
HYI18T1G400BC-3
HYI18T1G800BC-3
HYI18T1G160BC-3
HYI18T1G400BC-3S
HYI18T1G800BC-3S
HYI18T1G160BC-3S
HYI18T1G400BC-3.7
HYI18T1G800BC-3.7
HYI18T1G160BC-3.7
HYI18T1G400BC-5
HYI18T1G800BC-5
HYI18T1G160BC-5
×4
DDR2-800D 5-5-5
400
400
333
333
266
200
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
DDR2-800E
6-6-6
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
DDR2-667C 4-4-4
DDR2-667D 5-5-5
DDR2-533C 4-4-4
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
×8
×16
×4
P-TFBGA-84
P-TFBGA-68
DDR2-400B
3-3-3
×8
×16
P-TFBGA-84
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
1) CAS: Column Address Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
Note: For product nomenclature see Chapter 9 of this data sheet
Rev. 1.3, 2007-07
8
03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration and addressing.
2.1
Chip Configuration for PG-TFBGA-68
The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 8 and Table 9 respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 7
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×4×8 Organizations
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×4×8 Organizations
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×4×8 Organizations
L2
L3
L1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Bank Address Bus 2
Note: 1 Gbit components and higher
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
P7
R2
R8
Address Signal 13
Note: 1 Gbit ×4/×8 components
Data Signals ×4×8 Organizations
G8
G2
H7
H3
H1
H9
F1
F9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 3:0
Note: Bi-directional data bus.
DQ[3:0] for ×4 components
DQ[7:0] for ×8 components
Data Signal 7:4
Data Strobe ×4×8 Organizations
F7
E8
DQS
DQS
I/O
I/O
SSTL
SSTL
Data Strobe
Data Strobe ×8 Organizations
F3
E2
RDQS
RDQS
O
O
SSTL
SSTL
Read Data Strobe
Data Mask ×4×8 Organizations
F3 DM
Power Supplies ×4×8 Organizations
I
SSTL
—
Data Mask
E9, G1, G3, G7, VDDQ
PWR
I/O Driver Power Supply
G9
E1, J9, M9, R1 VDD
PWR
PWR
—
—
Power Supply
E7, F2, F8, H2, VSSQ
I/O Driver Power Supply
H8
E3, J3, N1, P9 VSS
PWR
Al
—
—
Power Supply
J2
VREF
I/O Reference Voltage
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
J1
J7
VDDL
PWR
PWR
—
—
Power Supply
Power Supply
VSSDL
Not Connected ×4 Organizations
A1, A2, A8, A9, NC
E2, F9, H1,F1,
R7, H9, W1,
W2, W8, W9,
R3
NC
—
Not Connected
Not Connected ×8 Organization
A1, A2, A8, A9, NC
R7, W1, W2,
NC
—
Not Connected
W8, W9, R3
Other Balls ×4×8 Organizations
K9
ODT
I
SSTL
On-Die Termination Control
TABLE 8
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 9
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 1
Ball Configuration for ×4 components, PG-TFBGA-68 (top view)
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Note: VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS and
SSQ are isolated on the device.
V
Rev. 1.3, 2007-07
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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 2
Ball Configuration for ×8 components, PG-TFBGA-68 (top view)
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Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. VDDL and VSSDL are power and ground for the DLL. They are connected on the device from VDD, VDDQ, VSS and VSSQ
.
Rev. 1.3, 2007-07
13
03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2.2
Chip Configuration for PG-TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 10. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 11 and Table 12 respectively.
TABLE 10
Chip Configuration of DDR SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×16 Organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×16 Organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
L2
BA0
BA1
BA2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Note: 1 Gbit components and higher
L3
L1
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Data Signals ×16 Organization
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for ×16 components
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Data Strobe ×16 Organization
B7
A8
F7
E8
UDQS
UDQS
LDQS
LDQS
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×16 Organization
B3
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
Power Supplies ×16 Organization
J2
VREF
AI
—
—
I/O Reference Voltage
C1, C3, C7, C9, VDDQ
E9, G1, G3, G7,
G9, A9
PWR
I/O Driver Power Supply
J1
VDDL
PWR
PWR
—
—
Power Supply
Power Supply
A1, E1, J9, M9, VDD
R1
A7, D2, D8, E7, VSSQ
PWR
—
Power Supply
F2, F8, H2, H8
J7
VSSDL
PWR
PWR
—
—
Power Supply
Power Supply
A3, E3, J3, N1, VSS
P9
Not Connected ×16 Organization
A2, E2, R3, R7, NC
R8
NC
—
Not Connected
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Other Balls ×16 Organization
K9
ODT
I
SSTL
On-Die Termination Control
TABLE 11
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 12
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 3
Chip Configuration for x16 Components in PG–TFBGA–84 (Top view)
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Rev. 1.3, 2007-07
03062006-ZNH8-HURV
17
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2.3
Chip Configuration for PG-TFBGA-92
The chip configuration of a DDR2 SDRAM is listed by function in Table 13. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 14 and Table 15 respectively.
TABLE 13
Chip Configuration of DDR SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×16 Organization
M8
N8
N2
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
CK
CKE
Control Signals ×16 Organization
N7
P7
N3
P8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
P2
P3
P1
R8
R3
R7
T2
T8
T3
T7
U2
U8
U3
R2
BA0
BA1
BA2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Note: 1 Gbit components and higher
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
U7
V2
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1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Data Signals ×16 Organization
K8
K2
L7
L3
L1
L9
J1
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0] for ×16 components
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
J9
DQ7
F8
F2
G7
G3
G1
G9
E1
E9
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Data Strobe ×16 Organization
E7
D8
J7
UDQS
UDQS
LDQS
LDQS
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
H8
Data Mask ×16 Organization
E3
J3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
Power Supplies ×16 Organization
M2
VREF
AI
—
—
I/O Reference Voltage
F1, F3, F7, F9, VDDQ
H9, K1, K3, K7,
K9, D9
PWR
I/O Driver Power Supply
M1
VDDL
PWR
PWR
—
—
Power Supply
Power Supply
D1, H1, M9, R9, VDD
V1
D7, E2, E8, H7, VSSQ
G2, G8, J2, J8,
L2, L8
PWR
—
Power Supply
M7
VSSDL
PWR
PWR
—
—
Power Supply
Power Supply
D3, H3, M3, T1, VSS
U9
Rev. 1.3, 2007-07
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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Not Connected ×16 Organization
A1, A2, A8, A9, NC
D2, V3, V7, V8,
AA1, AA2, AA8,
AA9
NC
—
Not Connected
Other Balls ×16 Organization
N9
ODT
I
SSTL
On-Die Termination Control
TABLE 14
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 15
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2.4
1-Gbit DDR2 Addressing
This chapter describes the 1-Gbit DDR2 addressing.
TABLE 16
DDR2 Addressing for ×4 Organization
Configuration
256Mb x 41)
Note
Bank Address
BA[2:0]
8
Number of Banks
Auto-Precharge
A10 / AP
A[13:0]
A11, A[9:0]
11
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
4
Page Size [Bytes]
1024 (1K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
TABLE 17
DDR2 Addressing for ×8 Organization
Configuration
128Mb x 81)
Note
Bank Address
BA[2:0]
8
Number of Banks
Auto-Precharge
A10 / AP
A[13:0]
A[9:0]
10
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
8
Page Size [Bytes]
1024 (1K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
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1-Gbit Double-Data-Rate-Two SDRAM
TABLE 18
DDR2 Addressing for ×16 Organization
Configuration
64Mb x 161)
Note
Bank Address
BA[2:0]
8
Number of Banks
Auto-Precharge
A10 / AP
A[12:0]
A[9:0]
10
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
16
Page Size [Bytes]
2048 (2K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
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1-Gbit Double-Data-Rate-Two SDRAM
3
Functional Description
This chapter contains the functional description.
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TABLE 19
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address [1]
BA1
BA0
A13
15
14
13
0B
BA1 Bank Address
Bank Address [0]
0B
BA0 Bank Address
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13 Address bit 13
PD
12
w
w
Active Power-Down Mode Select
0B
1B
PD Fast exit
PD Slow exit
WR
[11:9]
Write Recovery2)
Note: All other bit combinations are illegal.
001B WR 2
010B WR 3
011B WR 4
100B WR 5
101B WR 6
DLL
TM
8
7
w
w
DLL Reset
0B
1B
DLL No
DLL Yes
Test Mode
0B
1B
TM Normal Mode
TM Vendor specific test mode
Rev. 1.3, 2007-07
23
03062006-ZNH8-HURV
U
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G
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Zꢋ
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3
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ꢀꢋ
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
011B CL 3
100B CL 4
101B CL 5
110B CL 6
111B CL 7
BT
BL
3
w
w
Burst Type
0B
1B
BT Sequential
BT Interleaved
[2:0]
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN
.
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$
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$
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$
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$
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$
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$
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$
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$
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TABLE 20
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address [1]
BA2
16
reg. addr.
BA1
BA0
A13
15
14
13
0B
BA1 Bank Address
Bank Address [0]
1B
BA0 Bank Address
w
w
Address Bus [13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13 Address bit 13
Qoff
12
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
RDQS
11
w
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS Disable
RDQS Enable
DQS
10
w
w
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
OCD
[9:7]
Off-Chip Driver Calibration Program
Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
w
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
RTT
6,2
w
Nominal Termination Resistance of ODT
Note: See Table 31 “ODT DC Electrical Characteristics” on Page 33
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
w
w
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
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TABLE 21
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field Bits
Type1)
Description
BA2
16
w
Bank Address
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA
[15:14]
w
Bank Adress
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
[13:8]
7
w
w
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
000000B A Address bits
SRF
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:4]
3
w
w
Address Bus
000B A Address bits
DCC
Address Bus, Duty Cycle Correction (DCC)
0B
1B
A3 DCC disabled
A3 DCC enabled
Partial Self Refresh for 4 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 4 Banks3)
Note: Only for 256 Mbit and 512 Mbit components
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
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1-Gbit Double-Data-Rate-Two SDRAM
Field Bits
Type1)
Description
Partial Self Refresh for 8 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 8 Banks3)
Note: Only for 1G and 2G components
000B PASR0 Full Array
001B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)
010B PASR2 Quarter Array (BA[2:0]=000, 001)
011B PASR3 1/8 array (BA[2:0] = 000)
100B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)
101B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)
110B PASR6 Quarter array (BA[2:0]= 110 & 111)
111B PASR7 1/8 array(BA[2:0]=111)
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
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TABLE 22
EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA1
BA0
A
15
Bank Adress[1]
1B
BA1 Bank Address
14
Bank Adress[0]
1B
BA0 Bank Address
[13:0]
w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
00000000000000BA[13:0] Address bits
1) w = write only
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TABLE 23
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
×4 Components
DQ[3:0]
DQS
X
X
0
DQS
X
DM
X
×8 Components
DQ[7:0]
DQS
X
X
0
DQS
X
1
1
0
RDQS
X
0
RDQS
DM
X
×16 Components
DQ[7:0]
DQ[15:8]
LDQS
X
X
X
0
LDQS
X
X
UDQS
X
0
UDQS
LDM
X
X
UDM
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
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TABLE 24
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
× 0 0
× 0 1
×1 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
×1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
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4
Truth Tables
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two
SDRAM.
TABLE 25
Command Truth Table
Function
CKE
CS RAS CAS WE BA0 A[13:11] A10 A[9:0]
Note1)2)3)
BA1
BA2
Previous Current
Cycle
Cycle
4)5)
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
4)
Auto-Refresh
H
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
4)6)
4)6)7)
Self-Refresh Entry
Self-Refresh Exit
L
L
H
X
H
L
X
H
H
H
H
L
4)5)
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
BA
X
X
X
L
X
X
4)
L
L
H
4)5)
L
H
L
BA
BA
BA
Row Address
4)5)8)
4)5)8)
Write
H
H
Column
Column
L
Column
Column
Write with Auto-
Precharge
L
L
H
4)5)8)
4)5)8)
Read
H
H
H
H
L
L
H
H
L
L
H
H
BA
BA
Column
Column
L
Column
Column
Read with Auto-
Precharge
H
4)
No Operation
H
H
H
X
X
L
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
4)
Device Deselect
Power Down Entry
H
H
L
4)9)
4)9)
Power Down Exit
L
H
H
L
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[2:0] determine which bank is to be operated upon. For (E)MRS BA[2:0] selects an (Extended) Mode Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
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TABLE 26
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE
Previous Cycle6)
Command (N)2) 3)
RAS, CAS, WE
Action (N)2)
Note4)5)
Current Cycle6)
(N)
(N-1)
7)8)11)
Power-Down
Self Refresh
L
L
L
H
L
X
Maintain Power-Down
Power-Down Exit
7)9)10)11)
8)11)12)
DESELECT or NOP
X
L
Maintain Self Refresh
Self Refresh Exit
9)11)12)13)14)
7)9)10)11)15)
9)10)11)15)
L
H
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
Bank(s) Active
All Banks Idle
H
H
Active Power-Down Entry
L
Precharge Power-Down
Entry
7)11)14)16)
17)
H
H
L
AUTOREFRESH
Self Refresh Entry
Any State other
than
H
Refer to the Command Truth Table
listed above
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 × tCK + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
TABLE 27
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
X
1)
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
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5
Electrical Characteristics
This chapter describes the electrical characteristics.
5.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 28 at any time.
5.1.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 28 at any time.
TABLE 28
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
–1.0
–0.5
–0.5
–0.5
–55
+2.3
+2.3
+2.3
+2.3
+100
V
1)2)
1)2)
1)
VDDQ
VDDL
V
V
VIN, VOUT
TSTG
V
1)2)
°C
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 29
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
TOPER
Operating Temperature
0
95
85
°C
°C
1)2)3)4) for HYB...
for HYI...
–40
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
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5.2
DC Characteristics
Input and output 0s are higher with dual-die components compared to standard single-die components, due to the double
loading of the input / output pins, except CS[1:0], CKE[1:0] and ODT[1:0] and the additional package internal wiring.
TABLE 30
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating
Min.
Unit
Note
Typ.
Max.
1)
VDD
Supply Voltage
1.7
1.8
1.9
V
V
V
V
V
1)
VDDDL
VDDQ
VREF
VTT
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
1)
1.7
1.8
1.9
2)3)
4)
0.49 × VDDQ
0.5 × VDDQ
VREF
0.51 × VDDQ
V
REF – 0.04
VREF + 0.04
1)
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
3) Peak to peak ac noise on VREF may not exceed ± 2 % VREF (dc)
.
4)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF
.
TABLE 31
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
1)
2)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
Rtt3(eff)
delta VM
120
40
150
50
180
Ω
Ω
%
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
60
Deviation of VM with respect to VDDQ / 2
–6.00
—
+ 6.00
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
1) x 100 %
TABLE 32
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Note
1)
IIL
Input Leakage Current; any input 0 V < VIN < VDD
Output Leakage Current; 0 V < VOUT < VDDQ
–2
–5
+2
+5
µA
µA
2)
IOL
1) All other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
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5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
relative to the rising or falling edges of DQS crossing at VREF
.
TABLE 33
DC & AC Logic Input Levels for DDR2-667 and DDR2-800
Symbol
Parameter
DDR2-667, DDR2-800
Units
Min.
Max.
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
V
REF + 0.125
V
V
DDQ + 0.3
REF – 0.125
V
V
V
V
–0.3
AC input logic high
AC input low
V
REF + 0.200
—
—
VREF – 0.200
TABLE 34
DC & AC Logic Input Levels for DDR2-533 and DDR2-400
Symbol
Parameter
DDR2-533, DDR2-400
Units
Min.
Max.
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
V
REF + 0.125
V
V
DDQ + 0.3
REF - 0.125
V
V
V
V
–0.3
AC input logic high
AC input low
V
REF + 0.250
—
—
VREF - 0.250
TABLE 35
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Note
1)
VREF
Input reference voltage
0.5 x VDDQ
1.0
V
1)
VSWING.MAX
SLEW
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
V
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to
IL(ac).MAX for falling edges as shown in Figure 4
V
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
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FIGURE 4
Single-ended AC Input Test Conditions Diagram
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TABLE 36
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
Max.
Unit
Note
1)
2)
3)
4)
5)
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
DC input signal voltage
–0.3
V
V
V
DDQ + 0.3
—
—
V
DC differential input voltage
AC differential input voltage
AC differential cross point input voltage
0.25
DDQ + 0.6
DDQ + 0.6
0.5
0.5 × VDDQ – 0.175
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
AC differential cross point output voltage 0.5 × VDDQ – 0.125
V
1)
2)
3)
V
V
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
.
.
4) The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
Rev. 1.3, 2007-07
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03062006-ZNH8-HURV
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FIGURE 5
Differential DC and AC Input and Output Logic Levels Diagram
9
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5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 37
SSTL_18 Output DC Current Drive
Symbol
Parameter
SSTL_18
Unit
Note
1)2)
IOH
IOL
Output Minimum Source DC Current
Output Minimum Sink DC Current
–13.4
13.4
mA
mA
2)3)
1)
VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ – 280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN
plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
.
3)
VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
TABLE 38
SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18
Unit
Note
1)
VOH
VOL
Minimum Required Output Pull-up
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
V
V
V
1)
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
VOTR
1) SSTL_18 test load for VOH and VOL is different from the referenced load described. The SSTL_18 test load has a 20 Ohm series resistor
additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be developed across the
effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a
minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA × 45 Ohm = 603 mV).
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TABLE 39
OCD Default Characteristics
Symbol
Description
Min.
Nominal
Max.
Unit
Note
1)2)
—
—
—
Output Impedance
—
0
Ω
Ω
Ω
1)2)3)
4)
Pull-up / Pull down mismatch
—
—
4
Output Impedance step size
for OCD calibration
0
1.5
1)5)6)7)
SOUT
Output Slew Rate
1.5
—
5.0
V / ns
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than
23.4 Ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current:
VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 Ohms at nominal conditions across all process parameters and represents only
the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS
specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
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5.5
Input / Output Capacitance
This chapter contains the input / output capacitance.
TABLE 40
Input / Output Capacitance for DDR2-800
Symbol
Parameter
DDR2-800
Min.
Max.
Unit
CCK
CDCK
CI
Input capacitance, CK and CK
1.0
—
2.0
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
0.25
1.75
0.25
3.5
1.0
—
CDI
CIO
Input/output capacitance,
2.5
DQ, DM, DQS, DQS, RDQS, RDQS
CDIO
Input/output capacitance delta,
—
0.5
pF
DQ, DM, DQS, DQS, RDQS, RDQS
TABLE 41
Input / Output Capacitance for DDR2-667
Symbol
Parameter
DDR2-667
Min.
Max.
Unit
CCK
CDCK
CI
Input capacitance, CK and CK
1.0
—
2.0
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
0.25
2.0
1.0
—
CDI
CIO
0.25
3.5
Input/output capacitance,
2.5
DQ, DM, DQS, DQS, RDQS, RDQS
CDIO
Input/output capacitance delta,
—
0.5
pF
DQ, DM, DQS, DQS, RDQS, RDQS
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TABLE 42
Input / Output Capacitance for DDR2-533
Symbol
Parameter
DDR2-533
Min.
Max.
Unit
CCK
CDCK
CI
Input capacitance, CK and CK
1.0
—
2.0
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
0.25
2.0
1.0
—
CDI
CIO
0.25
4.0
Input/output capacitance,
2.5
DQ, DM, DQS, DQS, RDQS, RDQS
CDIO
Input/output capacitance delta,
—
0.5
pF
DQ, DM, DQS, DQS, RDQS, RDQS
TABLE 43
Input / Output Capacitance for DDR2-400
Symbol
Parameter
DDR2-400
Min.
Max.
Unit
CCK
CDCK
CI
Input capacitance, CK and CK
1.0
—
2.0
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
0.25
2.0
1.0
—
CDI
CIO
0.25
4.0
Input/output capacitance,
2.5
DQ, DM, DQS, DQS, RDQS, RDQS
CDIO
Input/output capacitance delta,
—
0.5
pF
DQ, DM, DQS, DQS, RDQS, RDQS
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5.6
Overshoot and Undershoot Specification
This chapter contains overshoot and undershoot specification.
TABLE 44
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Unit
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above VDD
0.9
0.9
0.9
0.9
V
0.9
0.9
0.9
0.9
V
1.33
1.33
1.00
1.00
0.80
0.80
0.66
0.66
V.ns
V.ns
Maximum undershoot area below VSS
FIGURE 6
AC Overshoot / Undershoot Diagram for Address and Control Pins
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TABLE 45
AC Overshoot / Undershoot Spec. for Clock, Data, Strobe and Mask Pins
Parameter
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Unit
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above VDDQ
0.9
0.9
0.9
0.9
V
0.9
0.9
0.9
0.9
V
0.38
0.38
0.28
0.28
0.23
0.23
0.23
0.23
V.ns
V.ns
Maximum undershoot area below VSSQ
FIGURE 7
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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6
Currents Measurement Conditions
This chapter describes the current measurement specifications and conditions.
TABLE 46
DD Measurement Conditions
I
Parameter
Symbol Note
1)2)3)4)5)
Operating Current - One bank Active - Precharge
IDD0
6)
t
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are switching; Databus inputs are switching.
1)2)3)4)5)
Operating Current - One bank Active - Read - Precharge
IDD1
6)
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus
inputs are switching.
1)2)3)4)5)
6)
Precharge Power-Down Current
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are
IDD2P
floating.
1)2)3)4)5)
6)
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
IDD2N
1)2)3)4)5)
6)
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable,
Data bus inputs are floating.
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
1)2)3)4)5)
6)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs
are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
1)2)3)4)5)
6)
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
1)2)3)4)5)
6)
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
1)2)3)4)5)
6)
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD)
;
t
RAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching; IOUT = 0 mA.
1)2)3)4)5)
6)
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD)
;
t
RAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
1)2)3)4)5)
6)
Burst Refresh Current
IDD5B
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5)
6)
Distributed Refresh Current
IDD5D
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
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Parameter
Symbol Note
1)2)3)4)5)
Self-Refresh Current
IDD6
6)
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating,
Data bus inputs are floating.
1)2)3)4)5)
6)7)
Operating Bank Interleave Read Current
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD)
IDD7
,
t
RC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid commands.
Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern:
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks)
DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks)
1)
2)
3)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized.
DD parameter are specified with ODT disabled.
I
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for IDD: see Table 47
6) Timing parameter minimum and maximum values for IDD current measurements are defined in Chapter 7.
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
TABLE 47
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
FLOATING
SWITCHING
defined as inputs are stable at a HIGH or LOW level
defined as inputs are VREF = VDDQ / 2
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
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TABLE 48
DD Specification
I
Symbol
25F
2.5
3
3S
3.7
5
Unit Note
DDR2 - 800 DDR2 - 800 DDR2 - 667 DDR2 - 667 DDR2 - 533 DDR2 - 400
Max.
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
125
150
135
160
12
125
150
135
160
12
110
135
120
145
12
110
135
120
145
12
100
125
105
130
12
95
mA ×4/×8
mA ×16
mA ×4/×8
mA ×16
mA
120
100
125
12
IDD2P
IDD2N
IDD2Q
70
70
65
65
55
50
mA
65
65
60
60
50
45
mA
I
I
DD3P_0 (fast) 48
DD3P_1 (slow) 15
48
45
45
38
35
mA
15
15
15
15
15
mA
IDD3N
IDD4R
90
90
70
70
60
55
mA
200
240
200
240
225
13
200
240
200
240
225
13
170
205
170
205
210
13
170
205
170
205
210
13
150
175
150
175
200
13
135
150
135
150
190
13
mA ×4/×8
mA ×16
mA ×4/×8
mA ×16
mA
IDD4W
IDD5B
IDD5D
IDD6
1)
mA
10
10
10
10
10
10
mA 1) Standard
—
—
—
3.7
4.8
3.7
230
300
3.7
4.8
3.7
225
280
3.7
4.8
—
mA 1) ×4/×8 Low power
mA 1) ×16 Low power
mA 1) ×16 Very low power
mA ×4/×8
—
—
—
—
—
—
IDD7
270
340
270
340
230
300
215
265
mA ×16
1) 0° ≤ TCASE ≤ 85 °C.
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7
Timing Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
7.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications (tCK = 5ns with tRAS = 40ns).
TABLE 49
Speed Grade Definition Speed Bins for DDR2–800
Speed Grade
DDR2–800D
DDR2–800E
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–2.5F
–2.5
5–5–5
6–6–6
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
2.5
8
3.75
3
8
tCK
8
8
tCK
2.5
45
8
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
70000
—
57.5
12.5
12.5
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined .
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
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TABLE 50
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3
–3S
4–4–4
5–5–5
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3
8
3.75
3
8
tCK
3
8
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70000
—
45
60
15
15
70000
—
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
TABLE 51
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3.7
4–4–4
tCK
Parameter
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3.75
45
8
tCK
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
60
15
—
15
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
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1-Gbit Double-Data-Rate-Two SDRAM
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
TABLE 52
Speed Grade Definition Speed Bins for DDR2-400B
Speed Grade
DDR2–400B
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–5
3–3–3
tCK
Parameter
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
5
8
tCK
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
40
55
15
15
70000
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
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1-Gbit Double-Data-Rate-Two SDRAM
7.2
Component AC Timing Parameters
List of Timing Parameters Tables.
TABLE 53
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note1)2)3)4)5)6)7)
Min.
Max.
8)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–400
2
+400
—
ps
tCCD
nCK
tCK.AVG
ps
9)10)
9)10)
11)
tCH.AVG
tCK.AVG
0.48
2500
3
0.52
8000
—
CKE minimum pulse width ( high and low pulse tCKE
nCK
width)
9)10)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
12)13)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
––
18)19)14)
8)
DQ and DM input hold time
tDH.BASE
tDIPW
tDQSCK
tDQSH
125
––
ps
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
0.35
–350
0.35
0.35
—
—
tCK.AVG
ps
+350
—
tCK.AVG
tCK.AVG
ps
DQS input low pulse width
tDQSL
—
15)
16)
DQS-DQ skew for DQS & associated DQ signals tDQSQ
200
+ 0.25
DQS latching rising transition to associated clock tDQSS
– 0.25
tCK.AVG
edges
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
tDSH
tDSS
50
0.2
0.2
35
45
––
—
—
—
—
__
ps
DQS falling edge hold time from CK
DQS falling edge to CK setup time
tCK.AVG
tCK.AVG
ns
16)
34)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
34)
ns
20)
CK half pulse width
tHP
Min(tCH.ABS
,
ps
tCL.ABS
)
8)21)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
22)24)
tIH.BASE
250
0.6
ps
Control & address input pulse width for each input tIPW
—
tCK.AVG
ps
23)24)
8)21)
8)21)
34)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS.BASE
175
—
tLZ.DQ
tLZ.DQS
tMOD
tMRD
tOIT
2 x tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
0
ns
—
nCK
ns
34)
25)
12
DQ/DQS output hold time from DQS
tQH
t
HP – tQHS
—
ps
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1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–800
Min.
Unit
Note1)2)3)4)5)6)7)
Max.
26)
DQ hold skew factor
tQHS
tREFI
—
300
7.8
3.9
—
ps
µs
µs
ns
27)28)
28)29)
30)
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-Refresh command tRFC
127.5
period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1 × tCK
—
ns
31)32)
31)33)
34)
tRPRE
tRPST
tRRD
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Read postamble
Active to active command period for 1KB page
size products
34)
34)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
0.35
0.4
15
—
—
0.6
—
—
—
—
ns
tWPRE
tWPST
tWR
tCK.AVG
tCK.AVG
ns
Write postamble
34)
Write recovery time
34)35)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
2
ns
nCK
nCK
Exit active power-down mode to read command tXARDS
8 – AL
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
34)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
RL – 1
1)
V
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT
.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN
– 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
=
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and
these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
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10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between
the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
of Chapter 7.3).
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period.
Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 9.
15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN
See Figure 9.
.
18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 10.
23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 10.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples:
1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum.
2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26) tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output;
and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are
independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
28) 0 °C≤ TCASE ≤ 85 °C
29) 85 °C < TCASE ≤ 95 °C
30) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 8 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
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1-Gbit Double-Data-Rate-Two SDRAM
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
TABLE 54
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
Min.
Max.
8)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
tAC
–450
2
+450
—
ps
tCCD
nCK
tCK.AVG
ps
9)10)
11)
tCH.AVG
tCK.AVG
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and low pulse tCKE
nCK
width)
9)10)
Average clock low pulse width
tCL.AVG
0.48
0.52
—
tCK.AVG
nCK
ns
12)13)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
––
18)19)14)
8)
DQ and DM input hold time
tDH.BASE
tDIPW
tDQSCK
tDQSH
175
––
ps
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
0.35
–400
0.35
0.35
—
—
tCK.AVG
ps
+400
—
tCK.AVG
tCK.AVG
ps
DQS input low pulse width
tDQSL
—
15)
16)
DQS-DQ skew for DQS & associated DQ signals tDQSQ
240
+ 0.25
DQS latching rising transition to associated clock tDQSS
– 0.25
tCK.AVG
edges
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
tDSH
tDSS
100
0.2
0.2
37.5
50
––
—
—
—
—
__
ps
DQS falling edge hold time from CK
DQS falling edge to CK setup time
tCK.AVG
tCK.AVG
ns
16)
34)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
34)
ns
20)
CK half pulse width
tHP
Min(tCH.ABS
,
ps
tCL.ABS
)
8)21)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
ps
ps
24)22)
tIH.BASE
275
—
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–667
Min.
Unit
Note1)2)3)4)5)6)7)
Max.
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
ps
23)24)
8)21)
8)21)
34)
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS.BASE
200
—
tLZ.DQ
tLZ.DQS
tMOD
tMRD
tOIT
2 x tAC.MIN
tAC.MAX
tAC.MAX
12
ps
tAC.MIN
ps
0
2
0
ns
—
nCK
ns
34)
12
25)
DQ/DQS output hold time from DQS
DQ hold skew factor
tQH
t
HP – tQHS
—
ps
26)
tQHS
tREFI
—
340
7.8
3.9
—
ps
27)28)
28)29)
30)
Average periodic refresh Interval
—
µs
—
µs
Auto-Refresh to Active/Auto-Refresh command tRFC
127.5
ns
period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1 × tCK
—
ns
31)32)
31)33)
34)
tRPRE
tRPST
tRRD
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Read postamble
Active to active command period for 1KB page
size products
34)
34)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
0.35
0.4
15
—
—
0.6
—
—
—
—
ns
tWPRE
tWPST
tWR
tCK.AVG
tCK.AVG
ns
Write postamble
34)
Write recovery time
34)35)
Internal write to read command delay
Exit power down to read command
tWTR
tXARD
7.5
2
ns
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
34)
Exit self-refresh to a non-read command
Exit self-refresh to read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
nCK
nCK
Write command to DQS associated clock edges WL
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
RL–1
1)
V
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT
.
Rev. 1.3, 2007-07
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN
– 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
=
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and
these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between
the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
of Chapter 7.3).
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period.
Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 9.
15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN
See Figure 9.
.
18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 10.
23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 10.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples:
1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum.
2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
Rev. 1.3, 2007-07
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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
26) tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output;
and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are
independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
28) 0 °C≤ TCASE ≤ 85 °C
29) 85 °C < TCASE ≤ 95 °C
30) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 8 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 8
Method for calculating transitions and endpoint
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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 9
Differential input waveform timing - tDS and tDS
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Rev. 1.3, 2007-07
03062006-ZNH8-HURV
55
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 55
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
7)17)
8)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
9)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
10)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
10)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
10)
10)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended data tDS1(base)
strobe)
–25
0.2
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
—
—
tCK
ns
ns
Four Activate Window period
Four Activate Window period
Clock half period
tFAW
tFAW
tHP
37.5
12)
11)
12)
10)
50
MIN. (tCL, tCH
)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
375
0.6
Address and control input pulse width
(each input)
—
10)
13)
13)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMOD
250
—
ps
ps
ps
ns
tCK
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
12
tAC.MIN
0
2
0
tMRD
—
tOIT
12
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–533
Min.
Unit
Note1)2)3)4)5)
6)
Max.
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
tREFI
tREFI
tRFC
—
400
7.8
3.9
—
ps
µs
µs
ns
13)14)
15)17)
16)
Average periodic refresh Interval
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-Refresh
command period
127.5
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1 × tCK
—
ns
tCK
tCK
ns
13)
tRPRE
tRPST
tRRD
0.9
1.1
0.60
—
13)
Read postamble
0.40
7.5
13)17)
Active bank A to Active bank B command
period
15)21)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
18)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
19)
20)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
WR
t
RFC +10
200
WR/tCK
—
—
—
ns
tCK
tCK
21)
Write recovery time for write with Auto-
Precharge
t
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT
.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
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1-Gbit Double-Data-Rate-Two SDRAM
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for Lead-Free
Products (RoHS Compliant)” on Page 5.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
TABLE 56
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–600
2
+600
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
7)20)
8)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
275
––
––
—
ns
ps
ps
9)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
10)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–500
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+500
—
DQS input low (high) pulse width (write cycle) tDQSL,H
10)
10)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
350
Write command to 1st DQS latching transition tDQSS
– 0.25
150
+ 0.25
—
tCK
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Min.
Max.
10)
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
–25
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
—
—
tCK
ns
ns
Four Activate Window period
Four Activate Window period
Clock half period
tFAW
tFAW
tHP
37.5
12)
11)
12)
10)
50
MIN. (tCL, tCH
)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
475
0.6
Address and control input pulse width
(each input)
—
10)
13)
13)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMOD
tMRD
tOIT
350
—
ps
ps
ps
ns
tCK
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
12
tAC.MIN
0
2
0
—
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
450
7.8
3.9
—
ps
µs
µs
ns
13)14)
15)17)
16)
Average periodic refresh Interval
Average periodic refresh Interval
tREFI
tREFI
—
—
—
Auto-Refresh to Active/Auto-Refresh
command period
127.5
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1 × tCK
—
ns
tCK
tCK
ns
13)
tRPRE
tRPST
tRRD
0.9
1.1
0.60
—
13)
Read postamble
0.40
7.5
13)17)
Active bank A to Active bank B command
period
15)21)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
18)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
19)
20)
Internal Write to Read command delay
tWTR
10
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
20)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
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Parameter
Symbol
DDR2–400
Unit
Note1)2)3)4)5)
6)
Min.
Max.
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
WR
t
RFC +10
200
WR/tCK
—
—
—
ns
tCK
tCK
21)
Write recovery time for write with Auto-
Precharge
t
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT
.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for Lead-Free
Products (RoHS Compliant)” on Page 5.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
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1-Gbit Double-Data-Rate-Two SDRAM
7.3
Jitter Definition and Clock Jitter Specification
Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table
provides an overview of the terminology.
TABLE 57
Average Clock and Jitter Symbols and Definition
Symbol
Parameter
Description
Units
tCK.AVG
Average clock period tCK.AVG is calculated as the average clock period within any consecutive ps
200-cycle window:
N
⎛
⎜
⎜
⎝
⎞
⎟
1
N
.
---
tCK.AVG =
tCKj
(1)
∑
⎟
⎠
j = 1
N = 200
tJIT.PER
Clock-period jitter
t
t
JIT.PER is defined as the largest deviation of any single tCK from tCK.AVG
JIT.PER = Min/Max of {tCKi – tCK.AVG} where i = 1 to 200
:
ps
t
t
JIT.PER defines the single-period jitter when the DLL is already locked.
JIT.PER is not guaranteed through final production testing.
t
JIT(PER, LCK)
Clock-period jitter
during DLL-locking
period
t
JIT(PER,LCK) uses the same definition as tJIT.PER, during the DLL-locking ps
period only.
t
JIT(PER,LCK) is not guaranteed through final production testing.
tJIT.CC
Cycle-to-cycle clock
period jitter
t
JIT.CC is defined as the absolute difference in clock period between two
ps
consecutive clock cycles:
t
JIT.CC = Max of ABS{tCKi+1 – tCKi}
t
t
JIT.CC defines the cycle- to- cycle jitter when the DLL is already locked.
JIT.CC is not guaranteed through final production testing.
t
JIT(CC, LCK)
Cycle-to-cycle clock
period jitter during
DLL-locking period
t
JIT(CC,LCK) uses the same definition as tJIT.CC during the DLL-locking
ps
period only.
t
JIT(CC,LCK) is not guaranteed through final production testing.
tERR.2PER
Cumulative error
across 2 cycles
t
ERR.2PER is defined as the cumulative error across 2 consecutive cycles ps
from tCK.AVG
:
i + n – 1
⎛
⎜
⎜
⎝
⎞
⎟
tERR(2per) =
tCKj – n × tCK(avg)
(2)
∑
⎟
⎠
j = i
n = 2 for tERR(2per)
where i = 1 to 200
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1-Gbit Double-Data-Rate-Two SDRAM
Symbol
Parameter
Description
Units
tERR.nPER
Cumulative error
across n cycles
t
ERR.2PER is defined as the cumulative error across n consecutive cycles ps
from tCK.AVG
:
i + n – 1
⎛
⎜
⎜
⎝
⎞
⎟
tERR(nper) =
tCKj – n × tCK(avg)
(3)
∑
⎟
⎠
j = i
where, i = 1 to 200 and
n = 3 for tERR.3PER
n = 4 for tERR.4PER
n = 5 for tERR.5PER
6 ≤ n ≤ 10 for tERR.6-10PER
11 ≤ n ≤ 50 for tERR.11-50PER
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse
width
tCH.AVG is defined as the average high-pulse width, as calculated across tCK.AVG
any consecutive 200 high pulses:
N
⎛
⎜
⎜
⎝
⎞
⎟
1
.
----------------------------------------
tCH(avg) =
tCHj
(4)
∑
⎟
⎠
(N × tCK(avg))
j = 1
N = 200
Average low-pulse
width
t
CL.AVG is defined as the average low-pulse width, as calculated across any tCK.AVG
consecutive 200 low pulses:
N
⎛
⎜
⎜
⎝
⎞
⎟
1
(5)
.
----------------------------------------
tCL(avg) =
tCLj
∑
⎟
⎠
(N × tCK(avg))
j = 1
N = 200
Duty-cycle jitter
t
t
t
t
t
JIT.DUTY = Min/Max of {tJIT.CH , tJIT.CL}, where:
ps
JIT.CH is the largest deviation of any single tCH from tCH.AVG
JIT.CL is the largest deviation of any single tCL from tCL.AVG
JIT.CH = {tCHi - tCH.AVG × tCK.AVG} where i=1 to 200
JIT.CL = {tCLi - tCL.AVG × tCK.AVG} where i=1 to 200
The following parameters are specified per their average values however, it is understood that the following relationship
between the average timing and the absolute instantaneous timing holds all the time.
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1-Gbit Double-Data-Rate-Two SDRAM
TABLE 58
Absolute Jitter Value Definitions
Symbol Parameter
Min.
Max.
Unit
tCK.ABS
tCH.ABS
Clock period
t
t
CK.AVG(Min) + tJIT.PER(Min)
t
CK.AVG(Max) + tJIT.PER(Max)
CH.AVG(Max) x tCK.AVG(Max) +
ps
ps
Clock high-pulse width
CH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min)
t
tJIT.DUTY(Max)
tCL.ABS
Clock low-pulse width
tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max)
+
ps
tJIT.DUTY(Max)
Example: for DDR2-667, tCH.ABS(Min) = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 59 shows clock-jitter specifications.
TABLE 59
Clock-Jitter Specifications for –667 and –800
Symbol
Parameter
DDR2 -667
DDR2 -800
Unit
Min.
Max.
Min.
Max.
tCK.AVG
Average clock period nominal w/o jitter
Clock-period jitter
3000
–125
–100
–250
–200
8000
+125
+100
+250
+200
2500
–100
–80
8000
+100
+80
ps
ps
ps
ps
ps
tJIT.PER
tJIT(PER,LCK)
tJIT.CC
Clock-period jitter during DLL locking period
Cycle-to-cycle clock-period jitter
–200
–160
+200
+160
tJIT(CC,LCK)
Cycle-to-cycle clock-period jitter during DLL-
locking period
tERR.2PER
tERR.3PER
tERR.4PER
tERR.5PER
tERR(6-10PER)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
–175
–225
–250
–250
–350
+175
+225
+250
+250
+350
–150
–175
–200
–200
–300
+150
+175
+200
+200
+300
ps
ps
ps
ps
ps
Cumulative error across n cycles with n = 6 ..
10, inclusive
tERR(11-50PER)
Cumulative error across n cycles with n = 11 .. –450
50, inclusive
+450
–450
+450
ps
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse width
Average low-pulse width
Duty-cycle jitter
0.48
0.48
–125
0.52
0.52
+125
0.48
0.48
–100
0.52
0.52
+100
tCK.AVG
tCK.AVG
ps
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7.4
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 60
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
TABLE 61
ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK +
tAC.MAX + 1 ns
ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
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1-Gbit Double-Data-Rate-Two SDRAM
8
Package Dimensions
This chapter describes the package dimensions.
FIGURE 11
Package Outline P(G)-TFBGA-68
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1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 12
Package Outline P(G)-TFBGA-84
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1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 13
Package Outline PG-TFBGA-92
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1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
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HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
9
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
TABLE 62
Examples for Nomenclature Fields
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
DDR2 SDRAM
DDR2 SDRAM
HYB
HYB
18
18
T
T
1G
1G
40
16
0
0
A
B
F
F
—
L
–3
–3.7
TABLE 63
DDR2 Memory Components
Field Description
Values Coding
1
Qimonda Component Prefix
HYB
HYI
18
Memory components
Memory components, industrial temperature range (-40°C – +85 °C)
2
3
4
Interface Voltage [V]
DRAM Technology
SSTL_18
DDR2
256 Mbit
512 Mbit
1 Gbit
T
Component Density [Mbit]
256
512
1G
2G
40
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
look up table
A(0 ..9) First
B(0 ..9) Second
C(0 ..9) Third
9
Package,
Lead-Free Status
C
F
FBGA, lead-containing
FBGA, lead-free
10
Power
—
L
Standard power product
Low power product
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Field Description
11 Speed Grade
Values Coding
–1.9
–25F
–2.5
–3
DDR2–1066
DDR2–800 5–5–5
DDR2–800 6–6–6
DDR2–667 4–4–4
DDR2–667 5–5–5
DDR2–533 4–4–4
DDR2–400 3–3–3
–3S
–3.7
–5
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List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Ball Configuration for ×4 components, PG-TFBGA-68 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ball Configuration for ×8 components, PG-TFBGA-68 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Configuration for x16 Components in PG–TFBGA–84 (Top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 41
Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Differential input waveform timing - tlS and tlH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Package Outline P(G)-TFBGA-68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Package Outline P(G)-TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Package Outline PG-TFBGA-92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Performance Tables for –2.5(F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance Table for –3(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance table for –3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance Table for –5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information for Lead-Free Products (RoHS Compliant). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for Lead-Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DDR2 Addressing for ×4 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDR2 Addressing for ×8 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDR2 Addressing for ×16 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B). . . . . . . . . . . . . . . . . . . . . . . . . . 26
EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ODT Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC & AC Logic Input Levels for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC & AC Logic Input Levels for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input / Output Capacitance for DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Input / Output Capacitance for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Input / Output Capacitance for DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Input / Output Capacitance for DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
AC Overshoot / Undershoot Spec. for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
I
DD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Speed Grade Definition Speed Bins for DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I
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Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Speed Grade Definition Speed Bins for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Speed Grade Definition Speed Bins for DDR2–533C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Speed Grade Definition Speed Bins for DDR2-400B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DRAM Component Timing Parameter by Speed Grade - DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DRAM Component Timing Parameter by Speed Grade - DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DRAM Component Timing Parameter by Speed Grade - DDR2–533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DRAM Component Timing Parameter by Speed Grade - DDR2-400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Average Clock and Jitter Symbols and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Absolute Jitter Value Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock-Jitter Specifications for –667 and –800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . 64
ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . 64
Examples for Nomenclature Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Configuration for PG-TFBGA-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Configuration for PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chip Configuration for PG-TFBGA-92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1-Gbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1
2.2
2.3
2.4
3
4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
5.1.1
5.2
5.3
5.4
5.5
5.6
6
Currents Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Jitter Definition and Clock Jitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.1
7.2
7.3
7.4
8
9
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Edition 2007-07
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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