HYB18T256800AC-5 [QIMONDA]
DDR DRAM, 32MX8, 0.6ns, CMOS, PBGA60, PLASTIC, TFBGA-60;型号: | HYB18T256800AC-5 |
厂家: | QIMONDA AG |
描述: | DDR DRAM, 32MX8, 0.6ns, CMOS, PBGA60, PLASTIC, TFBGA-60 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总63页 (文件大小:3578K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
December 2007
HY[B/I]18T256400A[C/F](L)
HY[B/I]18T256800A[C/F](L)
HY[B/I]18T256160A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.50
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
HY[B/I]18T256400A[C/F](L), HY[B/I]18T256800A[C/F](L), HY[B/I]18T256160A[C/F](L)
Revision History: 2007-12, Rev. 1.50
Page
Subjects (major changes since last revision)
All
All
All
Adapted Internet Version
25 New Products added
Editorial Changes
Previous Revision: 2007-01 Rev. 1.41
All Qimonda update
Previous Revision: 2005-07 Rev. 1.4
Added low-power components HYB18T256[40/80/16]0AFL-3.7
Added DDR2-800 5-5-5 components
92
Updated IDD Currents (IDD2P, IDD3P1, IDD6)
Chapter 2 Updated Pin Configuration - various editorial changes on notes
Previous Revision: 2005-07 Rev. 1.3
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
03062006-7M17-PXBC
2
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
•
1.8 V ± 0.1 V Power Supply
•
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving Power-
Down modes
1.8 V ± 0.1 V (SSTL_18) compatible I/O
DRAM organizations with 4,8,16 data in/outputs
Double Data Rate architecture:
•
•
•
•
– two data transfers per clock cycle
– four internal banks for concurrent operation
Programmable CAS Latency: 3, 4, 5 and 6
Programmable Burst Length: 4 and 8
•
Average Refresh Period 7.8 μs at a TCASE lower
than 85 °C, 3.9 μs between 85 °C and 95 °C
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
•
•
•
•
•
•
•
•
•
•
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
Data masks (DM) for write data
Full and reduced Strength Data-Output Drivers
1KB page size
•
•
Packages: PG-TFBGA-84, PG-TFBGA-60, P-TFBGA-84,
P-TFBGA-60
•
•
RoHS Compliant Products1)
•
All Speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
•
•
Posted CAS by programmable additive latency for better
command and data bus efficiency
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.50, 2007-12
3
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
–5
Unit
Note
DRAM Speed Grade
DDR2 –800D
–800E
6–6–6
–667C
4–4–4
–667D
5–5–5
–533C
4–4–4
–400B
3–3–3
CAS-RCD-RP latencies
5–5–5
tCK
Max.
Clock Frequency
CL3 fCK3
CL4 fCK4
200
200
266
333
400
15
200
333
333
–
200
266
333
–
200
266
266
–
200
200
–
MHz
MHz
MHz
MHz
ns
266
400
–
CL5 fCK5
CL6 fCK6
–
Min. RAS-CAS-Delay
tRCD
tRP
12.5
12.5
12
15
15
15
15
Min. Row Precharge
Time
15
12
15
15
ns
Min. Row Active Time
Min. Row Cycle Time
tRAS
tRC
45
45
60
15
45
57
12
45
60
15
45
60
15
40
55
15
ns
ns
ns
57.5
12.5
Precharge-All (4 banks) tPREA
command period
1.2
Description
The 256-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing
268,435,456 bits and internally configured as a quad-bank
DRAM. The 256-Mbit device is organized as 16 Mbit ×4 I/O ×4
banks or 8 Mbit ×8 I/O ×4 banks or 4 Mbit ×16 I/O ×4 banks
chip.
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 15 bit address bus for ×4 and ×8 organised components
and a 15 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
A 15 bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
The DDR2 SDRAM is available in TFBGA package.
Rev. 1.50, 2007-12
4
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note5)
Standard Temperature Range (0 °C - +85 °C)
DDR2-800E( 6-6-6)
HYB18T256400AF-2.5
HYB18T256160AF-2.5
DDR2-800D( 5-5-5)
×4
DDR2-800E 6-6-6
400
400
PG-TFBGA-60
×16 DDR2-800E 6-6-6
PG-TFBGA-84
HYB18T256800AF-25F
HYB18T256400AF-25F
HYB18T256160AF-25F
DDR2-667D( 5-5-5)
×8
×4
DDR2-800D 5-5-5
DDR2-800D 5-5-5
400
400
400
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×16 DDR2-800D 5-5-5
HYB18T256160AF-3S
HYB18T256800AF-3S
HYB18T256400AF-3S
DDR2-667C( 4-4-4)
×16 DDR2-667D 5-5-5
333
333
333
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
×8
×4
DDR2-667D 5-5-5
DDR2-667D 5-5-5
HYB18T256160AF-3
DDR2-533C( 4-4-4)
×16 DDR2-667C 4-4-4
×16 DDR2-533C 4-4-4
333
PG-TFBGA-84
HYB18T256160AFL-3.7
HYB18T256400AFL-3.7
HYB18T256800AFL-3.7
HYB18T256800AF-3.7
HYB18T256400AF-3.7
HYB18T256160AF-3.7
DDR2-533B( 3-3-3)
266
266
266
266
266
266
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×4
×8
×8
×4
DDR2-533C 4-4-4
DDR2-533C 4-4-4
DDR2-533C 4-4-4
DDR2-533C 4-4-4
×16 DDR2-533C 4-4-4
HYB18T256800AF-2.5
DDR2-400B( 3-3-3)
×8
DDR2-533B 3-3-3
266
PG-TFBGA-60
HYB18T256800AF-5
HYB18T256400AF-5
HYB18T256160AF-5
×8
×4
DDR2-400B 3-3-3
DDR2-400B 3-3-3
200
200
200
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×16 DDR2-400B 3-3-3
Industrial Temperature Range (–40 °C - +85 °C)
DDR2-667D( 5-5-5)
HYI18T256800AF-3S
HYI18T256160AF-3S
HYI18T256400AF-3S
DDR2-533C( 4-4-4)
HYI18T256160AF-3.7
HYI18T256800AF-3.7
×8
×16 DDR2-667D 5-5-5
×4 DDR2-667D 5-5-5
DDR2-667D 5-5-5
333
333
333
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
×16 DDR2-533C 4-4-4
×8 DDR2-533C 4-4-4
266
266
PG-TFBGA-84
PG-TFBGA-60
Rev. 1.50, 2007-12
5
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note5)
HYI18T256400AF-3.7
DDR2-400B( 3-3-3)
HYI18T256160AF-5
HYI18T256800AF-5
HYI18T256400AF-5
×4
DDR2-533C 4-4-4
266
PG-TFBGA-60
×16 DDR2-400B 3-3-3
200
200
200
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
×8
×4
DDR2-400B 3-3-3
DDR2-400B 3-3-3
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet.
2) CAS: Column Address Strobe
3) RCD: Row Column Delay
4) RP: Row Precharge
5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
TABLE 3
Ordering Information for non RoHS Compliant Products
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note
Standard Temperature Range (0 °C - +85 °C)
DDR2-667D( 5-5-5)
HYB18T256160AC-3S
HYB18T256800AC-3S
HYB18T256400AC-3S
DDR2-533C( 4-4-4)
×16 DDR2-667D 5-5-5
333
333
333
P-TFBGA-84
×8
×4
DDR2-667D 5-5-5
P-TFBGA-60
P-TFBGA-60
DDR2-667D 5-5-5
HYB18T256800AC-3.7
HYB18T256400AC-3.7
HYB18T256160AC-3.7
DDR2-400B( 3-3-3)
×8
×4
DDR2-533C 4-4-4
DDR2-533C 4-4-4
266
266
266
P-TFBGA-60
P-TFBGA-60
P-TFBGA-84
×16 DDR2-533C 4-4-4
HYB18T256800AC-5
HYB18T256400AC-5
HYB18T256160AC-5
×8
×4
DDR2-400B 3-3-3
DDR2-400B 3-3-3
200
200
200
P-TFBGA-60
P-TFBGA-60
P-TFBGA-84
×16 DDR2-400B 3-3-3
Industrial Temperature Range (–40 °C - +85 °C)
DDR2-667D( 5-5-5)
HYI18T256800AC-3S
HYI18T256160AC-3S
HYI18T256400AC-3S
DDR2-533C( 4-4-4)
HYI18T256800AC-3.7
HYI18T256160AC-3.7
HYI18T256400AC-3.7
DDR2-400B( 3-3-3)
HYI18T256160AC-5
×8
DDR2-667D 5-5-5
333
333
333
P-TFBGA-60
P-TFBGA-84
P-TFBGA-60
×16 DDR2-667D 5-5-5
×4
×8
DDR2-667D 5-5-5
DDR2-533C 4-4-4
266
266
266
P-TFBGA-60
P-TFBGA-84
P-TFBGA-60
×16 DDR2-533C 4-4-4
×4 DDR2-533C 4-4-4
×16 DDR2-400B 3-3-3
200
P-TFBGA-84
Rev. 1.50, 2007-12
6
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note
HYI18T256800AC-5
HYI18T256400AC-5
×8
×4
DDR2-400B 3-3-3
DDR2-400B 3-3-3
200
200
P-TFBGA-60
P-TFBGA-60
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet.
2) CAS: Column Address Strobe
3) RCD: Row Column Delay
4) RP: Row Precharge
Rev. 1.50, 2007-12
7
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration.
2.1
Configuration for TFBGA-60
The chip configuration of a DDR2 SDRAM is listed by function in Table 4. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 5 and Table 6 respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 4
Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals
E8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
F8
CK
F2
CKE
Control Signals
F7
G7
F3
G8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals
G2
G3
H8
H3
H7
J2
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
BA1
A0
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
J8
A4
J3
A5
J7
A6
K2
K8
K3
H2
A7
A8
A9
A10
AP
A11
A12
K7
L2
Rev. 1.50, 2007-12
8
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Data Signals ×4 Organization
C8
C2
D7
D3
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal 3:0
Data Signals ×8 Organization
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 7:0
Data Strobe ×4 Organization
B7
A8
DQS
DQS
I/O
I/O
SSTL
SSTL
Data Strobe
Data Strobe ×8 Organisation
B7
A8
B3
A2
DQS
I/O
I/O
O
SSTL
SSTL
SSTL
SSTL
Data Strobe
DQS
RDQS
RDQS
Read Data Strobe
O
Data Mask ×4 Organization
B3 DM
Data Mask ×8 Organization
I
SSTL
SSTL
–
Data Mask
B3
DM
I
Data Mask
Power Supplies
A9, C1, C3, C7, VDDQ
PWR
I/O Driver Power Supply
C9
A1, L1, E9, H9 VDD
PWR
PWR
–
–
Power Supply
A7, B2, B8, D2, VSSQ
I/O Driver Power Supply
D8
A3, E3, J1, K9 VSS
PWR
AI
–
–
–
–
Power Supply
E2
E1
E7
VREF
VDDL
VSSDL
I/O Reference Voltage
Power Supply
PWR
PWR
Power Supply
Not Connected ×4 Organization
A2, B1, B9, D1, NC
D9, G1, L3, L7,
L8
NC
–
Not Connected
Rev. 1.50, 2007-12
9
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Not Connected ×8 Organization
G1, L3, L7, L8 NC NC
Other Balls ×4 Organization
F9 ODT
Other Balls ×8 Organization
–
Not Connected
I
SSTL
SSTL
On-Die Termination Control
On-Die Termination Control
F9
ODT
I
TABLE 5
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.50, 2007-12
10
03062006-7M17-PXBC
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, TFBGA-60 (top view)
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Notes
1. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
2. Ball position L8 is Not Connected on 256-Mbit
Rev. 1.50, 2007-12
11
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 2
Chip Configuration for ×8 components, TFBGA-60 (top view)
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Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
5. Ball position L8 is Not Connected on 256-Mbit.
Rev. 1.50, 2007-12
12
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2.2
Configuration for TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 8 and Table 9 respectively.
TABLE 7
Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×16 Organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×16 Organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
L2
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
L3
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Data Signals ×16 Organization
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal Lower Byte 7:0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
Data Signal Upper Byte 15:8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Data Strobe ×16 Organization
B7
A8
F7
E8
UDQS
UDQS
LDQS
LDQS
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×16 Organization
B3
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
Note: LDM is the input mask signal that controls the lower byte.
Power Supplies ×16 Organization
J2
VREF
AI
–
–
I/O Reference Voltage
A9, C1, C3, C7, VDDQ
C9, E9, G1, G3,
G7, G9
PWR
I/O Driver Power Supply
J1
VDDL
PWR
PWR
–
–
Power Supply
Power Supply
A1, E1, J9, M9, VDD
R1
A7, B2, B8, D2, VSSQ
PWR
–
Power Supply
D8, E7, F2, F8,
H2,
H8
J7
VSSDL
PWR
PWR
–
–
Power Supply
Power Supply
A3, E3, J3, N1, VSS
P9
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Not Connected ×16 Organization
A2, E2, L1, R3, NC
R7, R8
NC
–
Not Connected
Other Balls ×16 Organization
K9
ODT
I
SSTL
On-Die Termination Control
TABLE 8
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 9
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.50, 2007-12
15
03062006-7M17-PXBC
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 3
Configuration for ×16 components, TFBGA-84 (top view)
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Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
Rev. 1.50, 2007-12
16
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
2.3
Addressing
This chapter describes the DDR2 addressing.
TABLE 10
256 Mb DDR2 Addressing
Configuration
64 Mb x 41)
32 Mb x 82)
16 Mb x163)
Note
Bank Address
Number of Banks
Auto Precharge
Row Address
BA[1:0]
4
BA[1:0]
4
BA[1:0]
4
A10 / AP
A[12:0]
A11, A[9:0]
A10 / AP
A[12:0]
A[9:0]
10
A10 / AP
A[12:0]
A[8:0]
9
Column Address
4)
5)
Number of Column Address Bits 11
Number of I/Os
4
8
16
Page Size [Bytes]
1024 (1 K)
1024 (1 K)
1024 (1 K)
1) Referred to as ’org’
2) Referred to as ’org’
3) Referred to as ’org’
4) Referred to as ’colbits’
5) PageSize = 2colbits × org/8 [Bytes]
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
This chapter contains the functional description.
3.1
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM.
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TABLE 11
Mode Register Definition, BA2:0 = 000B
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address 2
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address 1
BA1
BA0
A13
15
14
13
0B
BA1 Bank Address
Bank Address 0
0B
BA0 Bank Address
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13 Address bit 13
PD
12
w
w
Active Power-Down Mode Select
0B
1B
PD Fast exit
PD Slow exit
WR
[11:9]
Write Recovery2)
Note: All other bit combinations are illegal.
001B WR 2
010B WR 3
011B WR 4
100B WR 5
101B WR 6
DLL
8
w
DLL Reset
0B
1B
DLL No
DLL Yes
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
Test Mode
TM
7
w
0B
1B
TM Normal Mode
TM Vendor specific test mode
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
011B CL 3
100B CL 4
101B CL 5
110B CL 6
111B CL 7
BT
BL
3
w
w
Burst Type
0B
1B
BT Sequential
BT Interleaved
[2:0]
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN
.
Rev. 1.50, 2007-12
19
03062006-7M17-PXBC
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
3.2
Extended Mode Register EMR(1)
The Extended Mode Register EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,
OCD program, ODT, DQS and output buffers disable, RDQS and RDQS enable.
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TABLE 12
Extended Mode Register Definition, BA2:0 = 001B
Field
Bits Type1)
Description
Bank Address 2
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address 1
BA2
16
reg. addr.
BA1
BA0
A13
15
14
13
0B
BA1 Bank Address
Bank Address 0
1B
BA0 Bank Address
w
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13 Address bit 13
Qoff
12
w
w
w
w
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
RDQS
DQS
OCD
11
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS Disable
RDQS Enable
10
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
[9:7]
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
Program
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
w
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Field
Bits Type1)
Description
RTT
6,2
w
Nominal Termination Resistance of ODT
Note: See Table 22 “ODT DC Electrical Characteristics” on Page 28
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
w
w
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
3.3
Extended Mode Register EMR(2)
The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the
mode register during initialization.
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TABLE 13
EMR(2) Programming Extended Mode Register Definition, BA2:0=010B
Field Bits
Type1)
Description
BA
[15:14]
w
Bank Adress
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
[13:8]
7
w
w
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
000000B A Address bits
SRF
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:4]
3
w
w
Address Bus
000B A Address bits
DCC
Address Bus, Duty Cycle Correction (DCC)
0B
1B
A3 DCC disabled
A3 DCC enabled
Partial Self Refresh for 4 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 4 Banks2)
Note: Only for 256 Mbit and 512 Mbit components
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to 1 before the self refresh
mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
Rev. 1.50, 2007-12
22
03062006-7M17-PXBC
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
3.4
Extended Mode Register EMR(3)
The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0
when setting the mode register during initialization.
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TABLE 14
EMR(3) Programming Extended Mode Register Definition, BA2:0=011B
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address 2
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2 Bank Address
BA1
BA0
A
15
Bank Adress 1
1B
BA1 Bank Address
14
Bank Adress 0
1B
BA0 Bank Address
[13:0]
w
Address Bus 13:0
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
00000000000000BA[13:0] Address bits
1) w = write only
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
3.5
Burst Mode Operation
TABLE 15
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
× 0 0
× 0 1
×1 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
×1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Rev. 1.50, 2007-12
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
This chapter describes the truth tables.
TABLE 16
Command Truth Table
Function
CKE
CS RAS CAS WE BA0 A[12:11] A10 A[9:0]
Note1)2)3)
BA1
Previous Current
Cycle
Cycle
4)5)6)
4)
(Extended) Mode Register Set H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
BA OP Code
Auto-Refresh
H
H
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
4)7)
Self-Refresh Entry
Self-Refresh Exit
L
L
4)7)8)
H
X
H
L
X
H
H
H
H
L
4)5)
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
BA
X
X
X
L
X
X
4)5)
L
L
H
4)5)
L
H
L
BA Row Address
4)5)9)
4)5)9)
4)5)9)
4)5)9)
4)
Write
H
H
H
H
H
X
X
H
X
H
BA Column
BA Column
BA Column
BA Column
L
Column
Column
Column
Column
X
Write with Auto-Precharge
Read
L
L
H
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge
No Operation
L
H
X
X
X
H
X
X
H
X
H
X
X
X
X
X
X
4)
Device Deselect
Power Down Entry
X
4)10)
X
4)10)
Power Down Exit
L
H
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) All banks must be in a precharged idle state, CKE must be high at least for tXP and all read/write bursts must be finished before the
(Extended) Mode Register set Command is issued.
7)
VREF must be maintained during Self Refresh operation.
8) Self Refresh Exit is asynchronous.
9) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 3.5 for details.
10)The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
Rev. 1.50, 2007-12
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256-Mbit Double-Data-Rate-Two SDRAM
TABLE 17
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1)
CKE
Command
(N)2)3)RAS, CAS, WE,
CS
Action (N)2)
Note4)5)
Previous Cycle6) Current Cycle6)
(N-1)
(N)
7)8)11)
Power-Down
Self Refresh
L
L
L
L
H
H
L
H
L
H
L
L
X
Maintain Power-Down
Power-Down Exit
7)9)10)11)
8)11)12)
DESELECT or NOP
X
Maintain Self Refresh
Self Refresh Exit
9)11)12)13)14)
7)9)10)11)15)
9)10)11)15)
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
Bank(s) Active
All Banks Idle
Active Power-Down Entry
Precharge Power-Down
Entry
7)11)14)16)
17)
H
H
L
AUTOREFRESH
Self Refresh Entry
Any State other than
listed above
H
Refer to the Command Truth Table
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 × tCK + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15)Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
TABLE 18
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
X
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.50, 2007-12
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5
Electrical Characteristics
This chapter describes the Electrical Characteristics.
5.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 19 at any time.
TABLE 19
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
–1.0
–0.5
–0.5
–0.5
–55
+2.3
+2.3
+2.3
+2.3
+100
V
1)2)
1)2)
1)
VDDQ
VDDL
V
V
VIN, VOUT
TSTG
V
1)2)
°C
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 20
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Notes
Min.
Max.
1)2)3)4)
TOPER
Operating Temperature
0
+95
+85
°C
-40
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C for HYB... products and -40 - +85 for HYI... products under all other specification
parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 μs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.50, 2007-12
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
TABLE 21
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating
Min.
Unit
Note
Typ.
Max.
1)
VDD
Supply Voltage
1.7
1.8
1.9
V
V
V
V
V
1)
VDDDL
VDDQ
VREF
VTT
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
1)
1.7
1.8
1.9
2)3)
4)
0.49 × VDDQ
0.5 × VDDQ
VREF
0.51 × VDDQ
V
REF – 0.04
VREF + 0.04
1)
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
2) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
3) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
.
4)
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF
.
TABLE 22
ODT DC Electrical Characteristics
Parameter / Condition
Symbol Min. Nom. Max. Unit Note
1)
Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Rtt1(eff) 60
Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Rtt2(eff) 120
75
150
50
90
Ω
Ω
Ω
1)
180
60
1)2)
3)
Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Deviation of VM with respect to VDDQ / 2
Rtt3(eff) 40
delta VM –6.00
—
+6.00 %
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Optional for DDR2-400, DDR2-533 and DDR2-667, mandatory for DDR2-800.
3) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
1) x 100%
TABLE 23
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Note
1)
IIL
Input Leakage Current; any input 0 V < VIN < VDD
Output Leakage Current; 0 V < VOUT < VDDQ
–2
–5
+2
+5
μA
μA
2)
IOL
1) All other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Rev. 1.50, 2007-12
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
relative to the rising or falling edges of DQS crossing at VREF
.
TABLE 24
DC & AC Logic Input Levels
Symbol
Parameter
DDR2-667, DDR2-800
DDR2-533, DDR2-400
Units
Min.
REF + 0.125
–0.3
REF + 0.200
Max.
Min.
REF + 0.125
–0.3
REF + 0.250
Max.
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic HIGH
DC input LOW
V
V
V
DDQ + 0.3
REF – 0.125
V
V
DDQ + 0.3
REF – 0.125
V
V
V
V
V
AC input logic HIGH
AC input LOW
V
—
V
—
—
V
REF – 0.200
—
VREF - 0.250
TABLE 25
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Notes
1)
VREF
Input reference voltage
0.5 x VDDQ
1.0
V
1)
VSWING.MAX
SLEW
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
V
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF
to VIL(ac).MAX for falling edges as shown in Figure 4
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
Rev. 1.50, 2007-12
29
03062006-7M17-PXBC
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 4
Single-ended AC Input Test Conditions Diagram
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TABLE 26
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
DC input signal voltage
Min.
Max.
Unit
Notes
1)
2)
3)
4)
5)
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
–0.3
V
V
V
DDQ + 0.3
—
—
V
DC differential input voltage
0.25
DDQ + 0.6
DDQ + 0.6
AC differential input voltage
0.5
AC differential cross point input voltage
0.5 × VDDQ – 0.175
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
AC differential cross point output voltage 0.5 × VDDQ – 0.125
V
1)
2)
3)
V
V
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
.
.
4) The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
FIGURE 5
Differential DC and AC Input and Output Logic Levels Diagram
9
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 27
SSTL_18 Output DC Current Drive
Symbol
Parameter
SSTL_18
Unit
Notes
1)2)
IOH
IOL
Output Minimum Source DC Current
Output Minimum Sink DC Current
–13.4
13.4
mA
mA
2)3)
1)
VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ – 280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN
plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
.
3)
VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
TABLE 28
SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18
Unit
Note
1)
VOH
VOL
Minimum Required Output Pull-up
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
V
V
V
1)
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
VOTR
1)SSTL_18 test load for VOH and VOL is different from the referenced load . The SSTL_18 test load has a 20 Ohm series resistor additionally
to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25 Ohm
termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement
of 603 mV swing relative to VTT, at the ouput device (13.4 mA × 45 Ohm = 603 mV).
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TABLE 29
OCD Default Characteristics
Symbol Description
Min.
Nominal
Max.
Unit
Notes
1)2)
—
Output Impedance
Ω
1)2)3)
4)
—
Pull-up / Pull down mismatch
Output Impedance step size for OCD calibration
Output Slew Rate
0
—
—
—
4
Ω
—
0
1.5
5.0
Ω
1)5)6)7)8)
SOUT
1.5
V / ns
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than 23.4
ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V;
V
OUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5)Slew Rates VIL(ac) to VIH(ac)
.
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS
specification.
8) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
This chapter contains the Input / Output Capacitance.
TABLE 30
Input / Output Capacitance
Symbol Parameter
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
CCK
CDCK
CI
Input capacitance, CK and CK
1.0
—
2.0
1.0
—
2.0
1.0
—
2.0
1.0
—
2.0
pF
pF
pF
Input capacitance delta, CK and CK
0.25
1.75
0.25
2.0
0.25
2.0
0.25
2.0
Input capacitance, all other input-only
pins
1.0
1.0
1.0
1.0
CDI
Input capacitance delta, all other input-
only pins
—
0.25
3.5
—
0.25
3.5
—
0.25
4.0
—
0.25
4.0
pF
pF
pF
CIO
Input/output capacitance,
DQ, DM, DQS, DQS
2.5
—
2.5
—
2.5
—
2.5
—
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS
0.5
0.5
0.5
0.5
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
5.6
Overshoot and Undershoot Specification
This chapter contains Overshoot and Undershoot Specification.
TABLE 31
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Unit
Maximum peak amplitude allowed for
overshoot area
0.9
0.9
0.9
0.9
V
Maximum peak amplitude allowed for
undershoot area
0.9
0.9
0.9
0.9
V
Maximum overshoot area above VDD
Maximum undershoot area below VSS
1.33
1.33
1.00
1.00
0.8
0.8
0.66
0.66
V-ns
V-ns
FIGURE 6
AC Overshoot / Undershoot Diagram for Address and Control Pins
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Rev. 1.50, 2007-12
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TABLE 32
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Unit
Maximum peak amplitude allowed for
overshoot area
0.9
0.9
0.9
0.9
V
Maximum peak amplitude allowed for
undershoot area
0.9
0.9
0.9
0.9
V
Maximum overshoot area above VDDQ
Maximum undershoot area below VSSQ
0.38
0.38
0.28
0.28
0.23
0.23
0.23
0.23
V-ns
V-ns
FIGURE 7
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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6
Currents Measurement Conditions
This chapter describes the Current Measurement, Specifications and Conditions.
TABLE 33
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)6)
Operating Current - One bank Active - Precharge
IDD0
t
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are switching; Databus inputs are switching.
1)2)3)4)5)6)
Operating Current - One bank Active - Read - Precharge
IDD1
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching;
Databus inputs are switching.
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
Precharge Power-Down Current
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs
are floating.
IDD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
IDD2N
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable,
Data bus inputs are floating.
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs
are floating. MRS A12 bit is set to 0 (Fast Power-down Exit).
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS
RAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
=
t
switching; Data Bus inputs are switching; IOUT = 0 mA.
1)2)3)4)5)6)
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS
=
t
RAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
1)2)3)4)5)6)
1)2)3)4)5)6)
Burst Refresh Current
IDD5B
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
IDD5D
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 μs interval, CKE is LOW and CS is HIGH between
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
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256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol Note
1)2)3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
1)2)3)4)5)6)
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK
=
t
CK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern: see Detailed IDD7 timings shown below.
1)
2)
3)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V.
I
I
DD specifications are tested after the device is properly initialized.
DD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for IDD , see Table 34.
6) Timing parameter minimum and maximum values for IDD current measurements are defined in Chapter 7.
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect.
IDD7 : Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC.IDD without violating tRRD.IDD using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0 mA.
DDR2-400 3-3-3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
DDR2-533 4-4-4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
DDR2-667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
DDR2-667 4-4-4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
DDR2-800 6-6-6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
DDR2-800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
TABLE 34
Definition for IDD
Parameter
Description
LOW
Defined as VIN ≤ VIL.AC.MAX
HIGH
Defined as VIN ≥ VIH.AC.MIN
STABLE
FLOATING
SWITCHING
Defined as inputs are stable at a HIGH or LOW level
Defined as inputs are VREF = VDDQ / 2
Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
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TABLE 35
DD Specification
I
Symbol
–25F
–2.5
–3
–3S
–3.7
–5
Unit
Note
DDR2-800D DDR2-800E DDR2-667C DDR2-667D DDR2-533C DDR2-400B
Max.
80
Max.
Max.
65
Max.
Max.
55
Max.
50
IDD0
IDD1
IDD2P
75
85
5.0
62
71
5.0
mA
mA
mA
mA
×4/×8/×16
×4/×8/×16
90
75
60
55
5.0
5.0
4.5
2.0
4.5
I
DD2P low
power
IDD2N
IDD2Q
50
35
22
50
45
45
35
25
16
4.5
35
90
115
95
130
90
6
28
20
13
4.5
30
70
90
75
105
85
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
35
30
30
1)
2)
I
I
DD3P_0 (fast)
22
19
19
DD3P_1 (slow) 5.0
5.0
50
5.0
45
5.0
45
IDD3N
IDD4R
IDD4R
IDD4W
IDD4W
IDD5B
IDD5D
IDD6
50
125
175
135
190
95
125
175
135
190
95
110
145
115
160
95
110
145
115
160
95
×4/×8
×16
×4/×8
×16
3)
3)
6
6
6
6
4.5
4.5
4.5
4.5
4.5
2.0
4.5
I
DD6 low
power
IDD7
165
180
155
170
145
165
138
157
135
150
125
140
mA
mA
×4/×8
×16
IDD7
1) MRS(12)=0
2) MRS(12)=1
3) 0° ≤ TCASE ≤ 85°C.
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7
Timing Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
7.1
Speed Grade Definitions
TABLE 36
Speed Grade Definition
Speed Grade
DDR2–800D
–25F
DDR2–800E
–2.5
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
5–5–5
Min.
6–6–6
tCK
Symbol
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period
@ CL = 3
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
@ CL = 4
@ CL = 5
@ CL = 6
tCK
3.75
2.5
2.5
45
8
3.75
3
8
tCK
8
8
tCK
8
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
tRAS
tRC
tRCD
tRP
70k
—
—
—
70k
—
—
—
57.5
12.5
12.5
Row Precharge Time
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TABLE 37
Speed Grade Definition
Speed Grade
DDR2–667C
–3
DDR2–667D
–3S
DDR2–533C
DDR2–400B Unit Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
–5
4–4–4
5–5–5
4–4–4
Min.
3–3–3
Min.
tCK
Symbol Min.
Max.
Min.
Max.
Max.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period @ CL = 3
@ CL = 4
tCK
5
8
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3
8
3.75
3
8
3.75
3.75
45
8
5
8
@ CL = 5
tCK
3
8
8
8
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70k
—
—
—
45
60
15
15
70k
—
—
—
70k
—
—
—
40
55
15
15
70k
—
—
—
60
15
15
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. .
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
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7.2
Component AC Timing Parameters
TABLE 38
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
8)
DQ output access time from CK / CK tAC
–400
2
+400
—
–450
2
+450
—
ps
CAS to CAS command delay
Average clock high pulse width
Average clock period
tCCD
tCH.AVG
tCK.AVG
nCK
tCK.AVG
ps
9)10)
11)
0.48
2500
3
0.52
8000
—
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and tCKE
nCK
low pulse width)
9)10)
Average clock low pulse width
tCL.AVG
tDAL
0.48
0.52
—
0.48
0.52
—
tCK.AVG
12)13)
Auto-Precharge write recovery +
precharge time
WR + tnRP
WR + tnRP
nCK
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
tIS + tCK .AVG ––
+ tIH
tIS +
tCK .AVG + tIH
––
ns
14)18)19)
DQ and DM input hold time
tDH.BASE
125
––
—
175
––
—
ps
DQ and DM input pulse width for each tDIPW
0.35
0.35
tCK.AVG
input
8)
DQS output access time from CK / CK tDQSCK
–350
0.35
0.35
—
+350
—
–400
0.35
0.35
—
+400
—
ps
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tCK.AVG
tCK.AVG
ps
—
—
15)
16)
DQS-DQ skew for DQS & associated tDQSQ
DQ signals
200
240
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK.AVG
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
50
––
—
—
__
100
––
—
—
__
ps
DQS falling edge hold time from CK tDSH
0.2
0.2
tCK.AVG
tCK.AVG
ps
16)
DQS falling edge to CK setup time
CK half pulse width
tDSS
tHP
0.2
0.2
20)
Min(tCH.ABS
,
Min(tCH.ABS,
tCL.ABS
)
tCL.ABS)
8)21)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
22)24)
Address and control input hold time tIH.BASE
250
0.6
—
—
275
0.6
—
—
ps
Control & address input pulse width tIPW
tCK.AVG
for each input
23)24)
8)21)
8)21)
Address and control input setup time tIS.BASE
DQ low impedance time from CK/CK tLZ.DQ
175
—
200
—
ps
ps
ps
2 x tAC.MIN
tAC.MAX
tAC.MAX
2 x tAC.MIN
tAC.MAX
tAC.MAX
DQS/DQS low-impedance time from tLZ.DQS
tAC.MIN
tAC.MIN
CK / CK
34)
MRS command to ODT update delay tMOD
0
12
0
12
ns
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256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol DDR2–800
Min.
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Max.
Min.
Max.
Mode register set command cycle
time
tMRD
2
—
2
—
nCK
34)
OCD drive mode output delay
tOIT
0
12
0
12
ns
ps
ps
μs
μs
ns
25)
DQ/DQS output hold time from DQS tQH
t
HP – tQHS
—
t
HP – tQHS
—
26)
DQ hold skew factor
tQHS
tREFI
—
—
—
75
300
7.8
3.9
—
—
—
—
75
340
7.8
3.9
—
27)28)
27)29)
30)
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh tRFC
command period
31)32)
31)33)
34)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
7.5
1.1
0.6
—
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Active to active command period for tRRD
1KB page size products
34)
Internal Read to Precharge command tRTP
7.5
—
7.5
—
ns
delay
Write preamble
tWPRE
tWPST
tWR
0.35
0.4
—
0.6
—
—
—
—
0.35
0.4
—
0.6
—
—
—
—
tCK.AVG
tCK.AVG
ns
Write postamble
Write recovery time
34)
15
15
34)35)
Internal write to read command delay tWTR
Exit power down to read command tXARD
7.5
7.5
ns
2
2
nCK
nCK
Exit active power-down mode to read tXARDS
8 – AL
7 – AL
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
nCK
ns
34)
Exit self-refresh to a non-read
command
tXSNR
t
RFC +10
—
—
t
RFC +10
—
—
Exit self-refresh to read command
tXSRD
200
200
nCK
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the Reference Load for Timing Measurements.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
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8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
t
DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and
these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between
the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
of Chapter 7.3).
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
V
IH.DC.MIN. See Figure 9.
15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 9.
18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
22) input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 10.
23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 10.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
28) 0 °C≤ TCASE ≤ 85 °C.
29) 85 °C < TCASE ≤ 95 °C.
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256-Mbit Double-Data-Rate-Two SDRAM
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x tREFI
.
31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 8 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
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256-Mbit Double-Data-Rate-Two SDRAM
TABLE 39
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes1)2)
3)4)5)6)
Min.
Max.
Min.
Max.
DQ output access time from CK / CK tAC
CAS A to CAS B command period tCCD
–500
2
+500
—
–600
2
+600
—
ps
tCK
tCK
tCK
CK, CK high-level width
tCH
0.45
3
0.55
—
0.45
3
0.55
—
CKE minimum high and low pulse
width
tCKE
CK, CK low-level width
tCL
0.45
0.55
—
0.45
0.55
—
tCK
tCK
7)
8)
Auto-Precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK + tIH ––
tIS + tCK + tIH ––
ns
9)
DQ and DM input hold time
(differential data strobe)
tDH.BASE
225
–25
0.35
–450
0.35
0.35
—
––
275
25
––
ps
ps
tCK
ps
tCK
tCK
ps
tCK
ps
ps
tCK
tCK
10)
DQ and DM input hold time (single tDH1.BASE
ended data strobe)
—
—
DQ and DM input pulse width (each tDIPW
input)
—
0.35
–500
0.35
0.35
—
—
DQS output access time from CK / tDQSCK
CK
+450
—
+500
—
DQS input HIGH pulse width (write tDQSH
cycle)
DQS input LOW pulse width (write tDQSL
cycle)
—
—
10)
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
300
+ 0.25
—
350
+ 0.25
—
Write command to 1st DQS latching tDQSS
transition
– 0.25
100
–25
0.2
– 0.25
150
25
10)
10)
DQ and DM input setup time
(differential data strobe)
tDS.BASE
DQ and DM input setup time (single tDS1.BASE
ended data strobe)
—
—
DQS falling edge hold time from CK tDSH
(write cycle)
—
0.2
—
DQS falling edge to CK setup time tDSS
0.2
—
0.2
—
(write cycle)
11)
12)
Clock half period
tHP
MIN. (tCL, tCH
)
MIN. (tCL, tCH)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
ps
10)
Address and control input hold time tIH.BASE
375
—
475
—
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256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes1)2)
3)4)5)6)
Min.
Max.
Min.
Max.
Address and control input pulse
tIPW
0.6
—
0.6
—
tCK
width
(each input)
10)
13)
Address and control input setup time tIS.BASE
250
—
350
—
ps
ps
DQ low-impedance time from CK / tLZ(DQ)
2 × tAC.MIN
tAC.MAX
2 × tAC.MIN
tAC.MAX
CK
13)
DQS low-impedance from CK / CK tLZ(DQS)
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MAX
ps
ns
MRS command to ODT update
delay
tMOD
0
12
0
12
Mode register set command cycle
time
tMRD
2
0
—
2
0
—
tCK
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
tOIT
12
12
ns
tQH
t
HP –tQHS
—
t
HP –tQHS
—
tQHS
tREFI
tREFI
tRFC
—
—
—
75
400
7.8
3.9
—
—
—
450
7.8
3.9
—
ps
μs
μs
ns
13)14)
15)17)
16)
Average periodic refresh Interval
Average periodic refresh Interval
—
Auto-Refresh to Active/Auto-
Refresh command period
75
13)
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
1.1
0.60
—
0.9
1.1
0.60
—
tCK
tCK
ns
13)
0.40
7.5
0.40
7.5
13)17)
Active bank A to Active bank B
command period for 1 KB page size
Internal Read to Precharge
command delay
tRTP
7.5
—
7.5
—
ns
Write preamble
Write postamble
tWPRE
tWPST
0.25
0.40
15
—
0.25
0.40
15
—
tCK
tCK
ns
18)
0.60
—
0.60
—
Write recovery time for write without tWR
Auto-Precharge
19)
20)
Internal Write to Read command
delay
tWTR
7.5
2
—
—
10
2
—
—
ns
Exit power down to any valid
command
tXARD
tCK
(other than NOP or Deselect)
20)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
6 – AL
2
—
—
—
6 – AL
2
—
—
—
tCK
tCK
ns
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
Exit Self-Refresh to non-Read
command
tXSNR
t
RFC +10
tRFC +10
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes1)2)
3)4)5)6)
Min.
Max.
Min.
Max.
Exit Self-Refresh to Read command tXSRD
200
—
200
—
tCK
tCK
21)
Write recovery time for write with
Auto-Precharge
WR
t
WR/tCK
tWR/tCK
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. . Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the Reference Load for Timing Measurements .
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. .
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ TCASE ≤ 85 °C.
15) 85 °C < TCASE ≤ 95 °C.
16) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x tREFI
.
17) The tRRD timing parameter depends on the page size of the DRAM organization.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 8
Method for Calculating Transitions and Endpoint
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ꢆꢏ
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FIGURE 9
Differential Input Waveform Timing - tDS and tDH
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W'6
W'+
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Rev. 1.50, 2007-12
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 10
Differential Input Waveform Timing - tlS and tlH
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&.
W,6
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W,6
W,+
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Rev. 1.50, 2007-12
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
7.3
Jitter Definition and Clock Jitter Specification
Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table
provides an overview of the terminology.
TABLE 40
Average Clock and Jitter Symbols and Definition
Symbol
Parameter
Description
Units
tCK.AVG
Average clock period tCK.AVG is calculated as the average clock period within any consecutive ps
200-cycle window:
ꢈ
ꢇ
ꢃ
ꢉꢉꢉꢉ
ꢈ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁ ꢂꢊ
ꢊ
ꢀ
ꢇ
N = 200
tJIT.PER
Clock-period jitter
t
t
JIT.PER is defined as the largest deviation of any single tCK from tCK.AVG
JIT.PER = Min/Max of {tCKi – tCK.AVG} where i = 1 to 200
:
ps
t
t
JIT.PER defines the single-period jitter when the DLL is already locked.
JIT.PER is not guaranteed through final production testing.
t
JIT(PER, LCK)
Clock-period jitter
during DLL-locking
period
t
JIT(PER,LCK) uses the same definition as tJIT.PER, during the DLL-locking ps
period only.
t
JIT(PER,LCK) is not guaranteed through final production testing.
tJIT.CC
Cycle-to-cycle clock
period jitter
t
JIT.CC is defined as the absolute difference in clock period between two ps
consecutive clock cycles:
t
JIT.CC = Max of ABS{tCKi+1 – tCKi}
t
t
JIT.CC defines the cycle - to - cycle jitter when the DLL is already locked.
JIT.CC is not guaranteed through final production testing.
t
JIT(CC, LCK)
Cycle-to-cycle clock
period jitter during
DLL-locking period
t
JIT(CC,LCK) uses the same definition as tJIT.CC during the DLL-locking
ps
period only.
t
JIT(CC,LCK) is not guaranteed through final production testing.
tERR.2PER
Cumulative error
across 2 cycles
t
ERR.2PER is defined as the cumulative error across 2 consecutive cycles ps
from tCK.AVG
:
ꢇ
ꢀ
ꢎ
ꢂ
ꢈ
ꢋꢀꢁ ꢁ ꢂ ꢌꢃ ꢍ
ꢁ
ꢋꢄ ꢅꢆ
ꢂ
ꢎ
ꢋ ꢄꢅ ꢉꢏ ꢊ
ꢆ
ꢁ
ꢇ
n = 2 for tERR(2per)
where i = 1 to 200
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HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Symbol
Parameter
Description
Units
tERR.nPER
Cumulative error
across n cycles
t
ERR.2PER is defined as the cumulative error across n consecutive cycles ps
from tCK.AVG
:
ꢉ
ꢀ
ꢂ
ꢂ
ꢊ
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ꢁ
ꢆꢇ ꢈꢊ
ꢂ
ꢂ
ꢆ ꢇꢈ ꢋꢌ ꢍ
ꢊ
ꢁ
ꢉ
where, i = 1 to 200 and
n = 3 for tERR.3PER
n = 4 for tERR.4PER
n = 5 for tERR.5PER
6 ≤ n ≤ 10 for tERR.6-10PER
11 ≤ n ≤ 50 for tERR.11-50PER
tCH.AVG
Average high-pulse
width
t
CH.AVG is defined as the average high-pulse width, as calculated across tCK.AVG
any consecutive 200 high pulses:
ꢅ
ꢇ
ꢃ
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ꢀ
ꢀꢀ ꢁꢊ
ꢅ
ꢀ ꢀꢆ ꢂꢃ ꢄ
ꢊ
ꢀ
ꢇ
N = 200
tCL.AVG
Average low-pulse
width
t
CL.AVG is defined as the average low-pulse width, as calculated across any tCK.AVG
consecutive 200 low pulses:
ꢄ
ꢇ
ꢃ
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N = 200
tJIT.DUTY
Duty-cycle jitter
t
t
t
t
t
JIT.DUTY = Min/Max of {tJIT.CH , tJIT.CL}, where:
ps
JIT.CH is the largest deviation of any single tCH from tCH.AVG
JIT.CL is the largest deviation of any single tCL from tCL.AVG
JIT.CH = {tCHi - tCH.AVG × tCK.AVG} where i=1 to 200
JIT.CL = {tCLi - tCL.AVG × tCK.AVG} where i=1 to 200
The following parameters are specified per their average values however, it is understood that the following relationship
between the average timing and the absolute instantaneous timing holds all the time.
Rev. 1.50, 2007-12
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03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 41
Absolute Jitter Value Definitions
Symbol Parameter
Min.
Max.
Unit
tCK.ABS
tCH.ABS
Clock period
t
t
CK.AVG(Min) + tJIT.PER(Min)
t
CK.AVG(Max) + tJIT.PER(Max)
CH.AVG(Max) x tCK.AVG(Max) +
ps
ps
Clock high-pulse width
CH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min)
t
tJIT.DUTY(Max)
tCL.ABS
Clock low-pulse width
tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max)
+
ps
tJIT.DUTY(Max)
Example: for DDR2-667, tCH.ABS.MIN = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.
Table 42 shows clock-jitter specifications.
TABLE 42
Clock-Jitter Specifications for –667, –800
Symbol
Parameter
DDR2 -667
Min.
DDR2 -800
Unit
Max.
Min.
Max.
tCK.AVG
Average clock period nominal w/o jitter
Clock-period jitter
3000
–125
–100
8000
+125
+100
2500
–100
–80
8000
+100
+80
ps
ps
ps
tJIT.PER
tJIT(PER,LCK)
Clock-period jitter during DLL locking
period
tJIT.CC
Cycle-to-cycle clock-period jitter
–250
–200
+250
+200
–200
–160
+200
+160
ps
ps
tJIT(CC,LCK)
Cycle-to-cycle clock-period jitter during
DLL-locking period
tERR.2PER
tERR.3PER
tERR.4PER
tERR.5PER
tERR(6-10PER)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
–175
–225
–250
–250
+175
+225
+250
+250
+350
–150
–175
–200
–200
–300
+150
+175
+200
+200
+300
ps
ps
ps
ps
ps
Cumulative error across n cycles with n = 6 –350
.. 10, inclusive
tERR(11-50PER)
Cumulative error across n cycles with n = –450
11 .. 50, inclusive
+450
–450
+450
ps
tCH.AVG
tCL.AVG
tJIT.DUTY
Average high-pulse width
Average low-pulse width
Duty-cycle jitter
0.48
0.48
–125
0.52
0.52
+125
0.48
0.48
–100
0.52
0.52
+100
tCK.AVG
tCK.AVG
ps
Rev. 1.50, 2007-12
52
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
7.4
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 43
ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800 Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800 tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed,
t
AOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
Rev. 1.50, 2007-12
53
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 44
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.50, 2007-12
54
03062006-7M17-PXBC
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
8
Package Outline
This chapter contains the package dimension figures.
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
FIGURE 11
Package Outline P-TFBGA-60
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Rev. 1.50, 2007-12
55
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 12
Package Outline P-TFBGA-84
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Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 13
Package Outline PG-TFBGA-84
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03062006-7M17-PXBC
57
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
9
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
TABLE 45
Examples for Nomenclature Fields
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
DDR2 DRAM
HYB
18
T
256
16
0
A
C
–3.7
TABLE 46
DDR2 Memory Components
Field Description
Values
Coding
Memory components
1
Qimonda Component Prefix
HYB
HYI
18
Memory components, industrial temperature range (-40°C – +85 °C)
2
Interface Voltage [V]
SSTL_18, + 1.8 V (± 0.1 V)
15
SSTL_15, + 1.5 V (± 0.1 V)
3
4
DRAM Technology
T
DDR2
32 Mbit
64 Mbit
128 Mbit
256 Mbit
512 Mbit
1 Gbit
Component Density [Mbit]
32
64
128
256
512
1G
2G
4G
40
2 Gbit
4 Gbit
5
Number of I/Os
× 4
80
× 8
16
× 16
32
× 32
6
7
Product Variations
Die Revision
0 .. 9
look up table
A ( 0...9 ) First
B ( 0...9 ) Second
C ( 0...9 ) Third
8
9
Package,
Lead-Free Status
C
F
–
FBGA, lead-containing
FBGA, lead-free
Power
Standard power product
Low power product
L
Rev. 1.50, 2007-12
58
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Field Description
10 Speed Grade
Values
Coding
–19F
–1.9
–25F
–2.5
–3
DDR2–1066 6–6–6
DDR2–1066 7–7–7
DDR2–800 5–5–5
DDR2–800 6–6–6
DDR2–667 4–4–4
DDR2–667 5–5–5
DDR2–533 4–4–4
DDR2–400 3–3–3
–3S
–3.7
–5
Rev. 1.50, 2007-12
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03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Chip Configuration for ×4 components, TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Configuration for ×8 components, TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Configuration for ×16 components, TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 35
Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Differential Input Waveform Timing - tDS and tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Differential Input Waveform Timing - tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Package Outline P-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Package Outline P-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Package Outline PG-TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Rev. 1.50, 2007-12
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03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Performance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for non RoHS Compliant Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
256 Mb DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register Definition, BA2:0 = 000B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Extended Mode Register Definition, BA2:0 = 001B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EMR(2) Programming Extended Mode Register Definition, BA2:0=010B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EMR(3) Programming Extended Mode Register Definition, BA2:0=011B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Enable (CKE) Truth Table for Synchronous Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 35
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
I
DD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667 . . . . . . . . . . . . . . . . . . 41
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400 . . . . . . . . . . . . . . . . . . 45
Average Clock and Jitter Symbols and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Absolute Jitter Value Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock-Jitter Specifications for –667, –800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . 53
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 54
Examples for Nomenclature Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Rev. 1.50, 2007-12
61
03062006-7M17-PXBC
Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Configuration for TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Configuration for TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1
2.2
2.3
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Extended Mode Register EMR(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Extended Mode Register EMR(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Extended Mode Register EMR(3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
3.2
3.3
3.4
3.5
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input / Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Overshoot and Undershoot Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1
5.2
5.3
5.4
5.5
5.6
6
Currents Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Jitter Definition and Clock Jitter Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1
7.2
7.3
7.4
8
9
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Product Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Rev. 1.50, 2007-12
62
03062006-7M17-PXBC
Internet Data Sheet
Edition 2007-12
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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