HYB18T4G802AF-2.5_技术文档

April 2008

HYB18T4G402AF

HYB18T4G802AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

DDR2 SDRAM

RoHS Compliant Products

Internet Data Sheet

Rev. 1.00

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Revision History: Rev. 1.00, 2008-04

Adapted internet edition

Final revision

Previous Revision: Rev. 0.50, 2008-02

First revision

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

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qag_techdoc_A4, 4.20, 2008-01-25

07192007-CK80-SF4Y

2

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

1

Overview

This chapter gives an overview of the 4-Gbit Double-Data-Rate-Two SDRAM product family and describes its main

characteristics.

1.1

Features

The 4-Gbit Double-Data-Rate-Two SDRAM offers the following key features:

•

1.8 V ± 0.1 V Power Supply

•

Off-Chip-Driver impedance adjustment (OCD) and

On-Die-Termination (ODT) for better signal quality

Auto-Precharge operation for read and write bursts

Auto-Refresh, Self-Refresh and power saving Power-

Down modes

1.8 V ± 0.1 V (SSTL_18) compatible I/O

DRAM organizations with 4,8 data in/outputs

Double Data Rate architecture:

•

– two data transfers per clock cycle

– eight internal banks for concurrent operation

Programmable CAS Latency: 3, 4, 5, 6 and 7

Programmable Burst Length: 4 and 8

•

Operating temperature range 0 °C to 95 °C

Average Refresh Period 7.8 µs at a T_CASElower

than 85 °C, 3.9 µs between 85 °C and 95 °C

Programmable self refresh rate via EMRS2 setting

Programmable partial array refresh via EMRS2 settings

DCC enabling via EMRS2 setting

•

Differential clock inputs (CK and CK)

•

Bi-directional, differential data strobes (DQS and DQS) are

transmitted / received with data. Edge aligned with read

data and center-aligned with write data.

DLL aligns DQ and DQS transitions with clock

DQS can be disabled for single-ended data strobe

operation

Full and reduced Strength Data-Output Drivers

1KB page size for ×4 and ×8

•

Packages: PG-TFBGA-71

RoHS Compliant Products¹⁾

•

Commands entered on each positive clock edge, data and

data mask are referenced to both edges of DQS

Data masks (DM) for write data

Posted CAS by programmable additive latency for better

command and data bus efficiency

All Speed grades faster than DDR2–400 comply with

DDR2–400 timing specifications when run at a clock rate

of 200 MHz.

•

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

For more information please visit www.qimonda.com/green_products.

Rev. 1.00, 2008-04

3

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 1

Performance Table

QAG Speed Code

–25F

–2.5

–3S

–3.7

Unit

Note

DRAM Speed Grade

DDR2

–800D

5–5–5

–800E

6–6–6

–667D

5–5–5

–533C

4–4–4

CAS-RCD-RP latencies

t_CK

Max. Clock Frequency

CL3

CL4

CL5

CL6

f_CK3

f_CK4

f_CK5

f_CK6

t_RCD

t_RP

t_RAS

t_RC

t_PREA

200

266

400

–

12.5

45

200

266

333

400

15

45

60

17.5

200

266

333

–

15

45

60

18

200

266

–

15

45

60

18.75

MHz

ns

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

Precharge-All (8 banks) command

period

57.5

15

1)2)

1) This t_PREAvalue is the minimum value at which this chip will be functional.

2) Precharge-All command for an 8 bank device will equal to t_RP+ 1 × t_CKor t_nRP+ 1 × nCK, depending on the speed bin,

where t_nRP= RU{ t_RP/ t_CK(avg)} and t_RPis the value for a single bank precharge.

1.2

Description

The 4-Gbit DDR2 DRAM consists of two 2-Gbit Double Data-

Rate-Two dies in one package. Each 2-Gbit device is

organized as 64 Mbit ×4 I/O ×8 banks or 32 Mbit ×8 I/O ×8

banks chip.

These synchronous devices achieve high speed transfer

rates starting at 400 Mb/sec/pin for general applications. See

Table 1 for performance figures.

The device is designed to comply with all DDR2 DRAM key

features:

1. Posted CAS with additive latency.

2. Write latency = read latency - 1.

3. Normal and weak strength data-output driver.

4. Off-Chip Driver (OCD) impedance adjustment.

5. On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS-DQS pair in a source synchronous

fashion.

A 18 bit address bus for ×4 and ×8 organised components is

used to convey row, column and bank address information in

a RAS-CAS multiplexing style.

Since dual-die components share the same DQ bus, each of

the two 2-Gbit dies can be individually selected by its own CS,

CKE and ODT signal. All other signals are common for both

dies.

The DDR2 device operates with a 1.8 V ± 0.1 V power

supply. An Auto-Refresh and Self-Refresh mode is provided

along with various power-saving power-down modes.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

The DDR2 SDRAM is available in TFBGA package.

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Org. Speed

CAS-RCD-RP Clock (MHz) Package

Note⁵⁾

Latencies²⁾³⁾⁴⁾

Standard Temperature Range (0 °C - 95 °C)

DDR2-800E( 6-6-6 )

HYB18T4G802AF-2.5

HYB18T4G402AF-2.5

DDR2-800D( 5-5-5 )

HYB18T4G802AF-25F

HYB18T4G402AF-25F

DDR2-667D( 5-5-5 )

HYB18T4G402AF-3S

HYB18T4G802AF-3S

DDR2-533C( 4-4-4 )

HYB18T4G802AF-3.7

HYB18T4G402AF-3.7

×8

×4

DDR2-800E 6-6-6

400

PG-TFBGA-71

×8

×4

DDR2-800D 5-5-5

400

PG-TFBGA-71

×4

×8

DDR2-667D 5-5-5

333

PG-TFBGA-71

×8

×4

DDR2-533C 4-4-4

266

PG-TFBGA-71

1) For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet.

2) CAS: Column Address Strobe

3) RCD: Row Column Delay

4) RP: Row Precharge

5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit

www.qimonda.com/green_products.

Rev. 1.00, 2008-04

5

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

2

Configuration

This chapter contains the chip configuration.

2.1

Configuration for FBGA-71

The chip configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Ball# Type columns

are explained in Table 4 and Table 5 respectively. The ball numbering for the FBGA package is depicted in Figures.

TABLE 3

Configuration

Ball#

Name

Ball

Buffer

Type

Function

Type

Clock Signals ×4 /×8 Organizations

J8

CK

CKE0

CKE1

I

SSTL

Clock Signal CK, CK

Clock Enable

K8

K2

M1

Control Signals ×4 /×8 Organizations

K7

L7

K3

L8

L9

RAS

CAS

WE

CS0

CS1

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS),

Write Enable (WE)

Chip Select

Address Signals ×4 /×8 Organizations

L2

L3

L1

BA0

BA1

BA2

I

SSTL

Bank Address Bus 2:0

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Ball#

Name

Ball

Buffer

Type

Function

Type

M8

M3

M7

N2

N8

N3

N7

P2

P8

P3

M2

A0

A1

A2

A3

A4

A5

A6

A7

I

SSTL

Address Signal 14:0, Address Signal 10/Autoprecharge

A8

A9

A10

AP

A11

A12

A13

A14

P7

R2

R8

R3

Data Signals ×4 Organization

G8

G2

H7

H3

DQ0

DQ1

DQ2

DQ3

I/O

SSTL

Data Signal 3:0

Data Signal 7:0

Data Signals × 8 Organization

G8

G2

H7

H3

H1

H9

F1

F9

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Strobe ×4 /×8 Organizations

F7

E8

DQS

I/O

SSTL

Data Strobe

Data Strobe ×8 Organization

F3

E2

RDQS

O

SSTL

Read Data Strobe

Data Mask

Data Mask ×4 /×8 Organizations

F3 DM

I

SSTL

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Ball#

Name

Ball

Buffer

Type

Function

Type

Power Supplies ×4 /×8 Organizations

G1, G3, E9, G7, V_DDQ

PWR

–

I/O Driver Power Supply

G9

E1, R1, J9, M9 V_DD

PWR

–

Power Supply

I/O Driver Power Supply

F2, H2, E7, F8, V_SSQ

H8

E3, J3, N1, P9 V_SS

PWR

Al

PWR

–

Power Supply

I/O Reference Voltage

Power Supply

J2

J1

J7

V_REF

V_DDL

V_SSDL

Power Supply

Not Connected ×4 Organization

E2, F1, H1, H9, NC

R7, F9, A1, A2,

A8, A9, W1,

NC

–

Not Connected

W2, W8, W9

Not Connected ×8 Organization

R7, A1, A2, A8, NC

A9, W1, W2,

W8, W9

NC

–

Not Connected

Other Balls ×4 /×8 Organizations

K9

N9

ODT0

ODT1

I

SSTL

On-Die Termination Control

TABLE 4

Abbreviations for Ball Type

Abbreviation

Description

I

O

Standard input-only ball. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

I/O

AI

PWR

GND

NC

Ground

Not Connected

TABLE 5

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

LV-CMOS

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Abbreviation

Description

CMOS

OD

CMOS Levels

Open Drain. The corresponding ball has 2 operational states, active low and tristate, and

allows multiple devices to share as a wire-OR.

FIGURE 1

Configuration for x 4 Component, TFBGA-71 (Top View)

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Note: V_DDLand V_SSDLare power and ground for the DLL. V_DDLis connected to V_DDon the device. V_DD, V_DDQ, V_SSDL, V_SS, and

_SSQare isolated on the device.

V

Rev. 1.00, 2008-04

9

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

FIGURE 2

Configuration for x 8 Component, TFBGA-71 (Top View)

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Notes

1. RDQS / RDQS are enabled by EMRS(1) command.

2. If RDQS / RDQS is enabled, the DM function is disabled

3. When enabled, RDQS & RDQS are used as strobe signals during reads.

4. V_DDLand V_SSDLare power and ground for the DLL. They are connected on the device from V_DD, V_DDQ, V_SSand V_SSQ

.

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

2.2

Addressing

This chapter describes the DDR2 addressing.

TABLE 6

Addressing

Note

Configuration

2 x 512 Mb x 4¹⁾

2 x 256 Mb x 8²⁾

Number of Dies

Bank Address

Number of Banks

Auto Precharge

Row Address

Column Address

Chip Select

Number of Column Address Bits

Number of I/Os

2

BA[2:0]

8

BA[2:0]

8

A10 / AP

A[14:0]

A11, A[9:0]

CS[1:0]

11

A10 / AP

A[14:0]

A[9:0]

CS[1:0]

10

3)

4)

4

8

Page Size [Bytes]

1024 (1 K)

1) Referred to as ’org’

2) Referred to as ’org’

3) Referred to as ’colbits’

4) PageSize = 2^colbits× org/8 [Bytes]

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

3

Functional Description

This chapter contains the functional description.

3.1

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM.

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TABLE 7

Mode Register Definition, BA_2:0= 000_B

Field

Bits

Type¹⁾

Description

BA2

BA1

BA0

17

16

15

reg. addr.

Bank Address

0_B

BA2 Bank Address 2

BA1 Bank Address 1

BA0 Bank Address 0

A14

A13

14

13

Address Bus

0_B

A14 Address bit 14

A13 Address bit 13

PD

12

w

Active Power-Down Mode Select

0_B

1_B

PD Fast exit

PD Slow exit

WR

[11:9]

Write Recovery²⁾

Note: All other bit combinations are illegal.

001_BWR 2

010_BWR 3

011_BWR 4

100_BWR 5

101_BWR 6

DLL

TM

8

7

w

DLL Reset

0_B

1_B

DLL No

DLL Yes

Test Mode

0_B

1_B

TM Normal Mode

TM Vendor specific test mode

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Field

Bits

Type¹⁾

Description

CL

[6:4]

w

CAS Latency

Note: All other bit combinations are illegal.

011_BCL 3

100_BCL 4

101_BCL 5

110_BCL 6

111_BCL 7

BT

BL

3

w

Burst Type

0_B

1_B

BT Sequential

BT Interleaved

Burst Length

[2:0]

Note: All other bit combinations are illegal.

010_BBL 4

011_BBL 8

1) w = write only register bits

2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t_WR(in ns) by t_CK(in ns) and

rounding up to the next integer: WR [cycles] ≥ t_WR(ns) / t_CK(ns). The mode register must be programmed to fulfill the minimum requirement

for the analogue t_WRtiming WR_MINis determined by t_CK.MAXand WR_MAXis determined by t_CK.MIN

.

Rev. 1.00, 2008-04

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

3.2

Extended Mode Register EMR(1)

The Extended Mode Register EMR(1) stores the data for

enabling or disabling the DLL, output driver strength, additive

latency, OCD program, ODT, DQS and output buffers

disable, RDQS and RDQS enable.

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TABLE 8

Extended Mode Register Definition, BA_2:0= 001_B

Field

Bits Type¹⁾

Description

BA2

BA1

BA0

17

16

15

reg. addr.

Bank Address

0_B

BA2 Bank Address 2

BA1 Bank Address 1

BA1 Bank Address 0

A14

A13

14

13

w

Address Bus

0_B

A14 Address bit 14

A13 Address bit 13

Qoff

12

w

Output Disable

0_B

1_B

QOff Output buffers enabled

QOff Output buffers disabled

RDQS

DQS

11

Read Data Strobe Output (RDQS, RDQS)

0_B

1_B

RDQS Disable

RDQS Enable

10

Complement Data Strobe (DQS Output)

0_B

1_B

DQS Enable

DQS Disable

OCD

Program

[9:7]

Off-Chip Driver Calibration Program

000_BOCD OCD calibration mode exit, maintain setting

001_BOCD Drive (1)

010_BOCD Drive (0)

100_BOCD Adjust mode

111_BOCD OCD calibration default

AL

[5:3]

w

Additive Latency

Note: All other bit combinations are illegal.

000_BAL 0

001_BAL 1

010_BAL 2

011_BAL 3

100_BAL 4

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Field

Bits Type¹⁾

Description

R_TT

6,2

w

Nominal Termination Resistance of ODT

Note: See Table 18 “ODT DC Electrical Characteristics” on Page 22

00_BRTT ∞ (ODT disabled)

01_BRTT 75 Ohm

10_BRTT 150 Ohm

11_BRTT 50 Ohm

DIC

DLL

1

0

w

Off-chip Driver Impedance Control

0_B

1_B

DIC Full (Driver Size = 100%)

DIC Reduced

DLL Enable

0_B

1_B

DLL Enable

DLL Disable

1) w = write only register bits

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

3.3

Extended Mode Register EMR(2)

The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the

mode register during initialization.

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TABLE 9

EMR(2) Programming Extended Mode Register Definition, BA_2:0=010_B

Description

Field Bits

Type¹⁾

BA2

16

w

Bank Address

0_B

BA2 Bank Address

BA

[15:14]

w

Bank Adress

00_BBA MRS

01_BBA EMRS(1)

10_BBA EMRS(2)

11_BBA EMRS(3): Reserved

A

[14:8]

7

w

Address Bus

0000000_BA Address bits

SRF

Address Bus, High Temperature Self Refresh Rate for T_CASE> 85°C

0_B

1_B

A7 disable

A7 enable ²⁾

A

[6:4]

3

w

Address Bus

000_BA Address bits

DCC

Address Bus, Duty Cycle Correction (DCC)

0_B

1_B

A3 DCC disabled

A3 DCC enabled

Partial Self Refresh for 8 banks

PASR [2:0]

w

Address Bus, Partial Array Self Refresh for 8 Banks³⁾

Note: Only for 1G and 2G components

000_BPASR0 Full Array

001_BPASR1 Half Array (BA[2:0]=000, 001, 010 & 011)

010_BPASR2 Quarter Array (BA[2:0]=000, 001)

011_BPASR3 1/8 array (BA[2:0] = 000)

100_BPASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)

101_BPASR5 Half array (BA[2:0]=100, 101, 110 & 111)

110_BPASR6 Quarter array (BA[2:0]= 110 & 111)

111_BPASR7 1/8 array(BA[2:0]=111)

1) w = write only

2) When DRAM is operated at 85°C ≤ T_Case≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to 1 before the self refresh

mode can be entered.

3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh

is entered. Data integrity will be maintained if t_REFconditions are met and no Self Refresh command is issued.

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3.4

Extended Mode Register EMR(3)

The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0

when setting the mode register during initialization.

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TABLE 10

EMR(3) Programming Extended Mode Register Definition, BA_2:0=011_B

Description

Field

Bits

Type¹⁾

BA2

16

reg.addr

Bank Address 2

0_B

BA2 Bank Address

BA1

BA0

A

15

Bank Adress 1

1_B

BA1 Bank Address

14

Bank Adress 0

1_B

BA0 Bank Address

[14:0]

w

Address Bus

000000000000000_BA[14:0] Address bits

1) w = write only

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3.5

Burst Mode Operation

TABLE 11

Burst Length and Sequence

Burst Length

Starting Address

(A2 A1 A0)

Sequential Addressing

Interleave Addressing

(decimal)

4

× 0 0

× 0 1

×1 0

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

×1 1

3, 0, 1, 2

3, 2, 1, 0

8

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

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4

Truth Tables

The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two

SDRAM.

TABLE 12

Command Truth Table

Function

CKE

CS RAS CAS WE BA0 A[14:11] A10 A[9:0]

Note¹⁾²⁾³⁾

BA1

BA2

Previous Current

Cycle

4)5)6)

4)

(Extended) Mode Register Set H

H

L

H

L

H

L

H

L

X

H

L

H

X

H

X

H

L

X

H

L

H

X

H

X

H

L

BA OP Code

Auto-Refresh

Self-Refresh Entry

Self-Refresh Exit

H

L

H

X

H

L

H

L

X

4)7)

4)7)8)

H

4)5)

Single Bank Precharge

Precharge all Banks

Bank Activate

H

X

L

BA

X

L

H

X

4)5)

BA Row Address

4)5)9)

4)

Write

BA Column

L

H

L

H

X

Column

X

Write with Auto-Precharge

Read

Read with Auto-Precharge

No Operation

Device Deselect

Power Down Entry

L

H

X

H

X

H

X

4)

X

4)10)

Power Down Exit

L

H

X

1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

2) “X” means H or L (but a defined logic level).

3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS and CKE at the rising edge of the clock.

5) Bank addresses BA[2:0] determine which bank is to be operated upon. For (E)MRS BA[2:0] selects an (Extended) Mode Register.

6) All banks must be in a precharged idle state, CKE must be high at least for t_XPand all read/write bursts must be finished before the

(Extended) Mode Register set Command is issued.

7)

V_REFmust be maintained during Self Refresh operation.

8) Self Refresh Exit is asynchronous.

9) Burst reads or writes at BL = 4 cannot be terminated. See Chapter 3.5 for details.

10) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh

requirements.

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TABLE 13

Clock Enable (CKE) Truth Table for Synchronous Transitions

Current State¹⁾

CKE

Command

(N)²⁾³⁾RAS, CAS, WE,

CS

Action (N)²⁾

Note⁴⁾⁵⁾

Previous Cycle⁶⁾Current Cycle⁶⁾

(N-1)

(N)

7)8)11)

Power-Down

Self Refresh

L

H

L

H

L

H

L

X

Maintain Power-Down

Power-Down Exit

Maintain Self Refresh

Self Refresh Exit

Active Power-Down Entry

Precharge Power-Down

Entry

7)9)10)11)

8)11)12)

DESELECT or NOP

X

DESELECT or NOP

9)11)12)13)14)

7)9)10)11)15)

9)10)11)15)

Bank(s) Active

All Banks Idle

7)11)14)16)

17)

H

L

H

AUTOREFRESH

Refer to the Command Truth Table

Self Refresh Entry

Any State other than

listed above

1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).

3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. .

4) CKE must be maintained HIGH while the device is in OCD calibration mode.

5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh

requirements.

8) “X” means “don’t care (including floating around V_REF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in

Power Down if the ODT function is enabled (Bit A2 or A6 set to 1 in EMRS(1)).

9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

11) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 × t_CK+ t_IH.

12) V_REFmust be maintained during Self Refresh operation.

13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t_XSNRperiod. Read

commands may be issued only after t_XSRD(200 clocks) is satisfied.

14) Valid commands for Self Refresh Exit are NOP and DESELCT only.

15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or

Refresh operations are in progress.

16) Self Refresh mode can only be entered from the All Banks Idle state.

17) Must be a legal command as defined in the Command Truth Table.

TABLE 14

Data Mask (DM) Truth Table

Name (Function)

DM

DQs

Note

1)

Write Enable

Write Inhibit

L

H

Valid

X

1) Used to mask write data; provided coincident with the corresponding data.

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5

Electrical Characteristics

This chapter describes the Electrical Characteristics.

5.1

Absolute Maximum Ratings

Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 15 at any time.

TABLE 15

Absolute Maximum Ratings

Symbol

Parameter

Rating

Min.

Unit

Note

Max.

1)

V_DD

V_DDQ

V_DDL

V_IN, V_OUT

T_STG

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

–1.0

–0.5

–55

+2.3

+100

V

1)2)

1)

1)2)

°C

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REFmay be equal to or less than 300 mV.

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

TABLE 16

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Unit

Note

Min.

Max.

T_OPER

Operating Temperature

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

0

+95

°C

^1)2)3)4)5)Standard

2) The operating temperature range are the temperatures where all DRAM specification will be supported.

3) During operation, the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters.

4) Above 85 °C the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs.

5) When operating this product in the 85 °C to 95 °C T_CASEtemperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to 1. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%.

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5.2

DC Characteristics

Input and output capacitances are higher with dual-die components compared to standard single-die components, due to the

double loading of the input / output pins, except for CS[1:0], CKE[1:0 and ODT[1:0] and the additional package internal wiring.

TABLE 17

Recommended DC Operating Conditions (SSTL_18)

Symbol

Parameter

Rating

Min.

Unit

Note

Typ.

Max.

1)

V_DD

Supply Voltage

1.7

0.49 × V_DDQ

1.8

0.5 × V_DDQ

V_REF

1.9

0.51 × V_DDQ

V

1)

V_DDDL

V_DDQ

V_REF

V_TT

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1)

2)3)

4)

V

_REF– 0.04

V_REF+ 0.04

1)

V_DDQtracks with V_DD, V_DDDLtracks with V_DD. AC parameters are measured with V_DD, V_DDQand V_DDDLtied together.

2) The value of V_REFmay be selected by the user to provide optimum noise margin in the system. Typically the value of V_REFis expected to

be about 0.5 × V_DDQof the transmitting device and V_REFis expected to track variations in V_DDQ

3) Peak to peak ac noise on V_REFmay not exceed ± 2% V_REF(dc)

.

4)

V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to V_REF, and

must track variations in die dc level of V_REF

.

TABLE 18

ODT DC Electrical Characteristics

Parameter / Condition

Symbol Min. Nom. Max. Unit Note

1)

Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Rtt1(eff) 60

Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Rtt2(eff) 120

Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm

Deviation of V_Mwith respect to V_DDQ/ 2

75

150

50

90

180

60

Ω

%

1)

1)2)

3)

Rtt3(eff) 40

delta V_M–6.00

—

+6.00

1) Measurement Definition for Rtt(eff): Apply V_IH(ac)and V_IL(ac)to test pin separately, then measure current I(V_IHac) and I(V_ILac) respectively.

Rtt(eff) = (V_IH(ac)– V_IL(ac)) /(I(V_IHac) – I(V_ILac)).

2) Optional for DDR2-400, DDR2-533 and DDR2-667, mandatory for DDR2-800.

3) Measurement Definition for V_M: Turn ODT on and measure voltage (V_M) at test pin (midpoint) with no load: delta V_M= ((2 x V_M/ V_DDQ) –

1) x 100%

TABLE 19

Input and Output Leakage Currents

Symbol

Parameter / Condition

Min.

Max.

Unit

Note

1)

I_IL

I_OL

Input Leakage Current; any input 0 V < VIN < V_DD

Output Leakage Current; 0 V < VOUT < V_DDQ

–2

–5

+2

+5

µA

2)

1) All other pins not under test = 0 V

2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off

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5.3

DC & AC Characteristics

DDR2 SDRAM pin timing are specified for either single ended

or differential mode depending on the setting of the EMRS(1)

“Enable DQS” mode bit; timing advantages of differential

mode are realized in system design. The method by which the

DDR2 SDRAM pin timing are measured is mode dependent.

In single ended mode, timing relationships are measured

In differential mode, these timing relationships are measured

relative to the crosspoint of DQS and its complement, DQS.

This distinction in timing methods is verified by design and

characterization but not subject to production test. In single

ended mode, the DQS (and RDQS) signals are internally

disabled and don’t care.

relative to the rising or falling edges of DQS crossing at V_REF

.

TABLE 20

DC & AC Logic Input Levels

Symbol

Parameter

DDR2-667, DDR2-800

Min. Max.

_REF+ 0.125

–0.3

_REF+ 0.200

DDR2-533

Units

Min.

Max.

V_IH(dc)

V_IL(dc)

V_IH(ac)

V_IL(ac)

DC input logic HIGH

DC input LOW

AC input logic HIGH

AC input LOW

V

—

_DDQ+ 0.3

_REF– 0.125

V

_REF+ 0.125

V

_DDQ+ 0.3

_REF– 0.125

V

–0.3

V

_REF+ 0.250

—

V_REF– 0.200

—

V_REF- 0.250

TABLE 21

Single-ended AC Input Test Conditions

Symbol

Condition

Value

Unit

Notes

1)

V_REF

V_SWING.MAX

SLEW

Input reference voltage

Input signal maximum peak to peak swing

Input signal minimum Slew Rate

0.5 x V_DDQ

1.0

V

V / ns

1)

2)3)

1) Input waveform timing is referenced to the input signal crossing through the V_REFlevel applied to the device under test.

2) The input signal minimum Slew Rate is to be maintained over the range from V_IH(ac).MINto V_REFfor rising edges and the range from V_REF

to V_IL(ac).MAXfor falling edges as shown in Figure 3

3) AC timings are referenced with input waveforms switching from V_IL(ac)to V_IH(ac)on the positive transitions and V_IH(ac)to V_IL(ac)on the negative

transitions.

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

FIGURE 3

Single-ended AC Input Test Conditions Diagram

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TABLE 22

Differential DC and AC Input and Output Logic Levels

Symbol

Parameter

DC input signal voltage

DC differential input voltage

AC differential input voltage

AC differential cross point input voltage

Min.

Max.

Unit

Notes

1)

2)

3)

4)

5)

V_IN(dc)

V_ID(dc)

V_ID(ac)

V_IX(ac)

V_OX(ac)

–0.3

0.25

0.5

V

_DDQ+ 0.3

_DDQ+ 0.6

—

V

0.5 × V_DDQ– 0.175

0.5 × V_DDQ+ 0.175

0.5 × V_DDQ+ 0.125

AC differential cross point output voltage 0.5 × V_DDQ– 0.125

1)

2)

3)

V

_IN(dc)specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.

_ID(dc)specifies the input differential voltage V_TR– V_CPrequired for switching. The minimum value is equal to V_IH(dc)– V_IL(dc)

.

_ID(ac)specifies the input differential voltage V_TR– V_CPrequired for switching. The minimum value is equal to V_IH(ac)– V_IL(ac)

.

4) The value of V_IX(ac)is expected to equal 0.5 × V_DDQof the transmitting device and V_IX(ac)is expected to track variations in V_DDQ. V_IX(ac)

indicates the voltage at which differential input signals must cross.

5) The value of V_OX(ac)is expected to equal 0.5 × V_DDQof the transmitting device and V_OX(ac)is expected to track variations in V_DDQ. V_OX(ac)

indicates the voltage at which differential input signals must cross.

FIGURE 4

Differential DC and AC Input and Output Logic Levels Diagram

9

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5.4

Output Buffer Characteristics

This chapter describes the Output Buffer Characteristics.

TABLE 23

SSTL_18 Output DC Current Drive

Symbol

Parameter

SSTL_18

Unit

Notes

1)2)

I_OH

I_OL

Output Minimum Source DC Current

Output Minimum Sink DC Current

–13.4

13.4

mA

2)3)

1)

V_DDQ= 1.7 V; V_OUT= 1.42 V. (V_OUT–V_DDQ) / I_OHmust be less than 21 Ω for values of V_OUTbetween V_DDQand V_DDQ– 280 mV.

2) The values of I_OH(dc)and I_OL(dc)are based on the conditions given in ¹⁾and ³⁾. They are used to test drive current capability to ensure V_IH.MIN

plus a noise margin and V_IL.MAXminus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by

shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.

.

3)

V_DDQ= 1.7 V; V_OUT= 280 mV. V_OUT/ I_OLmust be less than 21 Ohm for values of V_OUTbetween 0 V and 280 mV.

TABLE 24

SSTL_18 Output AC Test Conditions

Symbol

Parameter

SSTL_18

Unit

Note

1)

V_OH

V_OL

V_OTR

Minimum Required Output Pull-up

Maximum Required Output Pull-down

Output Timing Measurement Reference Level

V_TT+ 0.603

V_TT– 0.603

0.5 × V_DDQ

V

1)

1) SSTL_18 test load for V_OHand V_OLis different from the referenced load . The SSTL_18 test load has a 20 Ohm series resistor additionally

to the 25 Ohm termination resistor into V_TT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25

Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum

requirement of 603 mV swing relative to V_TT, at the ouput device (13.4 mA × 45 Ohm = 603 mV).

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TABLE 25

OCD Default Characteristics

Symbol Description

Min.

Nominal

Max.

Unit

Notes

1)2)

—

Output Impedance

Ω

1)2)3)

4)

—

S_OUT

Pull-up / Pull down mismatch

Output Impedance step size for OCD calibration

Output Slew Rate

0

1.5

—

4

1.5

5.0

Ω

1)5)6)7)

V / ns

1)

V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

2) Impedance measurement condition for output source dc current: V_DDQ= 1.7 V, V_OUT= 1420 mV; (V_OUT–V_DDQ) / I_OHmust be less than 23.4

ohms for values of V_OUTbetween V_DDQand V_DDQ– 280 mV. Impedance measurement condition for output sink dc current: V_DDQ= 1.7 V;

V

_OUT= –280 mV; V_OUT/ I_OLmust be less than 23.4 Ohms for values of V_OUTbetween 0 V and 280 mV.

3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.

4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the

DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal

conditions.

5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.

This is verified by design and characterization but not subject to production test.

6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in t_DQSQand t_QHS

specification.

7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.

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5.5

Input / Output Capacitance

This chapter contains the Input / Output Capacitance.

TABLE 26

Input / Output Capacitance

Symbol

Parameter

DDR2-800

Min.

DDR2-667

Min.

DDR2-533

Unit

Max.

Min.

Max.

CCK

CDCK

CI1

Input capacitance, CK and CK

Input capacitance delta, CK and CK

Input capacitance

CS[1:0], CKE[1:0],ODT[1:0]

3.5

—

1.75

7.5

0.375

3.5

—

1.75

7.5

0.375

3.5

—

1.75

7.5

0.375

3.75

pF

CDI1

CI2

Input capacitance delta

—

0.5

—

0.5

—

0.5

pF

CS[1:0], CKE[1:0],ODT[1:0]

Input capacitance

RAS, CAS, WE, A[14:0], BA[2:0]

Input capacitance delta

RAS, CAS, WE, A[14:0], BA[2:0]

Input/output capacitance,

DQ, DM, DQS, DQS

Input/output capacitance delta,

DQ, DM, DQS, DQS

3.25

—

7.5

3.25

—

7.5

3.25

—

7.5

CDI2

CIO

0.5

5.5

—

10.5

0.75

5.5

—

10.5

0.75

5.5

—

10.5

0.75

CDIO

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

5.6

Overshoot and Undershoot Specification

This chapter contains Overshoot and Undershoot Specification.

TABLE 27

AC Overshoot / Undershoot Specification for Address and Control Pins

Parameter

DDR2-533

DDR2-667

DDR2-800

Unit

Maximum peak amplitude allowed for

overshoot area

0.9

V

Maximum peak amplitude allowed for

undershoot area

0.9

V

Maximum overshoot area above V_DD

Maximum undershoot area below V_SS

1.00

0.8

0.66

V-ns

FIGURE 5

AC Overshoot / Undershoot Diagram for Address and Control Pins

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 28

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins

Parameter

DDR2-533

DDR2-667

DDR2-800

Unit

Maximum peak amplitude allowed for overshoot 0.9

area

0.9

V

Maximum peak amplitude allowed for

undershoot area

0.9

V

Maximum overshoot area above V_DDQ

Maximum undershoot area below V_SSQ

0.28

0.23

V-ns

FIGURE 6

AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

6

Currents Measurement Conditions

This chapter describes the Current Measurement, Specifications and Conditions.

TABLE 29

I_DDMeasurement Conditions

Parameter

Symbol Note

1)2)3)4)5)6)

Operating Current - One bank Active - Precharge

I_DD0

t

_CK= t_CK(IDD), t_RC= t_RC(IDD), t_RAS= t_RAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.

Address and control inputs are switching; Databus inputs are switching.

1)2)3)4)5)6)

Operating Current - One bank Active - Read - Precharge

I_DD1

I

_OUT= 0 mA, BL = 4, t_CK= t_CK(IDD), t_RC= t_RC(IDD), t_RAS= t_RAS.MIN(IDD), t_RCD= t_RCD(IDD), AL = 0, CL = CL(IDD);

CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching;

Databus inputs are switching.

1)2)3)4)5)6)

Precharge Power-Down Current

I_DD2P

All banks idle; CKE is LOW; t_CK= t_CK(IDD);Other control and address inputs are stable; Data bus inputs

are floating_.

Precharge Standby Current

I_DD2N

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK(IDD); Other control and address inputs are switching,

Data bus inputs are switching_.

Precharge Quiet Standby Current

I_DD2Q

I_DD3P(0)

I_DD3P(1)

I_DD3N

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK(IDD); Other control and address inputs are stable,

Data bus inputs are floating.

Active Power-Down Current

All banks open; t_CK= t_CK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs

are floating. MRS A12 bit is set to 0 (Fast Power-down Exit).

Active Power-Down Current

All banks open; t_CK= t_CK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs

are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);

Active Standby Current

All banks open; t_CK= t_CK(IDD); t_RAS= t_RAS.MAX(IDD), t_RP= t_RP(IDD); CKE is HIGH, CS is HIGH between valid

commands. Address inputs are switching; Data Bus inputs are switching;

Operating Current

I_DD4R

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_(IDD); t_CK= t_CK(IDD); t_RAS

=

t

_{RAS.MAX.(IDD)}, t_RP= t_RP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are

switching; Data Bus inputs are switching; I_OUT= 0 mA.

1)2)3)4)5)6)

Operating Current

I_DD4W

Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_(IDD); t_CK= t_CK(IDD); t_RAS

t

_RAS.MAX(IDD), t_RP= t_RP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are

switching; Data Bus inputs are switching;

1)2)3)4)5)6)

Burst Refresh Current

I_DD5B

t

_CK= t_CK(IDD), Refresh command every t_RFC= t_RFC(IDD)interval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are switching, Data bus inputs are switching.

Distributed Refresh Current

I_DD5D

t

_CK= t_CK(IDD), Refresh command every t_REFI= 7.8 µs interval, CKE is LOW and CS is HIGH between

valid commands, Other control and address inputs are switching, Data bus inputs are switching.

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Parameter

Symbol Note

1)2)3)4)5)6)

Self-Refresh Current

I_DD6

CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data

bus inputs are floating.

1)2)3)4)5)6)

Operating Bank Interleave Read Current

I_DD7

1. All banks interleaving reads, I_OUT= 0 mA; BL = 4, CL = CL_(IDD), AL = t_RCD(IDD)-1 × t_CK(IDD); t_CK

=

t

_CK(IDD), t_RC= t_RC(IDD), t_RRD= t_RRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid

commands. Address bus inputs are stable during deselects; Data bus is switching.

2. Timing pattern: see Detailed I_DD7timings shown below.

1)

2)

3)

V

_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V.

I

_DDspecifications are tested after the device is properly initialized.

_DDparameter are specified with ODT disabled.

I

4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.

5) Definitions for I_DD, see Table 30.

6) Timing parameter minimum and maximum values for I_DDcurrent measurements are defined in Chapter 7.

Detailed I_DD7

The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the

specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect.

I

_DD7: Operating Current: All Bank Interleave Read operation

All banks are being interleaved at minimum t_RC.IDDwithout violating t_RRD.IDDand t_FAW.IDDusing a burst length of 4. Control and

address bus inputs are STABLE during DESELECTs. IOUT = 0 mA.

Timing Patterns for devices with 1KB page size

DDR2-533: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D

DDR2-667: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D

DDR2-800: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D

TABLE 30

Definition for I_DD

Parameter

Description

LOW

Defined as V_IN≤ V_IL.AC.MAX

HIGH

Defined as V_IN≥ V_IH.AC.MIN

STABLE

FLOATING

SWITCHING

Defined as inputs are stable at a HIGH or LOW level

Defined as inputs are V_REF= V_DDQ/ 2

Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address

and control signals, and inputs changing between high and low every other clock (once per clock) for DQ

signals not including mask or strobes

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 31

I

_DDSpecification

Symbol

–25F

–2.5

–3S

–3.7

Unit

Note

DDR2-800D

Max.

DDR2-800E

Max.

DDR2-667D

Max.

DDR2-533C

Max.

1)

I_DD0

I_DD1

I_DD2N

I_DD2P

I_DD2Q

I_DD3N

150

154

126

32

122

138

70

150

154

126

32

122

138

70

139

144

116

32

110

126

66

125

130

100

32

98

114

64

mA

1)

2)

2)3)

2)4)

1)

I

_{DD3P_0}(fast)

_{DD3P_1}(slow)

34

I_DD4R

I_DD4W

I_DD5B

I_DD5D

I_DD6

206

217

285

40

32

269

206

217

285

40

32

269

188

197

273

40

32

247

172

174

260

40

32

234

1)

2)5)

1)

I_DD7

1) One Die is in I_DDxstate, the other Die is in I_DD2Nstate

2) Both dies are in the same state

3) MRS(12)=0

4) MRS(12)=1

5) For I_DD5Dand I_DD60° ≤ T_CASE≤ 85 °C

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

7

Timing Characteristics

This chapter contains speed grade definition, AC timing parameter and ODT tables.

7.1

Speed Grade Definitions

TABLE 32

Speed Grade Definition

Speed Grade

DDR2–800D

–25F

DDR2–800E

–2.5

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

Parameter

5–5–5

Min.

6–6–6

t_CK

Symbol

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Period

@ CL = 3

t_CK

t_RAS

t_RC

t_RCD

t_RP

5

8

70k

—

5

3.75

3

2.5

45

60

15

8

70k

—

ns

@ CL = 4

@ CL = 5

@ CL = 6

3.75

2.5

45

57.5

12.5

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 33

Speed Grade Definition

Speed Grade

DDR2–667D

–3S

DDR2–533C

–3.7

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

Parameter

5–5–5

4–4–4

t_CK

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Period

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

t_RAS

t_RC

t_RCD

t_RP

5

3.75

3

45

60

15

8

70k

—

5

8

70k

—

ns

3.75

45

60

15

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

15

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode. CKDQS RDQS

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQ

4) The output timing reference voltage level is V_TT

.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

.

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

7.2

Component AC Timing Parameters

The AC timings parameters are guaranteed with CK/CK clock

differential slew rate of 2.0 V/ns. For data strobe signals

timings are guaranteed with a differential slew rate of 2.0 V/ns

in differential strobe mode and a slew rate of 1 V/ns in single

ended mode. If slew rates can’t be met, the basic values for

setup and hold times have to be derated. The component

data sheet provides derating tables for these parameters.

Timings are further guaranteed for normal OCD drive strength

(EMR1 A1 = 0). The CK / CK input reference level (for timing

referenced to CK / CK) is the point at which CK and CK cross.

The DQS/DQS, RDQS/RDQS reference level is the

crosspoint when in differential strobe mode. For single-ended

strobe mode see the respective section in the component

data sheet. Inputs are not recognized as valid until V_REF

stabilizes.

During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as LOW. The output timing reference voltage

level is V_TT.

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 34

DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667

Parameter

Symbol DDR2–800

DDR2–667

Unit

Note¹⁾²⁾³

)4)5)6)7)

Min.

Max.

Min.

Max.

8)36)

9)10)

11)

DQ output access time from CK / CK t_AC

–400

2

0.48

2500

3

+600

—

0.52

8000

—

–450

2

0.48

3000

3

+650

—

0.52

8000

—

ps

CAS to CAS command delay

Average clock high pulse width

Average clock period

t_CCD

t_CH.AVG

t_CK.AVG

nCK

t_CK.AVG

ps

CKE minimum pulse width ( high and t_CKE

nCK

low pulse width)

Average clock low pulse width

Auto-Precharge write recovery +

precharge time

9)10)

t_CL.AVG

t_DAL

0.48

WR + t_nRP

0.52

—

0.48

WR + t_nRP

0.52

—

t_CK.AVG

nCK

12)13)

Minimum time clocks remain ON after t_DELAY

t_IS+ t_{CK .AVG}––

+ t_IH

t_IS+

––

ns

CKE asynchronously drops LOW

t_{CK .AVG}+ t_IH

14)18)19)38)

8)37)

DQ and DM input hold time

t_DH.BASE

125

0.35

––

—

175

0.35

––

—

ps

t_CK.AVG

DQ and DM input pulse width for each t_DIPW

input

DQS output access time from CK / CK t_DQSCK

DQS input high pulse width

DQS input low pulse width

–350

0.35

—

+550

—

–400

0.35

—

+600

—

ps

t_DQSH

t_DQSL

t_CK.AVG

ps

15)

16)

DQS-DQ skew for DQS & associated t_DQSQ

200

240

DQ signals

DQS latching rising transition to

associated clock edges

DQ and DM input setup time

DQS falling edge hold time from CK t_DSH

DQS falling edge to CK setup time t_DSS

t_DQSS

– 0.25

+ 0.25

– 0.25

+ 0.25

t_CK.AVG

17)18)19)38)

t_DS.BASE

50

––

—

100

0.2

––

—

ps

16)

34)

0.2

35

t_CK.AVG

ns

Four Activate Window for 1KB page t_FAW

37.5

size products

34)

Four Activate Window for 2KB page t_FAW

45

—

50

—

ns

ps

size products

20)

CK half pulse width

t_HP

Min(t_CH.ABS

,

__

Min(t_CH.ABS

,

__

t_CL.ABS

)

t_CL.ABS)

8)21)

22)24)38)

Data-out high-impedance time from t_HZ

—

t_AC.MAX

—

t_AC.MAX

CK / CK

Address and control input hold time t_IH.BASE

250

0.6

—

275

0.6

—

ps

t_CK.AVG

Control & address input pulse width t_IPW

for each input

23)24)38)

8)21)

Address and control input setup time t_IS.BASE

DQ low impedance time from CK/CK t_LZ.DQ

175

2 × t_AC.MIN

t_AC.MIN

—

t_AC.MAX

200

2 × t_AC.MIN

t_AC.MIN

—

t_AC.MAX

ps

8)21)

DQS/DQS low-impedance time from t_LZ.DQS

CK / CK

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Parameter

Symbol DDR2–800

Min.

DDR2–667

Min.

Unit

Note¹⁾²⁾³

)4)5)6)7)

Max.

34)

MRS command to ODT update delay t_MOD

0

2

12

—

0

2

12

—

ns

nCK

Mode register set command cycle

time

t_MRD

34)

OCD drive mode output delay

t_OIT

0

12

—

300

7.8

3.9

—

0

12

—

340

7.8

3.9

—

ns

ps

µs

ns

25)

DQ/DQS output hold time from DQS t_QH

t

_HP– t_QHS

t

_HP– t_QHS

26)

DQ hold skew factor

Average periodic refresh Interval

t_QHS

t_REFI

—

195

—

195

27)28)

27)29)

30)

Auto-Refresh to Active/Auto-Refresh t_RFC

command period

31)32)

31)33)

34)

Read preamble

Read postamble

t_RPRE

t_RPST

0.9

0.4

7.5

1.1

0.6

—

0.9

0.4

7.5

1.1

0.6

—

t_CK.AVG

ns

Active to active command period for t_RRD

1KB page size products

34)

Internal Read to Precharge command t_RTP

7.5

—

7.5

—

ns

delay

Write preamble

Write postamble

Write recovery time

Internal write to read command delay t_WTR

Exit active power down to read

command

Exit active power down to read

command (slow exit, lower power)

Exit precharge power-down to any

command

Exit self-refresh to a non-read

command

Exit self-refresh to read command

Write command to DQS associated

clock edges

t_WPRE

t_WPST

t_WR

0.35

0.4

15

7.5

2

—

0.6

—

0.35

0.4

15

7.5

2

—

0.6

—

t_CK.AVG

ns

nCK

34)

34)35)

t_XARD

t_XARDS

t_XP

8 – AL

2

—

7 – AL

2

—

nCK

ns

34)

t_XSNR

t

_RFC+10

t_RFC+10

t_XSRD

WL

200

RL – 1

200

RL–1

nCK

1) V_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V.

2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode. DQS RDQS

5) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

6) The output timing reference voltage level is V_TT

.

7) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVGof the input clock

under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and

DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

.

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per)of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272

ps and t_{ERR(6- 10PER).MAX}= + 293 ps, then t_{DQSCK.MIN(DERATED)}= t_DQSCK.MIN– t_{ERR(6-10PER).MAX}= – 400 ps – 293 ps = – 693 ps and

t

_{DQSCK.MAX(DERATED)}= t_DQSCK.MAX– t_{ERR(6-10PER).MIN}= 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQfor DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}

= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)}= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and

these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.

10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between

the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations

of Chapter 7.3).

11) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 x t_CK+ t_IH.

12) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result

of the division is not already an integer, round up to the next highest integer. t_CKrefers to the application clock period. Example: For

DDR2–533 at t_CK= 3.75 ns with t_WRprogrammed to 4 clocks. t_DAL= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

13) t_DAL.nCK= WR [nCK] + t_nRP.nCK= WR + RU{t_RP[ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.

14) Input waveform timing t_DHwith differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the V_IH.DClevel for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the V_IL.DClevel for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAXand

V_IH.DC.MIN. See Figure 8.

15) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

17) Input waveform timing t_DSwith differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AClevel

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AClevel to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAXand V_ih(DC)MIN. See

Figure 8.

18) If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

20) t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not an input specification parameter.

It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The value to be used for t_QHcalculation is determined by the

following equation; t_HP= MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABSis the minimum of the actual instantaneous clock high time; t_CL.ABSis the

minimum of the actual instantaneous clock low time.

21) t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .

22) input waveform timing is referenced from the input signal crossing at the V_IL.DClevel for a rising signal and V_IH.DCfor a falling signal applied

to the device under test. See Figure 9.

23) Input waveform timing is referenced from the input signal crossing at the V_IH.AClevel for a rising signal and V_IL.ACfor a falling signal applied

to the device under test. See Figure 9.

24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC

,

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should

be met whether clock jitter is present or not.

25) t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis the specification value under

the max column. {The less half-pulse width distortion present, the larger the t_QHvalue is; and the larger the valid data eye will be.}

Examples: 1) If the system provides t_HPof 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 975 ps minimum. 2) If the system

provides t_HPof 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 1080 ps minimum.

26) t_QHSaccounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation

of the output drivers.

27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C

and 95 °C.

28) 0 °C≤ T_CASE≤ 85 °C.

29) 85 °C < T_CASE≤ 95 °C.

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between

any Refresh command and the next Refresh command is 9 x t_REFI

.

31) t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the device output is no longer driving

(t_RPST), or begins driving (t_RPRE). Figure 7 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins

driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the

calculation is consistent.

32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PERof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN= – 72 ps

and t_JIT.PER.MAX= + 93 ps, then t_{RPRE.MIN(DERATED)}= t_RPRE.MIN+ t_JIT.PER.MIN= 0.9 x t_CK.AVG– 72 ps = + 2178 ps and t_{RPRE.MAX(DERATED)}= t_RPRE.MAX

+ t_JIT.PER.MAX= 1.1 x t_CK.AVG+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTYof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN= – 72 ps

and t_JIT.DUTY.MAX= + 93 ps, then t_{RPST.MIN(DERATED)}= t_RPST.MIN+ t_JIT.DUTY.MIN= 0.4 x t_CK.AVG– 72 ps = + 928 ps and t_{RPST.MAX(DERATED)}= t_RPST.MAX

+ t_JIT.DUTY.MAX= 0.6 x t_CK.AVG+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

34) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM= RU{t_PARAM/ t_CK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP= RU{t_RP/ t_CK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP= 15 ns, the device will support

t

_nRP= RU{t_RP/ t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

35) t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

36) Dual-die component has extra capacitance on both data and clock path therefore clock to data out time minimum and maximum values

are shifted.

37) Dual-die component has extra capacitance on both DQS and clock path therefore clock to data out time minimum and maximum values

are shifted.

38) These numbers are based on the single die component with the slew rates which are mentioned in the single die component data sheet.

As a dual die component has higher capacitance compared to single die component, all the input signal drivers should be strong enough

to achieve the same slew rate and input levels as for a single die. Otherwise, it is necessary to change the setup and hold timings.

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 35

DRAM Component Timing Parameter by Speed Grade - DDR2–533

Parameter

Symbol

DDR2–533

Unit

Notes^1)2)3)4)5)

6)

Min.

Max.

22)

DQ output access time from CK / CK

CAS to CAS command delay

CK high pulse width

t_AC

t_CCD

t_CH

–500

2

0.45

3

0.45

WR + t_RP

+700

—

0.55

—

0.55

—

ps

t_CK

CKE minimum high and low pulse width t_CKE

CK low pulse width

t_CL

7)

Auto-Precharge write recovery +

precharge time

Minimum time clocks remain ON after

CKE asynchronously drops LOW

t_DAL

8)

t_DELAY

t_IS+ t_CK+ t_IH

225

––

—

ns

ps

t_CK

9)24)

10)24)

DQ and DM input hold time (differential t_DH.BASE

data strobe)

DQ and DM input hold time (single ended t_DH1.BASE

–25

data strobe)

DQ and DM input pulse width for each

input

t_DIPW

0.35

23)

10)

DQS output access time from CK / CK

DQS input HIGH pulse width

DQS input LOW pulse width

DQS-DQ skew (for DQS & associated

DQ signals)

t_DQSCK

t_DQSH

t_DQSL

t_DQSQ

–450

0.35

—

+650

—

ps

t_CK

ps

300

DQS latching rising transition to

associated clock edges

t_DQSS

– 0.25

100

+ 0.25

—

t_CK

ps

10)24)

DQ and DM input setup time (differential t_DS.BASE

strobe)

DQ and DM input setup time (single

ended strobe)

t_DS1.BASE

–25

—

DQS falling edge hold time from CK

DQS falling edge to CK setup time

t_DSH

t_DSS

0.2

37.5

—

t_CK

ns

Four Activate Window for 1KB page size t_FAW

products

12)

Four Activate Window for 2KB page size t_FAW

50

—

ns

ps

products

11)

CK half pulse width

t_HP

Min(t_CH.ABS

,

__

t_CL.ABS

)

12)

Data-out high-impedance time from CK / t_HZ

—

t_AC.MAX

CK

10)24)

Address and control input hold time

t_IH.BASE

375

0.6

—

ps

t_CK

Address and control input pulse width for t_IPW

each input

10)24)

Address and control input setup time

t_IS.BASE

250

40

—

ps

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Parameter

Symbol

DDR2–533

Min.

Unit

Notes^1)2)3)4)5)

6)

Max.

13)

DQ low-impedance time from CK / CK

t_LZ.DQ

2 × t_AC.MIN

t_AC.MIN

t_AC.MAX

ps

DQS/DQS low-impedance time from CK / t_LZ.DQS

CK

MRS command to ODT update delay

Mode register set command cycle time

OCD drive mode output delay

Data output hold time from DQS

Data hold skew factor

Average periodic refresh Interval

Auto-Refresh to Active/Auto-Refresh

command period

t_MOD

t_MRD

t_OIT

0

2

0

12

—

12

—

400

7.8

3.9

—

ns

t_CK

ns

ps

µs

ns

t_QH

t_HP–t_QHS

—

t_QHS

t_REFI

t_RFC

13)14)

15)17)

16)

195

13)

Read preamble

Read postamble

t_RPRE

t_RPST

0.9

0.40

7.5

1.1

0.60

—

t_CK

ns

13)

13)17)

Active bank A to Active bank B command t_RRD

period for 1 KB page size

Internal Read to Precharge command

delay

t_RTP

7.5

—

ns

Write preamble

Write postamble

Write recovery time

Internal Write to Read command delay

t_WPRE

t_WPST

t_WR

0.35

0.40

15

7.5

2

—

0.60

—

t_CK

ns

t_CK

18)

19)

20)

t_WTR

Exit active power down to read command t_XARD

Exit active power down to read command t_XARDS

6 – AL

—

(slow exit, lower power)

Exit precharge power down to any non- t_XP

2

—

t_CK

read command

Exit Self-Refresh to non-read command t_XSNR

t

_RFC+10

200

_WR/t_CK

—

ns

t_CK

Exit Self-Refresh to Read command

t_XSRD

21)

Write recovery time for write with Auto-

Precharge

WR

t

1) V_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V.

2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode. DQS RDQS

5) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

6) The output timing reference voltage level is V_TT

.

7) For each of the terms, if not already an integer, round to the next highest integer. t_CKrefers to the application clock period. WR refers to

the WR parameter stored in the MR.

8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.

9) For timing definition, refer to the Component data sheet.

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4-Gbit Dual Die Double-Data-Rate-Two SDRAM

10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate

mis-match between DQS / DQS and associated DQ in any given cycle.

11) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can

be greater than the minimum specification limits for t_CLand t_CH).

12) The t_HZ, t_RPSTand t_LZ, t_RPREparameters are referenced to a specific voltage level, which specify when the device output is no longer driving

(t_HZ,t_RPST), or begins driving (t_LZ,t_RPRE). t_HZand t_LZtransitions occur in the same access time windows as valid data transitions.These

parameters are verified by design and characterization, but not subject to production test.

13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C

and 95 °C.

14) 0 °C≤ T_CASE≤ 85 °C.

15) 85 °C < T_CASE≤ 95 °C.

16) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between

any Refresh command and the next Refresh command is 9 x t_REFI

.

17) The t_RRDtiming parameter depends on the page size of the DRAM organization.

18) The maximum limit for the t_WPSTparameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) degrades accordingly.

19) Minimum t_WTRis two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.

20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-

down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARDcan be used. In “low active power-down mode” (MR, A12 =”1”) a slow

power-down exit timing t_XARDShas to be satisfied.

21) WR must be programmed to fulfill the minimum requirement for the t_WRtiming parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded

up to the next integer value. t_DAL= WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK

refers to the application clock period. WR refers to the WR parameter stored in the MRS.

22) Dual-die component has extra capacitance on both data and clock path therefore clock to data out time minimum and maximum values

are shifted.

23) Dual-die component has extra capacitance on both DQS and clock path therefore clock to data out time minimum and maximum values

are shifted.

24) These numbers are based on the single die component with the slew rates which are mentioned in the single die component data sheet.

As a dual die component has higher capacitance compared to single die component, all the input signal drivers should be strong enough

to achieve the same slew rate and input levels as for a single die. Otherwise, it is necessary to change the setup and hold timings.

FIGURE 7

Method for Calculating Transitions and Endpoint

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Rev. 1.00, 2008-04

07192007-CK80-SF4Y

42

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

FIGURE 8

Differential Input Waveform Timing - t_DSand t_DH

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Rev. 1.00, 2008-04

43

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

FIGURE 9

Differential Input Waveform Timing - t_lSand t_lH

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Rev. 1.00, 2008-04

44

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

7.3

Jitter Definition and Clock Jitter Specification

Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table

provides an overview of the terminology.

TABLE 36

Average Clock and Jitter Symbols and Definition

Symbol

Parameter

Description

Units

t_CK.AVG

Average clock period t_CK.AVGis calculated as the average clock period within any consecutive ps

200-cycle window:

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ꢀ

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N = 200

t_JIT.PER

Clock-period jitter

t

_JIT.PERis defined as the largest deviation of any single t_CKfrom t_CK.AVG

:

ps

t

_JIT.PER= Min/Max of {t_CKi– t_CK.AVG} where i = 1 to 200

t

_JIT.PERdefines the single-period jitter when the DLL is already locked.

_JIT.PERis not guaranteed through final production testing.

t

_JIT(PER, LCK)

Clock-period jitter

during DLL-locking

period

Cycle-to-cycle clock

period jitter

t

_JIT(PER,LCK) uses the same definition as t_JIT.PER, during the DLL-locking ps

period only.

t

_JIT(PER,LCK) is not guaranteed through final production testing.

_JIT.CCis defined as the absolute difference in clock period between two ps

t_JIT.CC

consecutive clock cycles:

t

_JIT.CC= Max of ABS{t_CKi+1– t_CKi}

t

_JIT.CCdefines the cycle - to - cycle jitter when the DLL is already locked.

_JIT.CCis not guaranteed through final production testing.

t

_JIT(CC, LCK)

Cycle-to-cycle clock

period jitter during

DLL-locking period

Cumulative error

across 2 cycles

t

_JIT(CC,LCK) uses the same definition as t_JIT.CCduring the DLL-locking

ps

period only.

t

_JIT(CC,LCK) is not guaranteed through final production testing.

_ERR.2PERis defined as the cumulative error across 2 consecutive cycles ps

t_ERR.2PER

from t_CK.AVG

:

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ꢋ

ꢁ

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ꢉ

ꢀ

ꢊ

n = 2 for t_ERR(2per)

where i = 1 to 200

Rev. 1.00, 2008-04

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HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Symbol

Parameter

Description

Units

t_ERR.nPER

Cumulative error

across n cycles

t

_ERR.2PERis defined as the cumulative error across n consecutive cycles ps

from t_CK.AVG

:

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where, i = 1 to 200 and

n = 3 for t_ERR.3PER

n = 4 for t_ERR.4PER

n = 5 for t_ERR.5PER

6 ≤ n ≤ 10 for t_ERR.6-10PER

11 ≤ n ≤ 50 for t_ERR.11-50PER

t_CH.AVG

Average high-pulse

width

t

_CH.AVGis defined as the average high-pulse width, as calculated across t_CK.AVG

any consecutive 200 high pulses:

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N = 200

t_CL.AVG

Average low-pulse

width

t

_CL.AVGis defined as the average low-pulse width, as calculated across any t_CK.AVG

consecutive 200 low pulses:

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N = 200

t_JIT.DUTY

Duty-cycle jitter

t

_JIT.DUTY= Min/Max of {t_JIT.CH, t_JIT.CL}, where:

ps

_JIT.CHis the largest deviation of any single t_CHfrom t_CH.AVG

_JIT.CLis the largest deviation of any single t_CLfrom t_CL.AVG

_JIT.CH= {t_CHi- t_CH.AVG× t_CK.AVG} where i=1 to 200

_JIT.CL= {t_CLi- t_CL.AVG× t_CK.AVG} where i=1 to 200

The following parameters are specified per their average values however, it is understood that the following relationship

between the average timing and the absolute instantaneous timing holds all the time.

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 37

Absolute Jitter Value Definitions

Symbol Parameter

Min.

Max.

Unit

t_CK.ABS

t_CH.ABS

Clock period

Clock high-pulse width

t

_CK.AVG(Min)+ t_JIT.PER(Min)

t

_CK.AVG(Max)+ t_JIT.PER(Max)

_CH.AVG(Max)x t_CK.AVG(Max)+

ps

t_CH.AVG(Min)x t_CK.AVG(Min)+ t_{JIT.DUTY(Min)}

t_{JIT.DUTY(Max)}

t_CL.ABS

Clock low-pulse width

t_CL.AVG(Min)x t_CK.AVG(Min)+ t_{JIT.DUTY(Min)}t_CL.AVG(Max)x t_CK.AVG(Max)

+

ps

t_{JIT.DUTY(Max)}

Example: for DDR2-667, t_CH.ABS.MIN= (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps.

Table 38 shows clock-jitter specifications.

TABLE 38

Clock-Jitter Specifications for –667, –800

Symbol

Parameter

DDR2 -667

DDR2 -800

Unit

Min.

Max.

Min.

Max.

t_CK.AVG

t_JIT.PER

t_JIT(PER,LCK)

t_JIT.CC

t_JIT(CC,LCK)

t_ERR.2PER

t_ERR.3PER

t_ERR.4PER

t_ERR.5PER

t_ERR(6-10PER)

Average clock period nominal w/o jitter

Clock-period jitter

Clock-period jitter during DLL locking period

Cycle-to-cycle clock-period jitter

Cycle-to-cycle clock-period jitter during DLL-locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across n cycles with n = 6 .. 10, inclusive

3000

–125

–100

–250

–200

–175

–225

–250

–350

–450

0.48

8000

125

100

250

200

175

225

250

350

450

0.52

125

2500

–100

–80

8000

100

80

ps

t_CK.AVG

ps

–200

–160

–150

–175

–200

–300

–450

0.48

200

160

150

175

200

300

450

0.52

100

t_{ERR(11-50PER)}Cumulative error across n cycles with n = 11 .. 50, inclusive

t_CH.AVG

t_CL.AVG

t_JIT.DUTY

Average high-pulse width

Average low-pulse width

Duty-cycle jitter

0.48

–125

0.48

–100

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

7.4

ODT AC Electrical Characteristics

This chapter describes the ODT AC electrical characteristics.

TABLE 39

ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800

Symbol

Parameter / Condition

Values

Unit

Note

Min.

Max.

1)

t_AOND

t_AON

ODT turn-on delay

ODT turn-on

2

n_CK

ns

n_CK

ns

1)2)

1)

t_AC.MIN

t_AC.MAX+ 0.7 ns

2 t_CK+ t_AC.MAX+ 1 ns

2.5

t_AC.MAX+ 0.6 ns

2.5 t_CK+ t_AC.MAX+ 1 ns ns

—

t_AONPD

t_AOFD

t_AOF

ODT turn-on (Power-Down Modes)

ODT turn-off delay

ODT turn-off

t_AC.MIN+ 2 ns

1)

2.5

t_AC.MIN

1)3)

1)

t_AOFPD

t_ANPD

t_AXPD

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency

ODT Power Down Exit Latency

t_AC.MIN+ 2 ns

1)

3

8

n_CK

1)

1) New units, “t_CK.AVG” and “n_CK”, are introduced in DDR2-667 and DDR2-800 Unit “t_CK.AVG” represents the actual t_CK.AVGof the input clock

under operation. Unit “n_CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and

DDR2-533, “t_CK” is used for both concepts. Example: t_XP= 2 [n_CK] means; if Power Down exit is registered at T_m, an Active command may

be registered at T_m+ 2, even if (T_m+ 2 - T_m) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

.

2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-667/800 t_AONDis

2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.

3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if t_CK(avg)= 3 ns is assumed,

t

_AOFDis 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by

counting the actual input clock edges.

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 40

ODT AC Characteristics and Operating Conditions for DDR2-533

Symbol

Parameter / Condition

Values

Unit

Note

Min.

Max.

t_AOND

t_AON

t_AONPD

t_AOFD

t_AOF

t_AOFPD

t_ANPD

t_AXPD

ODT turn-on delay

ODT turn-on

ODT turn-on (Power-Down Modes)

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency

ODT Power Down Exit Latency

2

t_CK

ns

t_CK

ns

t_CK

1)

2)

t_AC.MIN

t_AC.MAX+ 1 ns

2 t_{CK +}t_AC.MAX+ 1 ns

2.5

t_AC.MAX+ 0.6 ns

2.5 t_{CK +}t_AC.MAX+ 1 ns

—

t_AC.MIN+ 2 ns

2.5

t_AC.MIN

t_AC.MIN+ 2 ns

3

8

1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-400/533, t_AONDis

10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if t_CK= 5 ns.

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

Both are measured from t_AOFD. Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-400/533, t_AOFDis

12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if t_CK= 5 ns.

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

8

Package Outline

This chapter contains the package dimension figures.

Notes

1. Drawing according to ISO 8015

2. Dimensions in mm

3. General tolerances +/- 0.15

FIGURE 10

Package Outline PG-TFBGA-71

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Rev. 1.00, 2008-04

50

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

9

Product Nomenclature

For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.

TABLE 41

Examples for Nomenclature Fields

Example for

Field Number

1

2

3

4

5

6

7

8

9

10

DDR2 DRAM

HYB

18

T

2G

16

0

A

F

–3.7

TABLE 42

DDR2 Memory Components

Field Description

Values

Coding

1

Qimonda Component Prefix

HYB

HYI

18

Memory components, standard temperature range (0°C – +95 °C)

Memory components, industrial temperature range (-40°C – +95 °C)

SSTL_18, + 1.8 V (± 0.1 V)

2

Interface Voltage [V]

15

SSTL_15, + 1.5 V (± 0.1 V)

3

4

DRAM Technology

Component Density [Mbit]

T

32

64

128

256

512

1G

2G

4G

40

DDR2

32 Mbit

64 Mbit

128 Mbit

256 Mbit

512 Mbit

1 Gbit

2 Gbit

4 Gbit

× 4

5

Number of I/Os

80

× 8

16

× 16

6

7

Product Variant

Die Revision

0 .. 9

–

A ( 0...9 ) First

B ( 0...9 ) Second

C ( 0...9 ) Third

8

9

Package,

C

F

–

FBGA, lead-containing

FBGA, lead-free

Standard power product

Low power product

Lead-Free Status

Power

L

Rev. 1.00, 2008-04

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07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Field Description

10 Speed Grade

Values

Coding

–19F

–1.9

–25F

–2.5

–3

–3S

–3.7

–5

DDR2–1066 6–6–6

DDR2–1066 7–7–7

DDR2–800 5–5–5

DDR2–800 6–6–6

DDR2–667 4–4–4

DDR2–667 5–5–5

DDR2–533 4–4–4

DDR2–400 3–3–3

Rev. 1.00, 2008-04

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

List of Illustrations

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Configuration for x 4 Component, TFBGA-71 (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Configuration for x 8 Component, TFBGA-71 (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 29

Method for Calculating Transitions and Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Differential Input Waveform Timing - t_DSand t_DH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Differential Input Waveform Timing - t_lSand t_lH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Package Outline PG-TFBGA-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

List of Tables

Table 1

Performance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Mode Register Definition, BA_2:0= 000_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Extended Mode Register Definition, BA_2:0= 001_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

EMR(2) Programming Extended Mode Register Definition, BA_2:0=010_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

EMR(3) Programming Extended Mode Register Definition, BA_2:0=011_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clock Enable (CKE) Truth Table for Synchronous Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 29

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

Table 28

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

Table 36

Table 37

Table 38

Table 39

Table 40

Table 41

Table 42

I

_DDMeasurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Definition for I_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

I_DDSpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667 . . . . . . . . . . . . . . . . . . 36

DRAM Component Timing Parameter by Speed Grade - DDR2–533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Average Clock and Jitter Symbols and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Absolute Jitter Value Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Clock-Jitter Specifications for –667, –800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . 48

ODT AC Characteristics and Operating Conditions for DDR2-533. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Examples for Nomenclature Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Rev. 1.00, 2008-04

54

07192007-CK80-SF4Y

Internet Data Sheet

HYB18T4G[40/80]2AF

4-Gbit Dual Die Double-Data-Rate-Two SDRAM

Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1

1.2

2

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Configuration for FBGA-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

2.2

3

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Extended Mode Register EMR(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Extended Mode Register EMR(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Extended Mode Register EMR(3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1

3.2

3.3

3.4

3.5

4

Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Input / Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Overshoot and Undershoot Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1

5.2

5.3

5.4

5.5

5.6

6

Currents Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7

Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Jitter Definition and Clock Jitter Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1

7.2

7.3

7.4

8

9

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Product Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Rev. 1.00, 2008-04

55

07192007-CK80-SF4Y

Internet Data Sheet

Edition 2008-04

Published by Qimonda AG

Gustav-Heinemann-Ring 212

D-81739 München, Germany

Legal Disclaimer

THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE

OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY

TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,

QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT

LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please

contact your nearest Qimonda Office.

Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a

failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human

body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

www.qimonda.com


型号：	HYB18T4G802AF-2.5
厂家：	QIMONDA AG
描述：	DDR DRAM, 512MX8, 0.6ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71 动态存储器双倍数据速率
文件：	总56页 (文件大小：2497K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HYB18T4G802AF-2.5 [QIMONDA]

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