HYB25D512400DE-6 [QIMONDA]
DDR DRAM, 128MX4, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66;
| 型号： | HYB25D512400DE-6 |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM, 128MX4, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66 动态存储器 双倍数据速率 光电二极管 |
| 文件： | 总40页 (文件大小：2421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2008
HYB25D512400D[E/F/T]
HY[B/I]25D512800D[C/E/F/T](L)
HY[B/I]25D512160D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
DDR SDRAM
Internet Data Sheet
Rev. 1.01
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Revision History: Rev. 1.01, 2008-07
All
Adapted internet edition
Page 29
Changed tCK.MAX at CL=3 for -5 speed
Previous Revision: Rev. 1.00, 2007-08
Page 33 Added new IDD values
Previous Revision: Rev. 0.5, 2007-08
All New data sheet
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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qag_techdoc_A4, 4.20, 2008-01-25
08102007-5IZ2-ENDV
2
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Programmable CAS latency: 2, 2.5, 3 and 4
Programmable burst lengths: 2, 4, or 8
Programmable drive strength: normal, weak
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 μs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
V
DD = 2.5 V ± 0.2 V
DDQ = 2.5 V ± 0.2 V
Packages: PG-TFBGA-60, P-TFBGA-60, PG-TSOPII-66, P-TSOPII-66
TABLE 1
Performance
Part Number Speed Code
–5
–6
Unit
Speed Grade
DDR400B
200
DDR333B
166
—
Max. Clock Frequency
@CL4
@CL3
@CL2.5
@CL2
fCK4
fCK3
fCK2.5
fCK2
MHz
MHz
MHz
MHz
200
166
166
166
133
133
Rev. 1.01, 2008-07
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08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
1.2
Description
The 512-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing 536,
870, 912 bits. It is internally configured as a quad-bank
DRAM.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The 512-Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512-Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access. As
with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge
and activation time.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the Industry
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
The 512-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
Rev. 1.01, 2008-07
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08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note5)
Standard Temperature Range (0 °C - 70 °C)
DDR400B( 3-3-3 )
HYB25D512800DF-5
HYB25D512160DF-5
HYB25D512400DE-5
HYB25D512160DE-5
HYB25D512400DF-5
HYB25D512800DE-5
DDR333B( 2.5-3-3 )
HYB25D512160DEL-6
HYB25D512160DF-6
HYB25D512400DE-6
HYB25D512800DEL-6
HYB25D512160DE-6
HYB25D512800DE-6
HYB25D512400DF-6
HYB25D512800DF-6
×8
×16 DDR400B
×4 DDR400B
×16 DDR400B
DDR400B
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
200
200
200
200
200
200
PG-TFBGA-60
PG-TFBGA-60
PG-TSOPII-66
PG-TSOPII-66
PG-TFBGA-60
PG-TSOPII-66
×4
×8
DDR400B
DDR400B
×16 DDR333B
×16 DDR333B
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
166
166
166
166
166
166
166
166
PG-TSOPII-66
PG-TFBGA-60
PG-TSOPII-66
PG-TSOPII-66
PG-TSOPII-66
PG-TSOPII-66
PG-TFBGA-60
PG-TFBGA-60
×4
×8
DDR333B
DDR333B
×16 DDR333B
×8
×4
×8
DDR333B
DDR333B
DDR333B
Industrial Temperature Range (-40 °C - 85 °C)
DDR400B( 3-3-3 )
HYI25D512800DE-5
HYI25D512160DE-5
HYI25D512800DF-5
HYI25D512160DF-5
DDR333B( 2.5-3-3 )
HYI25D512800DE-6
HYI25D512160DE-6
HYI25D512800DF-6
HYI25D512160DF-6
×8
×16 DDR400B
×8 DDR400B
×16 DDR400B
DDR400B
3-3-3
3-3-3
3-3-3
3-3-3
200
200
200
200
PG-TSOPII-66
PG-TSOPII-66
PG-TFBGA-60
PG-TFBGA-60
×8
×16 DDR333B
×8 DDR333B
×16 DDR333B
DDR333B
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
166
166
166
166
PG-TSOPII-66
PG-TSOPII-66
PG-TFBGA-60
PG-TFBGA-60
1) For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet.
2) CAS: Column Address Strobe
3) RCD: Row Column Delay
4) RP: Row Precharge
5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products.
Rev. 1.01, 2008-07
5
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 3
Ordering Information for Lead-Containing Products
Product Type1)
Org. Speed
CAS-RCD-RP
Latencies2)3)4)
Clock (MHz) Package
Note
Standard Temperature Range (0 °C - 70 °C)
DDR400B( 3-3-3 )
HYB25D512160DC-5
HYB25D512160DT-5
HYB25D512400DT-5
HYB25D512800DT-5
HYB25D512800DC-5
DDR333B( 2.5-3-3 )
HYB25D512160DC-6
HYB25D512160DT-6
HYB25D512400DT-6
HYB25D512800DC-6
HYB25D512800DT-6
×16 DDR400B
×16 DDR400B
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
200
200
200
200
200
P-TFBGA-60
P-TSOPII-66
P-TSOPII-66
P-TSOPII-66
P-TFBGA-60
×4
×8
×8
DDR400B
DDR400B
DDR400B
×16 DDR333B
×16 DDR333B
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
166
166
166
166
166
P-TFBGA-60
P-TSOPII-66
P-TSOPII-66
P-TFBGA-60
P-TSOPII-66
×4
×8
×8
DDR333B
DDR333B
DDR333B
Industrial Temperature Range (-40 °C - 85 °C)
DDR400B( 3-3-3 )
HYI25D512160DT-5
HYI25D512160DC-5
DDR333B( 2.5-3-3 )
HYI25D512160DT-6
HYI25D512160DC-6
×16 DDR400B
×16 DDR400B
3-3-3
3-3-3
200
200
P-TSOPII-66
P-TFBGA-60
×16 DDR333B
×16 DDR333B
2.5-3-3
2.5-3-3
166
166
P-TSOPII-66
P-TFBGA-60
1) For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet.
2) CAS: Column Address Strobe
3) RCD: Row Column Delay
4) RP: Row Precharge
Rev. 1.01, 2008-07
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
2
Configuration
This chapter contains the chip configuration and block diagrams.
2.1
Configuration for TFBGA-60
The ball configuration of a DDR SDRAM is listed by function in Table 4. The abbreviations used in the Ball#/Buffer Type column
are explained in Table 5 and Table 6 respectively.
TABLE 4
Configuration
Ball#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2
CK1
CK1
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
G3
Complementary Clock Signal
Clock Enable
H3
Control Signals
H7
G8
G7
H8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
CS
Chip Select
Address Signals
J8
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus
Address Bus
J7
BA1
A0
K7
L8
L7
M8
M2
L3
L2
K3
K2
J3
A1
A2
A3
A4
A5
A6
A7
A8
A9
K8
A10
AP
A11
A12
J2
H2
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Ball#
Name
Pin
Type
Buffer
Type
Function
Data Signals ×4 Organization
B7
D7
D3
B3
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal Bus 3:0
Data Strobe ×4Organization
E3
Data Mask ×4 Organization
F3 DM
DQS
I/O
I
SSTL
SSTL
Data Strobe
Data Mask
Data Signals ×8 Organization
A8
B7
C7
D7
D3
C3
B3
A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal Bus 7:0
Data Strobe ×8 Organization
E3
Data Mask ×8 Organization
F3 DM
DQS
I/O
I
SSTL
SSTL
Data Strobe
Data Mask
Data Signals ×16 Organization
A8
B9
B7
C9
C7
D9
D7
E9
E1
D3
D1
C3
C1
B3
B1
A2
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Ball#
Name
Pin
Type
Buffer
Type
Function
Data Strobe ×16 Organization
E3
E7
UDQS
LDQS
I/O
I/O
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×16 Organization
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
F7
Power Supplies
F1
VREF
AI
—
—
I/O Reference Voltage
A9, B2, C8, D2, VDDQ
E8
PWR
I/O Driver Power Supply
A7, F8, M7
VDD
PWR
PWR
—
—
Power Supply
Power Supply
A1, B8, C2, D8, VSSQ
E2
A3, F2, M3
VSS
PWR
—
—
Power Supply
Not Connected
Not Connected ×4 Organization
A2, A8, B1, B9, NC
C1, C3, C7, C9,
D1, D9, E1, E7,
E9, F7, F9
NC
Not Connected ×8 Organization
B1, B9, C1, C9, NC
D1, D9, E1, E7,
E9, F7, F9
NC
—
—
Not Connected
Not Connected
Not Connected ×16 Organization
F9
NC
NC
TABLE 5
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only pin. Digital levels
Output. Digital levels
I/O is a bidirectional input/output signal
Input. Analog levels
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
Rev. 1.01, 2008-07
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
FIGURE 1
Configuration for x4 Organization, TFBGA-60, Top View
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Rev. 1.01, 2008-07
10
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 2
Configuration for x8 Organization, TFBGA-60, Top View
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Rev. 1.01, 2008-07
11
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 3
Configuration for x16 Organization, TFBGA-60, Top View
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Rev. 1.01, 2008-07
12
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
2.2
Configuration for TSOPII-66
The pin configuration of a DDR SDRAM is listed by function in Table 7. The abbreviations used in the Pin#/Buffer Type column
are explained in Table 8 and Table 9 respectively.
TABLE 7
Configuration
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
45
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal
46
CK
Complementary Clock Signal
Clock Enable
44
CKE
Control Signals
23
22
21
24
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
CS
Chip Select
Address Signals
26
27
29
30
31
32
35
36
37
38
39
40
28
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus
Address Bus
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
41
42
Data Signals ×4 Organization
5
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal Bus 3:0
11
56
62
Data Strobe ×4 Organization
51 DQS I/O
SSTL
Data Strobe
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HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
Data Mask ×4 Organization
47 DM
I
SSTL
Data Mask
Data Signals × 8 Organization
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal Bus 7:0
5
8
11
56
59
62
65
Data Strobe × 8 Organization
51 DQS I/O
Data Mask × 8 Organization
47 DM
Data Signals ×16 Organization
SSTL
SSTL
Data Strobe
Data Mask
I
2
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
11
13
54
56
57
59
60
62
63
65
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Data Strobe ×16 Organization
51
16
UDQS
LDQS
I/O
I/O
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×16 Organization
47
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
20
Power Supplies
49
VREF
AI
—
I/O Reference Voltage
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HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Pin#
Name
Pin
Type
Buffer
Type
Function
3, 9, 15, 55, 61 VDDQ
1, 18, 33 VDD
6, 12, 52, 58, 64 VSSQ
34,48, 66 VSS
PWR
PWR
PWR
PWR
—
—
—
—
I/O Driver Power Supply
Power Supply
Power Supply
Power Supply
Not Connected ×4 Organization
2, 4, 7, 8, 10,
13, 14, 16, 17,
19, 20, 25, 43,
50, 53, 54, 57,
59, 60, 63, 65
NC
NC
—
Not Connected
Not Connected × 8 Organization
4, 7, 10, 13, 14, NC
16, 17, 19, 20,
25, 43, 50, 53,
54, 57, 60, 63
NC
—
—
Not Connected ×16 Organization
14, 17, 19, 25, NC
43, 50, 53
NC
TABLE 8
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels
Output. Digital levels
I/O is a bidirectional input/output signal
Input. Analog levels
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 9
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR
Rev. 1.01, 2008-07
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 4
Configuration TSOPII-66, Top View
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Rev. 1.01, 2008-07
16
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3
Functional Description
The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
3.1
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM.
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TABLE 10
Mode Register Definition
Field
BL
Bits
Type1) Description
Burst Length
Note: All other bit combinations are RESERVED.
[2:0]
W
001B
010B
011B
2
4
8
BT
CL
3
Burst Type
0 Sequential
1 Interleaved
[6:4]
CAS Latency
Note: All other bit combinations are RESERVED.
010B
2
110B 2.5
011B
100B
3
4
MODE [12:7]
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3.1.1
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 11.
TABLE 11
Burst Definition
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
2
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1
0-1
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
8
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.01, 2008-07
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HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
3.2
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register.
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TABLE 12
Extended Mode Register
Field
Bits
Type1)
Description
DLL Status
DLL
0
w
0B
1B
Enabled
Disabled
DS
1
Drive Strength
0B
1B
Normal
Weak
MODE
[12:2]
Operating Mode
00000000000B Normal Operation
Notes
1. A2 must be 0 to provide compatibility with early DDR devices.
2. All other bit combinations are RESERVED.
1) w = write only register bit
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HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
4
Truth Tables
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate
SDRAM.
TABLE 13
Truth Table 1: Commands
Name (Function)
CS RAS CAS WE Address
MNE
Note
1)2)
Deselect (NOP)
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
NOP
NOP
1)2)
1)3)
1)4)
1)4)
1)5)
1)6)
1)7)8)
1)9)
No Operation (NOP)
Active (Select Bank And Activate Row)
Read (Select Bank And Column, And Start Read Burst)
Write (Select Bank And Column, And Start Write Burst)
Burst Terminate
Bank/Row ACT
H
H
H
L
Bank/Col
Bank/Col
X
Read
Write
BST
L
H
H
L
L
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
Mode Register Set
L
Code
PRE
L
H
L
X
AR/SR
MRS
L
L
Op-Code
1) CKE is HIGH for all commands shown exceptSelf Refresh.VREF must be maintained during Self Refresh operation.
2) Deselect and NOP are functionally interchangeable.
3) BA0, BA1 provide bank address and A0 - Ai provide row address.
4) BA0, BA1 provide bank address; A0 - Ai provide column address; A10 HIGH enables the Auto Precharge feature (nonpersistent), A10
LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0 - Ai provide the op-code to be written to the selected Mode
Register.
TABLE 14
Truth Table 2: DM Operation
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
X
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.01, 2008-07
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 15
Truth Table 3: Clock Enable (CKE)
Current State CKE n-1
CKEn
Command n
Action n
Notes
Previous
Cycle
Current
Cycle
1)
2)
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
L
L
X
Maintain Self-Refresh
Exit Self-Refresh
L
H
L
Deselect or NOP
X
L
Maintain Power-Down
Exit Power-Down
–
–
–
–
–
–
L
H
L
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See Table 16
H
H
H
H
Precharge Power-Down Entry
Self Refresh Entry
Active Power-Down Entry
–
L
L
H
1)
VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
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HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 16
Truth Table 4: Current State Bank n - Command to Bank n (same bank)
Current State CS
RAS CAS WE Command
Action
Notes
1)2)3)4)5)6)
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
Deselect
NOP. Continue previous operation.
NOP. Continue previous operation.
Select and activate row
–
1)2)3)4)5)6)
No Operation
Active
1)2)3)4)5)6)
Idle
1)2)3)4)5)6)7)
1)2)3)4)5)6)7)
1)2)3)4)5)6)8)
1)2)3)4)5)6)8)
1)2)3)4)5)6)9)
1)2)3)4)5)6)8)
1)2)3)4)5)6)9)
1)2)3)4)5)6)10)
1)2)3)4)5)6)8)11)
1)2)3)4)5)6)8)
1)2)3)4)5)6)9)11)
L
AUTO REFRESH
MODE REGISTER SET –
Read
L
L
Row Active
H
H
L
L
H
L
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
L
Write
H
L
L
Precharge
Read
Read (Auto
Precharge
Disabled)
H
L
H
L
Select column and start new Read burst
Truncate Read burst, start Precharge
BURST TERMINATE
H
H
L
Precharge
BURST TERMINATE
Read
H
H
H
L
L
Write (Auto
Precharge
Disabled)
H
L
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
L
Write
H
L
Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 15 and after tXSNR/tXSRD has been met (if the previous state
was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge
command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active
command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with
registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle
state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has
been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and
according to Table 17.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is
met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command
and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with
registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
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512-Mbit Double-Data-Rate SDRAM
TABLE 17
Truth Table 5: Current State Bank n - Command to Bank m (different bank)
Current State CS RAS CAS WE Command
Action
Notes
1)2)3)4)5)6)
Any
H
L
X
H
X
X
H
X
X
H
X
Deselect
NOP. Continue previous operation
1)2)3)4)5)6)
1)2)3)4)5)6)
No Operation
NOP. Continue previous operation
–
Idle
X
Any Command
Otherwise Allowed to
Bank m
1)2)3)4)5)6)
Row
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
Active
Select and activate row
Select column and start Read burst
Select column and start Write burst
–
1)2)3)4)5)6)7)
1)2)3)4)5)6)7)
1)2)3)4)5)6)
Activating,
Active, or
Precharging
H
H
L
Read
L
Write
H
H
L
L
Precharge
Active
1)2)3)4)5)6)
Read (Auto
Precharge
Disabled)
L
H
H
L
Select and activate row
Select column and start new Read burst
–
1)2)3)4)5)6)7)
1)2)3)4)5)6)
H
L
Read
H
H
L
Precharge
Active
1)2)3)4)5)6)
Write (Auto
Precharge
Disabled)
L
H
H
L
Select and activate row
Select column and start Read burst
Select column and start new Write burst
–
1)2)3)4)5)6)7)8)
1)2)3)4)5)6)7)
1)2)3)4)5)6)
H
H
L
Read
L
Write
H
H
L
L
Precharge
Active
1)2)3)4)5)6)
Read (With
Auto
Precharge)
L
H
H
L
Select and activate row
Select column and start new Read burst
Select column and start Write burst
–
1)2)3)4)5)6)7)9)
1)2)3)4)5)6)7)9)10)
1)2)3)4)5)6)
H
H
L
Read
L
Write
H
H
L
L
Precharge
Active
1)2)3)4)5)6)
Write (With
Auto
Precharge)
L
H
H
L
Select and activate row
Select column and start Read burst
Select column and start new Write burst
–
1)2)3)4)5)6)7)9)
1)2)3)4)5)6)7)9)
1)2)3)4)5)6)
H
H
L
Read
L
Write
H
L
Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 15: Clock Enable (CKE) and after tXSNR/tXSRD has been met,
if the previous state was self refresh)
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated,
and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge:This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto
precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
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512-Mbit Double-Data-Rate SDRAM
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from
a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 18.
10) A Write command may be applied after the completion of data output.
TABLE 18
Truth Table 6: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto Unit
Precharge Support
WRITE w/AP
Read or Read w/AP
Write to Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
1 + (BL/2) + tWTR
tCK
tCK
tCK
tCK
tCK
tCK
BL/2
1
Read w/AP
BL/2
CL (rounded up) + BL/2
1
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512-Mbit Double-Data-Rate SDRAM
5
Electrical Characteristics
This chapter describes the electrical characteristics.
5.1
Operating Conditions
This chapter contains the operating conditions tables.
TABLE 19
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note
Min.
Typ. Max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
VIN, VOUT
VIN
–0.5
–1
—
—
—
—
—
—
—
1
V
DDQ + 0.5
V
—
+3.6
+3.6
+3.6
+70
+85
+150
—
V
—
VDD
–1
V
—
VDDQ
TA
–1
V
—
0
°C
°C
°C
W
mA
for HYB...
–40
–55
—
for HYI...
Storage temperature (plastic)
TSTG
PD
—
—
—
Power dissipation (per SDRAM component)
Short circuit output current
IOUT
—
50
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
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512-Mbit Double-Data-Rate SDRAM
TABLE 20
Input and Output Capacitances
Parameter
Symbol
Values
Unit Note/ Test Condition
Min. Typ. Max.
Input Capacitance: CK, CK
CI1
2.0
1.5
—
—
—
—
—
—
—
—
—
—
3.0
2.5
pF
pF
TSOPII1)
TFBGA 1)
1)
Delta Input Capacitance
CdI1
CI2
0.25 pF
Input Capacitance: All other input-only pins
1.5
2.0
—
2.5
3.0
0.5
4.5
5.0
0.5
pF
pF
pF
pF
pF
pF
TFBGA 1)
TSOPII 1)
1)
Delta Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ, DQS, DM
CdIO
CIO
3.5
4.0
—
TFBGA 1)2)
TSOPII 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 100 MHz, TA = 25 °C,
OUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
V
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
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512-Mbit Double-Data-Rate SDRAM
TABLE 21
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note/Test Condition 1)
Min.
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
VDD
2.3
2.3
0
2.5
2.5
2.7
2.7
0
V
V
V
fCK ≤ 200 MHz
fCK ≤ 200 MHz 2)
—
VDDQ
Supply Voltage,
VSS, VSSQ
I/O Supply Voltage
3)
4)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
V
V
I/O Termination Voltage
(System)
VREF – 0.04
VREF + 0.04
5)
5)
5)
Input High (Logic1) Voltage VIH.DC
Input Low (Logic0) Voltage VIL.DC
V
REF + 0.15
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
V
V
–0.3
–0.3
Input Voltage Level,
CK and CK Inputs
VIN.DC
5)6)
7)
Input Differential Voltage,
CK and CK Inputs
VID.DC
0.36
0.71
–2
VDDQ + 0.6
V
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
μA
Input Leakage Current
II
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)
Output Leakage Current
IOZ
IOH
IOL
–5
5
μA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ
8)
Output High Current,
Normal Strength Driver
—
–16.2
—
mA
mA
V
OUT = 1.95 V
OUT = 0.35 V
Output Low Current,
16.2
V
Normal Strength Driver
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
2) Under all conditions, VDDQ must be less than or equal to VDD
.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF.DC. VREF is also expected to track noise variations in VDDQ
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
.
.
5) Inputs are not recognized as valid until VREF stabilizes.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
8) Values are shown per pin.
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512-Mbit Double-Data-Rate SDRAM
5.2
AC Characteristics
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions,
DD Specifications and Conditions, and Electrical Characteristics and AC Timing.
I
Notes
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 5 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC)
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
.
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew
Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest Industry specification
for DDR components.
FIGURE 5
AC Output Load Circuit Diagram / Timing Reference Load
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TABLE 22
AC Operating Conditions
Parameter
Symbol
Values
Max.
Unit Note/ Test
Condition
Min.
1)2)3)
Input High (Logic 1) Voltage, DQ, DQS and DM Signals VIH.AC
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals VIL.AC
V
REF + 0.31
—
V
1)2)3)
—
0.7
V
V
REF – 0.31
DDQ + 0.6
V
1)2)3)4)
Input Differential Voltage, CK and CK Inputs
Input Closing Point Voltage, CK and CK Inputs
VID.AC
VIX.AC
V
1)2)3)5)
0.5 × VDDQ– 0.2 0.5 × VDDQ+ 0.2
V
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until VREF stabilizes.
4) VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 23
AC Timing - Absolute Specifications
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition 1)
DDR400
DDR333
Min.
Max.
Min.
Max.
2)3)4)5)
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.7
+0.7
–0.7
+0.7
ns
CK high-level width
Clock cycle time
tCH
tCK
0.45
5
0.55
12
0.45
6
0.55
12
tCK
ns
ns
ns
ns
tCK
tCK
CL = 4.0 2)3)4)5)
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
2)3)4)5)
5
12
6
12
6
12
6
12
7
12
7.5
0.45
12
CK low-level width
tCL
0.45
0.55
0.55
2)3)4)5)6)
Auto precharge write recovery + tDAL
Min. : (tWR/tCK)+(tRP/tCK), Max. : —
precharge time
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width
(each input)
tDIPW
1.75
2)3)4)5)
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
ns
tCK
ns
ns
tCK
DQS input low (high) pulse width tDQSL,H
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
tDQSQ
tDQSS
+0.40
+0.40
1.25
+0.45
+0.40
1.25
TSOPII
2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1st DQS
latching transition
—
—
TFBGA
2)3)4)5)
2)3)4)5)
0.72
0.75
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512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition 1)
DDR400
Min.
DDR333
Min.
Max.
Max.
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
tDS
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from tDSH
tCK
CK (write cycle)
2)3)4)5)
2)3)4)5)
2)3)4)5)7)
DQS falling edge to CK setup
time (write cycle)
tDSS
tHP
0.2
—
0.2
—
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
Clock Half Period
min. (tCL,
—
min. (tCL,
tCH)
—
tCH
)
Data-out high-impedance time
from CK/CK
tHZ
—
+0.7
—
—
+0.7
—
Address and control input hold tIH
time
0.6
0.7
2.2
0.6
0.7
–0.7
2
0.75
0.8
2.2
0.75
0.8
–0.7
2
fast slew rate
3)4)5)6)8)
—
—
slow slew rate
3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse
width (each input)
tIPW
—
—
Address and control input setup tIS
time
—
—
fast slew rate
3)4)5)6)8)
—
—
slow slew
rate3)4)5)6)8)
2)3)4)5)7)
Data-out low-impedance time
from CK/CK
tLZ
+0.7
—
+0.7
—
2)3)4)5)
2)3)4)5)
Mode register set command
cycle time
tMRD
DQ/DQS output hold time from tQH
t
HP –tQHS
—
t
HP –tQHS
—
DQS
Data hold skew factor
Data hold skew factor
tQHS
—
+0.50
+0.50
—
—
+0.55
+0.50
ns
ns
TSOPII2)3)4)5)
tQHS
—
TFBGA
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRAP
tRAS
tRC
tRCD
40
—
tRCD
42
—
ns
ns
ns
70E+3
—
70E+3
—
Active to Active/Auto-refresh
command period
55
60
2)3)4)5)
Active to Read or Write delay
tRCD
tREFI
15
—
—
18
—
—
ns
2)3)4)5)8)
Average Periodic Refresh
Interval
7.8
7.8
μs
2)3)4)5)
Auto-refresh to Active/Auto-
refresh command period
tRFC
68
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B tRRD
command
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512-Mbit Double-Data-Rate SDRAM
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition 1)
DDR400
DDR333
Min.
Min.
Max.
Max.
2)3)4)5)
Write preamble
tWPRE
Max. (0.25 ×
—
Max. (0.25
× tCK, 1.5
ns)
—
ns
t
CK, 1.5 ns)
2)3)4)5)10)
2)3)4)5)11)
2)3)4)5)
Write preamble setup time
Write postamble
tWPRES
tWPST
tWR
0
—
0
—
ns
tCK
ns
tCK
0.40
15
2
0.60
—
0.40
15
1
0.60
—
Write recovery time
2)3)4)5)
Internal write to read command tWTR
—
—
delay
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
tXSRD
75
—
—
75
—
—
ns
Exit self-refresh to read
command
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns.
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH.AC and VIL.AC
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS
.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
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512-Mbit Double-Data-Rate SDRAM
TABLE 24
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN
;
IDD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤VILMAX; tCK = tCKMIN
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current: CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other
control inputs stable at ≥ VIHMIN or ≤ VILMAX; VIN=VREF for DQ, DQS and DM.
IDD2Q
IDD3P
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK= tCKMIN; VIN = VREF for DQ, DQS and DM.
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA
IDD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN
IDD4W
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
Rev. 1.01, 2008-07
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Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
TABLE 25
DD Specification
I
Symbol
–5
–6
Unit
Note1)
DDR400B
Max.
DDR333B
Max.
IDD0
IDD1
65
69
72
78
4,6
30
22
14
37
37
69
88
69
85
146
5
57
60
62
68
4,6
27
20
14
34
34
64
77
64
74
126
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×4/×8 2)3)
×163)
×4/×8 3)
×163)
3)
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
3)
3)
3)
×4/×8 3)
×16 3)
3)
IDD4R
IDD4W
×4/×8
×16 3)
3)
×4/×8
×163)
3)
IDD5
4)
IDD6
IDD6_low power
IDD7
2,5
198
213
2,5
178
167
Low power
×4/×8 3)
×16 3)
1) Test conditions : VDD = 2.7 V, TA = 10 °C.
2) IDD specifications are tested after the device is properly initialized and measured at 200 MHz.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 1.01, 2008-07
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08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
6
Package Outlines
The package used for this product family.
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
FIGURE 6
Package Outline P(G)-TSOPII-66
ꢀꢁ
ꢂꢃꢆꢅ
ꢆꢂꢃꢆꢈ
ꢄ
ꢄ
ꢄ
ꢆꢄ
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ꢆꢄ
ꢆꢄ
ꢂꢃꢈꢄ
ꢂꢃꢆ
ꢄ
ꢂꢃꢄ
ꢆꢄ
ꢂꢃꢆ ꢈꢈX
ꢅꢁ
ꢂꢃꢂꢇ
ꢂꢃꢅ
3%!4).' 0,!.%
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ꢅꢀ X ꢂꢃꢈꢄ ꢉ ꢀꢂꢃꢇ
-
ꢈꢈX
ꢂꢃꢆꢀ
ꢈꢈ
ꢅꢊ
ꢆ
ꢅꢅ
ꢀꢃꢄ -!8ꢃ
ꢆꢁ
ꢂꢃꢆꢅ
ꢀꢀꢃꢀꢀ
)NDEX -ARKING
ꢆꢁ $OES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF ꢂꢃꢆꢄ MAXꢃ PER SIDE
ꢀꢁ $OES NOT INCLUDE PLASTIC PROTRUSION OF ꢂꢃꢀꢄ MAXꢃ PER SIDE
ꢅꢁ $OES NOT INCLUDE DAMBAR PROTRUSION OF ꢂꢃꢆꢅ MAXꢃ
&0/?0?ꢌ43/0))?ꢌꢂꢈꢈꢌꢂꢂꢆ
Rev. 1.01, 2008-07
08102007-5IZ2-ENDV
34
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
FIGURE 7
Package Outline PG-TFBGA-60
ꢆꢀ
ꢆꢆ X ꢆ ꢉ ꢆꢆ
ꢆ
ꢂꢃꢆꢇ -!8ꢃ
ꢂꢃꢀ
ꢅꢁ
"
ꢅꢁ
ꢊꢁ
ꢄꢁ
ꢀꢁ
ꢆꢁ
!
ꢂꢃꢆ
#
ꢂꢃꢆ
#
ꢈꢂX
ꢂꢃꢆꢄ
ꢂꢃꢂꢇ
ꢂꢃꢂꢄ
ꢂꢃꢊꢄ
-
! "
3%!4).' 0,!.%
#
#
#
-
,EAD FREE SOLDER BALLS ꢏGREEN SOLDER BALLSꢁ
ꢆꢁ 0ACKAGE ORIENTATION MARK !ꢆ
ꢀꢁ "AD UNIT MARKING ꢏ"5-ꢁ ꢏLIGHT ꢉ GOODꢁ
ꢅꢁ -IDDLE OF PACKAGES EDGES
ꢊꢁ $UMMY PADS WITHOUT BALL
ꢄꢁ 3"! FIDUCIAL ꢏSOLDER BALL ATTACHꢁ
&0/?0'ꢌ4&"'!??ꢌꢂꢈꢂꢌꢂꢈꢀ
Rev. 1.01, 2008-07
35
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
7
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
TABLE 26
Example for Nomenclature Fields
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
DDR SDRAM
HYB
25
D
512
80
0
D
E
–5
TABLE 27
DDR Memory Components
Field Description
Values Coding
1
Qimonda Component Prefix
HYB
HYI
25
D
Memory components
Memory components, industrial temperature range (-40°C – +85 °C)
2
3
4
Interface Voltage [V]
DRAM Technology
2.5 V
Double Data Rate SDRAM
Component Density [Mbit]
64
128
256
512
40
80
16
0 .. 9
A
64 Mbit
128 Mbit
256 Mbit
512 Mbit
5
Number of I/Os
×4
×8
×16
6
7
Product Variant
Die Revision
–
First
B
Second
C
Third
D
Fourth
8
Package,
Lead-Free Status
C
FBGA, lead containing
TSOP, lead- and halogen-free
FBGA, lead- and halogen-free
TSOP, lead containing
Standard power product
DDR500B
E
F
T
9
Power
–
10
Speed Grade
–4
–4A
–5
–5A
–6
DDR500A
DDR400B
DDR400A
DDR333B
Rev. 1.01, 2008-07
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08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Configuration for x4 Organization, TFBGA-60, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuration for x8 Organization, TFBGA-60, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration for x16 Organization, TFBGA-60, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Configuration TSOPII-66, Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Outline P(G)-TSOPII-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outline PG-TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Rev. 1.01, 2008-07
37
08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for Lead-Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Truth Table 1: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Truth Table 2: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Truth Table 3: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Truth Table 4: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Truth Table 5: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 23
Truth Table 6: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC Timing - Absolute Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Example for Nomenclature Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DDR Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Rev. 1.01, 2008-07
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08102007-5IZ2-ENDV
Internet Data Sheet
HY[B/I]25D512[40/80/16]0D[C/E/F/T](L)
512-Mbit Double-Data-Rate SDRAM
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration for TFBGA-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration for TSOPII-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.1.1
3.2
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
5.1
5.2
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Product Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Rev. 1.01, 2008-07
39
08102007-5IZ2-ENDV
Internet Data Sheet
Edition 2008-07
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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