HYS64D32000HDL [QIMONDA]
200-Pin Small-Outline Dual-In-Line Memory Modules; 200引脚小外形双列直插式内存模块
| 型号： | HYS64D32000HDL |
| 厂家： | 
QIMONDA AG |
| 描述： | 200-Pin Small-Outline Dual-In-Line Memory Modules |
| 文件： | 总32页 (文件大小：904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2006
HYS64D32000HDL–[5/6]–C
HYS64D64020HDL–[5/6]–C
200-Pin Small-Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
HYS64D32000HDL–[5/6]–C, HYS64D64020HDL–[5/6]–C
Revision History: 2006-09, Rev. 1.11
Page
Subjects (major changes since last revision)
All
Adapted internet edition
Previous Revision: Rev. 1.10, 2005-12
22
updated tRFC for DDR400 from 70 ns to 65 ns
Previous Revision: Rev. 1.0, 2005-04
We Listen to Your Comments
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03292006-428D-USV0
2
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1
Overview
This chapter gives an overview of the 200-Pin Small-Outline Dual-In-Line Memory Modules product family and describes its
main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Non-parity 200-Pin Small-Outline Dual-In-Line Memory Modules
One rank 32M ×64 and two ranks 64M ×64 organization
Standard Double Data Rate Synchronous DRAMs ( )
Single +2.5 V (± 0.2 V) power supply and +2.6 V (± 0.1 V) for DDR400
Built with 512 Mbit s organized as ×16 in P–TSOPII–66 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
Standard form factor: 67.60 mm × 31.75 mm × 3.80 mm
Standard reference layout Raw Cards A and C
Gold plated contacts
RoHS Compliant Products1)
TABLE 1
Performance
Part Number Speed Code
–5
–6
–7
Unit
Speed Grade Component
Module
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
DDR266A
—
PC2100–2033
—
max. Clock
Frequency
@CL3
@CL2.5
@CL2
fCK3
–
MHz
MHz
MHz
fCK2.5
fCK2
166
166
143
133
133
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.11, 2006-09
3
03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1.2
Description
The HYS64D32000HDL–[5/6]–C and HYS64D64020HDL–
[5/6]–C are industry standard 200-Pin Small-Outline
Dual-In-Line Memory Modules (SO-DIMMs) organized as
64M ×64. The memory array is designed with Double Data
Rate Synchronous DRAMs ( ). A variety of de coupling
capacitors are mounted on the PC board. The DIMMs feature
serial presence detect based on a serial E2PROM device
using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
TABLE 2
Ordering Information for Lead-Free (RoHS Compliant Products)
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC3200 (CL=3.0)
HYS64D32000HDL–5–C
HYS64D64020HDL–5–C
PC2700 (CL=2.5)
PC3200S-3033–1–C0
PC3200S-3033–1–A0
One rank 256MB SO-DIMM
Two ranks 512MB SO-DIMM
512 MBit (×16)
512 MBit (×16)
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
PC2700S–2533–1–C0
PC2700S-2533–1–A0
One rank 256MB SO-DIMM
Two ranks 512MB SO-DIMM
512 MBit (×16)
512 MBit (×16)
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
HYS64D64020GDL–5–B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example
“30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Pre-charge latency of 3 clocks), JEDEC
SPD code definition version 1, and the Raw Card used for this module.
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered Small Outline DDR
SDRAM DIMM is listed by function in Table 3 (200 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
numbering is depicted in Figure 1.
TABLE 3
Pin Configuration of SO-DIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
35
CK0
CK1
CK2
NC
I
SSTL
SSTL
SSTL
–
Clock Signal
Clock Signal
Clock Signal
160
89
I
I
NC
37
CK0
CK1
CK2
NC
I
SSTL
SSTL
SSTL
–
Complement Clock
Complement Clock
Complement Clock
158
91
I
I
NC
96
95
CKE0
CKE1
I
I
SSTL
SSTL
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-ranks module
Note: 1-rank module
NC
NC
–
Control Signals
121
122
S0
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
S1
NC
NC
–
118
120
119
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
Address Signals
117
116
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 1:0
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
112
111
110
109
108
107
106
105
102
101
115
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 11:0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
100
99
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: 128 Mbit based module
Address Signal 13
NC
NC
I
–
123
A13
SSTL
Note: 1 Gbit based module
NC
NC
–
Note: Module based on 512 Mbit or smaller dies
Data Signals
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
7
13
17
6
8
14
18
19
23
29
31
20
24
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
30
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
Rev. 1.11, 2006-09
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
172
176
177
181
187
189
178
182
188
190
71
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
Data Bus 63:0
Check Bit 0
Check Bit 1
Check Bit 2
Check Bit 3
Check Bit 4
Check Bit 5
Check Bit 6
Check Bit 7
Data Strobes 7:0
NC
73
79
83
72
74
80
84
CB1
SSTL
–
NC
CB2
SSTL
–
NC
CB3
SSTL
–
NC
CB4
SSTL
–
NC
CB5
SSTL
–
NC
CB6
SSTL
–
NC
CB7
SSTL
–
NC
11
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
25
47
61
133
147
169
183
77
Data Strobe 8
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
12
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
NC
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
Data Mask 7:0
26
I
48
I
62
I
134
148
170
184
78
I
I
I
I
I
Data Mask 8
NC
EEPROM
195
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
193
I/O
Serial Bus Data
194
I
I
I
CMOS
CMOS
CMOS
Slave Address Select Bus 2:0
196
198
Power Supplies
1,2
VREF
VDDSPD
AI
–
–
I/O Reference Voltage
EEPROM Power Supply
197
PWR
Rev. 1.11, 2006-09
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
9,10,21,
22,
VDD
PWR
–
Power Supply
33,
34,
36,
45,
46,
57,
58,
69,
70,
81,
82,
92,
93,
94,
113,
114,
131,
132,
143,
144,
155,
156,
157,
167,
168,
179,
180,
191,
192
Rev. 1.11, 2006-09
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
3,4,
VSS
GND
–
Ground Plane
15,
16,
27,
28,
38, 39, 40,
51,
52,
63,
64,
75,
76,
87,
88, 90, 103,
104,
125,
126,
137,
138,
149,
150,
159,
161,
162,
173,
174,
185,
186
Other Pins
199
VDDID
NC
O
OD
–
VDD Identification
85,
NC
Not connected
86, 97, 98,
124,
200
Rev. 1.11, 2006-09
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 4
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.11, 2006-09
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03292006-428D-USV0
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Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
FIGURE 1
Pin Configuration Diagram 200-Pin SO-DIMM
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Rev. 1.11, 2006-09
13
03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 6
Address Format
Density Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
256MB
512MB
32M ×64
64M ×64
1
2
32M ×16
32M ×16
4
8
13/2/10
13/2/10
8K
8K
64 ms
64 ms
7.8 ms
7.8 ms
Notes
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
Rev. 1.11, 2006-09
14
03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
3
Electrical Characteristics
3.1
Operating Conditions
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note/ Test
Condition
min.
typ. max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
–1
–1
0
–
V
DDQ + 0.5
V
–
–
–
–
–
–
–
–
–
+3.6
+3.6
+3.6
+70
+150
–
V
VDD
–
V
VDDQ
TA
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
1
IOUT
–
50
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note/Test Condition 1)
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.3
2.5
2.3
2.5
2.3
0
2.5
2.6
2.5
2.6
2.5
2.7
2.7
2.7
2.7
3.6
0
V
V
V
V
V
V
fck ≤ 166 MHz
fck ≤ 166 MHz 2)
fck ≤ 166 MHz 3)
fck ≤ 166 MHz 2)3)
—
VDD
VDDQ
VDDQ
VDDSPD
Supply Voltage, I/O Supply
Voltage
VSS
,
—
VSSQ
VREF
VTT
4)
5)
Input Reference Voltage
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
VREF – 0.04 VREF + 0.04
V
V
I/O Termination Voltage
(System)
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition 1)
Min.
Max.
6)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
VIH(DC)
VIL(DC)
VIN(DC)
VREF + 0.15
–0.3
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
6)
V
6)
Input Voltage Level,
CK and CK Inputs
–0.3
V
6)7)
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
0.71
–2
VDDQ + 0.6
V
8)
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
Input Leakage Current
II
µA
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 9)
Output Leakage Current
IOZ
–5
5
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ
9)
Output High Current, Normal IOH
Strength Driver
—
–16.2
—
mA VOUT
=
1.95 V
Output Low Current, Normal IOL
Strength Driver
16.2
mA VOUT = 0.35 V
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
5) TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
.
.
V
.
6) Inputs are not recognized as valid until VREF stabilizes.
7) VID is the magnitude of the difference between the input level on CK and the input level on CK.
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per pin.
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
3.2
Current Specification and Conditions
TABLE 9
DD Conditions
I
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 10
DD Specification for HYS64D[32/64]0x0HDL–5–C
I
Product Type
Organization
HYS64D32000HDL–5–C
HYS64D64020HDL–5–CC
Unit
Note 1)2)
256MB
×64
512MB
×64
1 Rank
–5
2 Ranks
–5
Symbol
Typ.
Max.
Typ.
Max.
3)
IDD0
300
360
4
360
440
18
450
510
9
540
620
37
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
100
70
120
90
200
140
100
300
590
610
730
–
240
180
130
360
720
720
940
24
5)
5)
50
60
5)
150
440
460
580
–
180
540
540
760
12
3)4)
3)
3)
5)
IDD6
3)4)
IDD7
840
1000
990
1180
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note )
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
TABLE 11
DD Specification HYS64D[32/64]0x0HDL–6–C
I
Product Type
Organization
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
Unit
Note 1)2)
256MB
×64
512MB
×64
1 Rank
–6
2 Ranks
–6
Symbol
Typ.
Max.
Typ.
Max.
3)
IDD0
IDD1
IDD2P
280
320
4
340
380
18
410
450
9
500
540
37
mA
mA
mA
3)4)
5)
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
Organization
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
Unit
Note 1)2)
256MB
×64
512MB
×64
1 Rank
–6
2 Ranks
–6
Symbol
Typ.
Max.
Typ.
Max.
5)
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
80
100
90
170
120
90
200
180
120
320
620
640
860
24
mA
mA
mA
mA
mA
mA
mA
mA
mA
5)
60
5)
40
60
5)
130
380
400
520
–
160
460
480
700
12
260
510
530
650
–
3)4)
3)
3)
5)
IDD6
3)4)
IDD7
760
920
890
1080
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note )
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
3.3
AC Characteristics
TABLE 12
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note/ Test
Condition 1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
0.55
8
0.45
6
0.55
12
tCK
5
ns
ns
ns
tCK
tCK
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
12
6
12
7.5
12
7.5
0.45
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.55
2)3)4)5)6)
Auto precharge write recovery + tDAL
precharge time
(tWR/tCK)+(tRP/tCK
)
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width
(each input)
tDIPW
1.75
2)3)4)5)
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
ns
tCK
ns
tCK
DQS input low (high) pulse width tDQSL,H
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1st DQS
latching transition
tDQSQ
tDQSS
tDS
+0.40
1.25
+0.40
1.25
TFBGA
2)3)4)5)
2)3)4)5)
0.72
0.75
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from tDSH
CK (write cycle)
tCK
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
tHZ
min. (tCL, tCH
)
—
min. (tCL, tCH
–0.7
)
—
ns
ns
2)3)4)5)7)
Data-out high-impedance time
from CK/CK
—
+0.7
+0.7
Address and control input hold
time
tIH
0.6
0.7
2.2
—
—
—
0.75
0.8
—
—
—
ns
ns
ns
fast slew rate
3)4)5)6)8)
slow slew rate
3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse
width (each input)
tIPW
2.2
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
Max.
Min.
Max.
Address and control input setup tIS
time
0.6
—
0.75
—
ns
ns
ns
tCK
fast slew rate
3)4)5)6)8)
0.7
–0.7
2
—
0.8
–0.7
2
—
slow slew rate
3)4)5)6)8)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time
from CK/CK
tLZ
+0.7
—
+0.7
—
Mode register set command
cycle time
tMRD
DQ/DQS output hold time
Data hold skew factor
tQH
tHP –tQHS
—
—
tHP –tQHS
—
—
ns
ns
ns
tQHS
tRAP
tRAS
tRC
+0.50
—
+0.50
—
TFBGA 2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRCD
40
tRCD
42
2)3)4)5)
2)3)4)5)
70E+3
—
70E+3 ns
Active to Active/Auto-refresh
command period
55
60
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tREFI
15
—
—
18
—
—
ns
2)3)4)5)10)
Average Periodic Refresh
Interval
7.8
7.8
µs
2)3)4)5)
Auto-refresh to Active/Auto-
refresh command period
tRFC
65
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
tCK
ns
tCK
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
2
0.60
—
0.40
15
1
0.60
—
Write recovery time
2)3)4)5)
Internal write to read command tWTR
delay
—
—
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
—
75
—
—
ns
Exit self-refresh to read
command
tXSRD
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); DDQ = 2.6 V ± 0.1 V, DD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
.
t
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximun of eight Autorefresh commands can be posted to any given DDR SDRAM device
11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
Table 13 “SPD Codes for HYS64D[32/64][000/020]HDL–5–C” on Page 25
Table 14 “SPD Codes for HYS64D[32/64][000/020]HDL–6–C” on Page 28
TABLE 13
SPD Codes for HYS64D[32/64][000/020]HDL–5–C
Product Type
Organization
HYS64D32000HDL–5–C
HYS64D64020HDL–5–C
256MB
512MB
×64
×64
1 Rank (×16)
PC3200S–30331
Rev. 1.0
2 Ranks (×16)
PC3200S–30331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
40
00
04
50
70
00
82
10
00
01
0E
04
1C
01
02
80
08
07
0D
0A
02
40
00
04
50
70
00
82
10
00
01
0E
04
1C
01
02
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
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Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
Organization
HYS64D32000HDL–5–C
HYS64D64020HDL–5–C
512MB
256MB
×64
×64
1 Rank (×16)
PC3200S–30331
Rev. 1.0
HEX
2 Ranks (×16)
PC3200S–30331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DIMM Attributes
20
C1
60
70
75
70
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
00
10
76
7F
7F
7F
7F
7F
51
00
20
C1
60
70
75
70
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
00
10
77
7F
7F
7F
7F
7F
51
00
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
t
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
t
tRRDmin [ns]
t
RCDmin [ns]
RASmin [ns]
t
Module Density per Rank
tAS, tCS [ns]
t
AH, tCH [ns]
tDS [ns]
DH [ns]
36 - 40 Not used
t
41
42
43
44
45
46
47
tRCmin [ns]
t
RFCmin [ns]
CKmax [ns]
t
tDQSQmax [ns]
QHSmax [ns]
t
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
66
67
68
69
70
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
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HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
Organization
HYS64D32000HDL–5–C
HYS64D64020HDL–5–C
512MB
256MB
×64
×64
1 Rank (×16)
PC3200S–30331
Rev. 1.0
HEX
2 Ranks (×16)
PC3200S–30331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
00
xx
36
34
44
33
32
30
30
30
48
44
4C
35
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
00
xx
36
34
44
36
34
30
32
30
48
44
4C
35
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.11, 2006-09
27
03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 14
SPD Codes for HYS64D[32/64][000/020]HDL–6–C
Product Type
Organization
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
256MB
512MB
×64
×64
1 Rank (×16)
PC2700S–25331
Rev. 1.0
2 Ranks (×16)
PC2700S–25331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
40
00
04
60
70
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
30
48
80
08
07
0D
0A
02
40
00
04
60
70
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
30
48
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
Rev. 1.11, 2006-09
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03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
Organization
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
512MB
256MB
×64
×64
1 Rank (×16)
PC2700S–25331
Rev. 1.0
HEX
2 Ranks (×16)
PC2700S–25331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
30
31
32
33
34
35
tRASmin [ns]
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
1A
7F
7F
7F
7F
7F
51
00
00
xx
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
1B
7F
7F
7F
7F
7F
51
00
00
xx
Module Density per Rank
tAS, tCS [ns]
t
AH, tCH [ns]
tDS [ns]
DH [ns]
t
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
t
RFCmin [ns]
CKmax [ns]
t
tDQSQmax [ns]
QHSmax [ns]
t
not used
DIMM PCB Height
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
36
34
44
33
32
30
30
36
34
44
36
34
30
32
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Rev. 1.11, 2006-09
29
03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
Organization
HYS64D32000HDL–6–C
HYS64D64020HDL–6–C
512MB
256MB
×64
×64
1 Rank (×16)
PC2700S–25331
Rev. 1.0
HEX
2 Ranks (×16)
PC2700S–25331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 8
30
48
44
4C
36
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
30
48
44
4C
36
43
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.11, 2006-09
30
03292006-428D-USV0
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Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
5
Package Outlines
FIGURE 4
Package Outline SO-DIMM Raw Card A (L-DIM-200-6)
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31
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Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
FIGURE 5
Package Outline SO-DIMM Raw Card C (L-DIM-200-11)
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Rev. 1.11, 2006-09
32
03292006-428D-USV0
Internet Data Sheet
HYS64D[32/64][000/020]HDL–[5/6]–C
Small-Outline DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
3.2
3.3
4
5
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Rev. 1.11, 2006-09
33
03292006-428D-USV0
Internet Data Sheet
Edition 2006-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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