HYS72D32300GU-5-C [QIMONDA]
DDR DRAM Module, 32MX72, 0.5ns, CMOS, LEAD FREE, UDIMM-184;
| 型号： | HYS72D32300GU-5-C |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM Module, 32MX72, 0.5ns, CMOS, LEAD FREE, UDIMM-184 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总37页 (文件大小：1533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
HYS64D[16/32/64][300/301/320][G/H]U–5–C
HYS72D[32/64][300/301/320][G/H]U–5–C
HYS64D[16/32/64][300/301/320][G/H]U–6–C
HYS72D[32/64][300/301/320][G/H]U–6–C
184- Pin Unbuffered DDR SDRAM Modules
UDIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C,
HYS64D[16/32/64][300/301/320][G/H]U–6–C, HYS72D[32/64][300/301/320][G/H]U–6–C
Revision History: 2007-01, Rev. 1.11
Page
Subjects (major changes since last revision)
All
All
Qimonda update
Adapted internet edition
Previous Revision: Rev. 1.1
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
09152006-1LHY-N6G4
2
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Overview
1
Overview
1.1
Features
•
184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Server main memory
applications
•
•
One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
and +2.6V (±0.1V) ppower supply for DDR400
•
•
•
•
•
•
•
•
•
Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 Speed Grade supported
Table 1
Performance
Product Type Speed Code
Module Speed Grade
Component Module
–5
–6
Unit
—
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
—
Max. Clock Frequency
@ CL = 3
@ CL = 2.5
@ CL = 2
fCK3
MHz
MHz
MHz
fCK2.5
fCK2
166
166
133
133
1.2
Description
The HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C,
HYS64D[16/32/64][300/301/320][G/H]U–6–C and HYS72D[32/64][300/301/320][G/H]U–6–C are industry
standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 16M ×64, 32M ×64 and 64M ×64
for non-parity and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is designed
with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the
printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer
Internet Data Sheet
3
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Overview
Table 2
Ordering Information for Lead-Free Products
Product Type2)
Compliance Code
Description
SDRAM Technology
PC3200 (CL=3)
HYS64D16301GU–5–C
HYS64D32300GU–5–C
HYS72D32300GU–5–C
HYS64D64320GU–5–C
HYS72D64320GU–5–C
PC2700 (CL=2.5)
PC3200U–30330–C0 one rank 128MB DIMM
PC3200U–30330–A0 one rank 256MB DIMM
256 Mbit (×16)
256 Mbit (×8)
PC3200U–30330–A0 one rank 256MB ECC-DIMM 256 Mbit (×8)
PC3200U–30330–B0 two ranks 512MB DIMM 256 Mbit (×8)
PC3200U–30330–B0 two ranks 512MB ECC-DIMM 256 Mbit (×8)
HYS64D16301GU–6–C
HYS64D32300GU–6–C
HYS72D32300GU–6–C
HYS64D64320GU–6–C
HYS72D64320GU–6–C
PC2700U–25330–C0 one rank 128MB DIMM
PC2700U–25330–A0 one rank 256MB DIMM
256 Mbit (×16)
256 Mbit (×8)
PC2700U–25330–A0 one rank 256MB ECC-DIMM 256 Mbit (×8)
PC2700U–25330–B0 two ranks 512MB DIMM 256 Mbit (×8)
PC2700U–25330–B0 two ranks 512MB ECC-DIMM 256 Mbit (×8)
Table 3
Ordering Information for Lead-Free (RoHS1) Compliant Products)
Product Type2)
Compliance Code
Description
SDRAM Technology
PC3200 (CL=3)
HYS64D16301HU–5–C
HYS64D32300HU–5–C
HYS72D32300HU–5–C
HYS64D64320HU–5–C
HYS72D64320HU–5–C
PC2700 (CL=2.5)
PC3200U–30330–C0
PC3200U–30330–A0
PC3200U–30330–A0
PC3200U–30330–B0
PC3200U–30330–B0
one rank 128MB DIMM
256 Mbit (×16)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
one rank 256MB DIMM
one rank 256MB ECC-DIMM
two ranks 512MB DIMM
two ranks 512MB ECC-DIMM
HYS64D16301HU–6–C
HYS64D32300HU–6–C
HYS72D32300HU–6–C
HYS64D64320HU–6–C
HYS72D64320HU–6–C
PC2700U–25330–C0
PC2700U–25330–A0
PC2700U–25330–A0
PC2700U–25330–B0
PC2700U–25330–B0
one rank 128MB DIMM
256 Mbit (×16)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
one rank 256MB DIMM
one rank 256MB ECC-DIMM
two ranks 512MB DIMM
two ranks 512MB ECC-DIMM
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
2) All part numbers end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The Compliance Code is printed
on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example
“20330” means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks, Row Precharge latency of
3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
Internet Data Sheet
4
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM Table 4
DIMM is listed by function in Table 4 (184 pins). The
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
abbreviations used in columns Pin and Buffer Type are
explained in Table 5 and Table 6 respectively. The pin
numbering is depicted in Figure 1.
Type Type
122 A8
27 A9
I
I
I
I
I
I
SSTL Address Bus 11:0
SSTL
141 A10
AP
SSTL
Table 4
Pin Configuration of UDIMM
SSTL
Pin# Name Pin Buffer Function
Type Type
118 A11
115 A12
SSTL
SSTL Address Signal 12
Clock Signals
Note:Module based on
256 Mbit or larger
dies
137 CK0
NC
I
SSTL Clock Signals 2:0
NC
—
16
76
CK1
CK2
I
SSTL
NC
NC
I
—
Note:128 Mbit based
module
I
SSTL
138 CK0
NC
I
SSTL Complement Clock
167 A13
SSTL Address Signal 13
Signals 2:0
NC
—
Note:1 Gbit based
module
17
75
21
CK1
I
I
I
I
SSTL
SSTL
CK2
NC
NC
—
Note:Module based on
512 Mbit or
CKE0
SSTL Clock Enable Rank 0
SSTL Clock Enable Rank 1
Note: 2-rank module
smaller dies
111 CKE1
Data Signals
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus 63:0
SSTL
NC
NC
—
Note: 1-rank module
4
Control Signals
6
SSTL
157 S0
158 S1
I
I
SSTL Chip Select Rank 0
SSTL Chip Select Rank 1
Note: 2-rank module
8
SSTL
94
95
98
99
12
13
19
20
SSTL
SSTL
NC
NC
—
Note: 1-rank module
SSTL
154 RAS
I
I
SSTL Row Address Strobe
SSTL
65
CAS
SSTL Column Address
Strobe
SSTL
63
WE
I
SSTL Write Enable
SSTL
Address Signals
DQ10 I/O
DQ11 I/O
SSTL
59
52
48
43
41
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
SSTL Bank Address Bus
SSTL
2:0
SSTL
105 DQ12 I/O
106 DQ13 I/O
109 DQ14 I/O
110 DQ15 I/O
SSTL
SSTL Address Bus 11:0
SSTL
A1
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
A2
SSTL
130 A3
23
24
28
31
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
SSTL
37
32
A4
A5
SSTL
SSTL
125 A6
29 A7
SSTL
114 DQ20 I/O
117 DQ21 I/O
SSTL
SSTL
Internet Data Sheet
5
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4
Pin Configuration of UDIMM (cont’d)
Table 4
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
Type Type
Pin# Name Pin Buffer Function
Type Type
121 DQ22 I/O
123 DQ23 I/O
SSTL Data Bus 63:0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
178 DQ62 I/O
179 DQ63 I/O
SSTL Data Bus 63:0
SSTL
33
35
39
40
DQ24 I/O
DQ25 I/O
DQ26 I/O
DQ27 I/O
44
45
49
51
CB0
I/O
SSTL Check Bit 0
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 1
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 2
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 3
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 4
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 5
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 6
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 7
Note:ECC type module
Note:Non-ECC module
NC
NC
I/O
—
CB1
126 DQ28 I/O
127 DQ29 I/O
131 DQ30 I/O
133 DQ31 I/O
NC
NC
I/O
—
CB2
53
55
57
60
DQ32 I/O
DQ33 I/O
DQ34 I/O
DQ35 I/O
NC
NC
I/O
—
CB3
NC
NC
I/O
—
146 DQ36 I/O
147 DQ37 I/O
150 DQ38 I/O
151 DQ39 I/O
134 CB4
NC
NC
I/O
—
135 CB5
61
64
68
69
DQ40 I/O
DQ41 I/O
DQ42 I/O
DQ43 I/O
NC
NC
I/O
—
142 CB6
153 DQ44 I/O
155 DQ45 I/O
161 DQ46 I/O
162 DQ47 I/O
NC
NC
I/O
—
144 CB7
NC
NC
—
72
73
79
80
DQ48 I/O
DQ49 I/O
DQ50 I/O
DQ51 I/O
5
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
SSTL Data Strobe Bus 7:0
14
25
36
56
67
78
86
47
SSTL
SSTL
SSTL
165 DQ52 I/O
166 DQ53 I/O
170 DQ54 I/O
171 DQ55 I/O
SSTL
SSTL
SSTL
SSTL
83
84
87
88
DQ56 I/O
DQ57 I/O
DQ58 I/O
DQ59 I/O
SSTL Data Strobe 8
Note:ECC type module
NC
NC
—
Note:Non-ECC module
174 DQ60 I/O
175 DQ61 I/O
Internet Data Sheet
6
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4
Pin Configuration of UDIMM (cont’d)
Table 4
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
Type Type
Pin# Name Pin Buffer Function
Type Type
97
DM0
I
I
I
I
I
I
I
I
I
SSTL Data Mask Bus 7:0
7,
38,
46,
70,
VDD
PWR —
Power Supply
107 DM1
119 DM2
129 DM3
149 DM4
159 DM5
169 DM6
177 DM7
140 DM8
SSTL
SSTL
SSTL
85,
SSTL
108,
120,
148,
168
SSTL
SSTL
SSTL
3,
11,
18,
26,
VSS
GND —
Ground Plane
SSTL Data Mask 8
Note: ECC type module
NC
NC
—
Note: Non-ECC module
EEPROM
34,
42,
50,
58,
66,
74,
81,
92
91
SCL
SDA
I
CMOS Serial Bus Clock
OD Serial Bus Data
CMOS Slave Address Select
I/O
181 SA0
182 SA1
183 SA2
I
I
I
Bus 2:0
CMOS
CMOS
89,
93,
Power Supplies
AI
1
VREF
—
I/O Reference Voltage
100,
116,
124,
132,
139,
145,
152,
160,
176
184 VDDSPD PWR —
EEPROM Power
Supply
15, VDDQ
22,
PWR —
I/O Driver Power
Supply
30,
54,
62,
77,
96,
Other Pins
104,
112,
128,
136,
143,
156,
164,
172,
180
82
VDDID
O
OD
VDD Identification
9,
10,
71,
90,
101,
102,
103,
113,
163,
173
NC
NC
—
Not connected
Internet Data Sheet
7
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 5
Abbreviations for Pin Type
Table 6
Abbreviations for Buffer Type
Abbreviation Description
Abbreviation Description
I
Standard input-only pin. Digital levels.
SSTL
Serial Stub Terminalted Logic (SSTL2)
O
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
LV-CMOS
CMOS
OD
Low Voltage CMOS
CMOS Levels
I/O
AI
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
PWR
GND
NC
Ground
Not Connected
V
REF - Pin 001
- Pin 003
Pin 093 - VSS
Pin 094 - DQ04
Pin 095 - DQ05
DQ00 - Pin 002
DQ01 - Pin 004
DQ02 - Pin 006
DQ03 - Pin 008
NC - Pin 010
V
SS
V
Pin 096 -
DDQ
DQS0 - Pin 005
VDD - Pin 007
NC - Pin 009
Pin 097 - DM0
Pin 099 - DQ07
Pin 101 - NC
Pin 098 - DQ06
V
Pin 100 -
SS
Pin 102 - NC
V
- Pin 011
Pin 103 - NC
SS
V
DQ08 - Pin 012
DQS1 - Pin 014
CK1 - Pin 016
VSS - Pin 018
Pin 104 -
DDQ
DQ09 - Pin 013
- Pin 015
Pin 105 - DQ12
Pin 107 - DM1
Pin 109 - DQ14
Pin 111 - CKE1/NC
Pin 113 - NC
Pin 106 - DQ13
V
DDQ
V
Pin 108 -
DD
CK1 - Pin 017
DQ10 - Pin 019
CKE0 - Pin 021
DQ16 - Pin 023
DQS2 - Pin 025
A9 - Pin 027
Pin 110 - DQ15
V
DQ11 - Pin 020
Pin 112 -
DDQ
VDDQ
- Pin 022
Pin 114 - DQ20
Pin 115 - A12/NC
Pin 117 - DQ21
Pin 119 - DM2
Pin 121 - DQ22
Pin 123 - DQ23
Pin 125 - A6
V
DQ17 - Pin 024
Pin 116 -
SS
V
- Pin 026
Pin 118 - A11
SS
V
DQ18 - Pin 028
VDDQ
Pin 120 -
DD
A7 - Pin 029
- Pin 030
A5 - Pin 032
Pin 122 - A8
DQ19 - Pin 031
DQ24 - Pin 033
DQ25 - Pin 035
A04 - Pin 037
V
Pin 124 -
SS
V
- Pin 034
Pin 126 - DQ28
SS
Pin 127 - DQ29
Pin 129 - DM3
Pin 131 - DQ30
Pin 133 - DQ31
Pin 135 - CB5/NC
Pin 137 - CK0/NC
V
DQS3 - Pin 036
Pin 128 -
DDQ
V
- Pin 038
Pin 130 - A3
DD
DQ26 - Pin 039
A2 - Pin 041
V
DQ27 - Pin 040
VSS
Pin 132 -
SS
- Pin 042
CB00/NC - Pin 044
Pin 134 - CB4/NC
A1 - Pin 043
V
Pin 136 -
DDQ
CB01/NC - Pin 045
DQS8/NC - Pin 047
CB02/NC - Pin 049
CB03/NC - Pin 051
V
- Pin 046
Pin 138 - CK0/NC
Pin 140 - DM8/NC
Pin 142 - CB06/NC
Pin 144 - CB7/NC
DD
Pin 139 - V
SS
A0 - Pin 048
VSS
Pin 141 - A10/AP
Pin 143 - VDDQ
- Pin 050
BA1 - Pin 052
DQ32 -
DQ33 -
DQ34 -
BA0 -
Pin 145 - V
Pin 053
Pin 055
Pin 057
Pin 059
Pin 061
Pin 063
Pin 065
Pin 067
Pin 069
Pin 071
Pin 073
Pin 075
Pin 077
Pin 079
Pin 081
Pin 083
Pin 085
Pin 087
Pin 089
Pin 091
SS
VDDQ
Pin 146 - DQ36
- Pin 054
Pin 147 - DQ37
Pin 149 - DM4
Pin 151 - DQ39
Pin 153 - DQ44
Pin 155 - DQ45
Pin 157 - S0
V
Pin 148 -
Pin 150 - DQ38
VSS
- Pin 056
- Pin 058
DQS4
VSS
DD
Pin 152 -
Pin 154 - RAS
VDDQ
DQ35 - Pin 060
DQ40 -
WE -
V
- Pin 062
DDQ
Pin 156 -
Pin 158 - S1/NC
DQ41 - Pin 064
CAS -
DQS5 -
DQ43 -
NC -
VSS
- Pin 066
Pin 159 - DM5
Pin 161 - DQ46
Pin 163 - NC
V
Pin 160 -
Pin 162 - DQ47
VDDQ
- Pin 068
- Pin 070
DQ42
VDD
SS
Pin 164 -
Pin 166 - DQ53
VDD
DQ48 - Pin 072
DQ49 -
CK2 -
Pin 165 - DQ52
Pin 167 - A13/NC
Pin 169 - DM6
Pin 171 - DQ51
Pin 173 - NC
V
- Pin 074
SS
Pin 168 -
Pin 170 - DQ54
CK2 - Pin 076
V
-
DDQ
DQS6 - Pin 078
DQ50 -
V
Pin 172 -
Pin 174 - DQ60
VSS
- Pin 080
- Pin 082
DQ51
VDDID
DDQ
V
-
SS
DQ56 -
VDD
DQ58 -
Pin 175 - DQ61
Pin 177 - DM7
Pin 179 - DQ63
Pin 181 - SA0
Pin 183 - SA2
Pin 176 -
Pin 178 - DQ62
DQ57 - Pin 084
- Pin 086
-
DQS7
V
Pin 180 -
Pin 182 - SA1
DQ59 - Pin 088
NC - Pin 090
DDQ
V
-
SS
SDA -
V
Pin 184 -
- Pin 092
SCL
DDSPD
MPPD0030
Figure 1
Pin Configuration 184-Pin, UDIMM
Internet Data Sheet
8
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 7
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
SDRAMs columns bits
Ranks
128MB
256MB
256MB
512MB
512MB
16M ×64
32M ×64
32M ×72
64M ×64
64M ×72
1
1
1
2
2
16M ×16
32M ×8
32M ×8
32M ×8
32M ×8
4
13/2/9
8K
8K
8K
8K
8K
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
8
13/2/10
13/2/10
13/2/10
13/2/10
9
16
18
Internet Data Sheet
9
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 8
Absolute Maximum Ratings
Parameter
Symbol
Values
Typ.
Unit Note/ Test
Condition
Min.
VIN, VOUT –0.5
Max.
V
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
—
—
—
—
—
—
1
DDQ +0.5 V
—
—
—
—
—
—
—
—
VIN
–1
–1
–1
0
+3.6
+3.6
+3.6
+70
+150
—
V
VDD
VDDQ
TA
V
V
°C
°C
W
mA
TSTG
PD
–55
—
—
Power dissipation (per SDRAM component)
Short circuit output current
IOUT
50
—
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 9
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Typ.
Unit Note/ Test Condition 1)
Min.
2.3
2.5
2.3
2.5
Max.
2.7
2.7
2.7
2.7
3.6
0
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.5
2.6
2.5
2.6
2.5
—
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
f
VDDSPD 2.3
—
—
Supply Voltage, I/O Supply VSS,
0
Voltage
VSSQ
VREF
VREF
Input Reference Voltage
Input Reference Voltage
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
DDQ / 2 DDQ / 2 DDQ/ 2
– 50 mV + 50 mV
V
V
fCK ≤ 166 MHz 4)
f
CK > 166 MHz 2)4)
V
V
V
5)
I/O Termination Voltage
(System)
VTT
V
REF – 0.04 —
V
REF + 0.04 V
8)
8)
8)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15 —
V
V
V
DDQ + 0.3
V
–0.3
—
—
REF – 0.15 V
Input Voltage Level,
CK and CK Inputs
VIN(DC) –0.3
DDQ + 0.3
DDQ + 0.6
V
V
8)6)
Input Differential Voltage, VID(DC) 0.36
—
V
CK and CK Inputs
Internet Data Sheet
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Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 9
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Values
Typ.
Unit Note/ Test Condition 1)
Min.
Max.
7)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
—
1.4
—
Input Leakage Current
II
–2
—
2
µA Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)9)
Output Leakage Current
IOZ
IOH
IOL
–5
—
—
—
5
µA DQs are disabled;
8)
0 V ≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver
—
–16.2
—
mA
mA
V
OUT = 1.95 V 8)
Output Low
16.2
V
OUT = 0.35 V 8)
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2 % VREF (DC). VREF is also expected to track noise variations in VDDQ
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF
.
.
.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Internet Data Sheet
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Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
Table 10
IDD Conditions
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50 % of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Internet Data Sheet
12
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 11
IDD Specification for PC3200
Unit Note 1)2)
128MB
×64
256MB
×64
256MB
×72
512MB
×64
512MB
×72
1 Rank
–5
1 Rank
–5
1 Rank
–5
2 Ranks
–5
2 Ranks
–5
Symbol Typ. Max. Typ.
Max. Typ.
Max. Typ. Max. Typ.
Max.
1215
1305
90
3)
IDD0
300 360
380 440
560
640
32
720
800
40
630
720
36
810
900
45
864
944
64
1080 972
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
1160 1062
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
16
20
80
72
5)
120 144
240
160
104
304
680
720
288
224
144
360
800
840
270
180
117
342
765
810
324
252
162
405
900
945
480
320
208
608
984
576
448
288
720
540
360
234
684
648
5)
80
52
112
72
504
5)
324
5)
172 216
400 480
400 520
560 760
810
3)4)
3)
1160 1107
1305
1350
2115
50
1024 1200 1152
3)
1120 1520 1260 1710 1424 1880 1602
11 22 13 25 22 45 25
840 1000 1680 2000 1890 2250 1984 2360 2232
IDD6
6
11
—
3)4)
IDD7
2655
1) Module IDD values are calculated on the basis of component IDD and can be measured differently depending on actual to
DQ loading capacitance.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Internet Data Sheet
13
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 12
IDD Specification for PC2700
Unit Note 1)2)
128MB
×64
256MB
×64
256MB
×72
512MB
×64
512MB
×72
1 Rank
–6
1 Rank
–6
1 Rank
–6
2 Ranks
–6
2 Ranks
–6
Symbol Typ. Max. Typ.
Max. Typ.
Max. Typ. Max. Typ.
Max.
1017
1107
90
3)
IDD0
260 300
320 380
480
560
32
600
680
40
540
630
36
675
765
45
736
816
64
904
984
80
828
918
72
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
16
20
5)
100 340
200
136
88
240
192
120
304
680
720
225
153
99
270
216
135
342
765
810
400
272
176
512
816
856
480
384
240
608
984
450
306
198
576
918
540
5)
68
44
96
60
432
5)
270
5)
144 180
340 400
360 440
480 640
256
560
600
960
11
288
630
675
684
3)4)
3)
1107
1152
1782
25
1024 963
3)
1280 1080 1440 1216 1584 1368
22 13 25 44 22 25
IDD6
6
11
—
3)4)
IDD7
720 860
1440 1720 1620 1935 1696 2024 1908
2277
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Internet Data Sheet
14
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.3
AC Characteristic
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
Min.
Max.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
5
0.55
8
0.45
6
0.55
12
tCK
ns
ns
ns
CL = 3.0
2)3)4)5)
6
12
6
12
CL = 2.5
2)3)4)5)
7.5
12
7.5
0.45
12
CL = 2.0
2)3)4)5)
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.55
tCK
tCK
2)3)4)5)6)
Auto precharge write recovery + tDAL
(tWR/tCK)+(tRP/tCK)
precharge time
2)3)4)5)
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
DQ and DM input pulse width
(each input)
tDIPW
1.75
2)3)4)5)
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.6
+0.6
—
–0.6
0.35
—
+0.6
—
ns
tCK
ns
tCK
DQS input low (high) pulse width tDQSL,H 0.35
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1st DQS
tDQSQ
tDQSS
tDS
—
+0.40
1.25
+0.45
1.25
TSOPII
2)3)4)5)
2)3)4)5)
0.72
0.75
latching transition
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from tDSH
tCK
CK (write cycle)
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
tHZ
min. (tCL, tCH) —
min. (tCL, tCH) —
ns
ns
2)3)4)5)7)
Data-out high-impedance time
from CK/CK
—
+0.7
–0.7
0.75
0.8
+0.7
Address and control input hold
time
tIH
0.6
0.7
—
—
—
—
ns
ns
fast slew rate
3)4)5)6)8)
slow slew
rate
3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse
width (each input)
tIPW
2.2
—
2.2
—
ns
Internet Data Sheet
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Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700 (cont’d)
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition 1)
DDR333
Min.
Min.
Max.
Max.
Address and control input setup tIS
time
0.6
—
0.75
—
ns
ns
fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
slow slew
rate
3)4)5)6)8)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time
from CK/CK
tLZ
–0.7
2
+0.7
—
–0.7
2
+0.7
—
ns
Mode register set command cycle tMRD
time
tCK
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP – tQH
—
t
HP – tQHS
—
ns
ns
tQHS
—
+0.50
—
+0.55
TSOPII
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRAP
tRAS
tRC
tRCD
40
—
tRCD
—
ns
70E+3 42
70E+3 ns
Active to Active/Auto-refresh
command period
55
—
60
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
15
—
65
—
18
—
72
—
ns
µs
ns
2)3)4)5)10)
2)3)4)5)
Average Periodic Refresh Interval tREFI
7.8
—
7.8
—
Auto-refresh to Active/Auto-
refresh command period
tRFC
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
0.60
—
0.40
15
0.60
—
tCK
ns
Write recovery time
2)3)4)5)
Internal write to read command
delay
tWTR
2
—
1
—
tCK
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
—
75
—
—
ns
Exit self-refresh to read command tXSRD
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
Internet Data Sheet
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Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Internet Data Sheet
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Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
4
SPD Contents
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
Table 14 “SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C” on Page 18
Table 15 “SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–6–C” on Page 22
Table 16 “SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–5–C” on Page 25
Table 17 “SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–6–C” on Page 28
Table 14
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
09
01
40
00
04
50
50
00
82
10
00
80
08
07
0D
0A
01
40
00
04
50
50
00
82
08
00
80
08
07
0D
0A
01
48
00
04
50
50
02
82
08
08
80
08
07
0D
0A
02
40
00
04
50
50
00
82
08
00
80
08
07
0D
0A
02
48
00
04
50
50
02
82
08
08
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
Internet Data Sheet
18
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
CCD [cycles]
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
t
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
20
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
Module Density per Rank
tAS,
tAH,
t
t
CS [ns]
CH [ns]
t
t
DS [ns]
DH [ns]
36 - 40 Not used
41
42
43
44
45
46
t
t
t
t
t
RCmin [ns]
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
Not used
Internet Data Sheet
19
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
47
DIMM PCB Height
00
00
00
E4
7F
7F
7F
7F
7F
51
00
00
xx
00
00
00
FD
7F
7F
7F
7F
7F
51
00
00
xx
00
00
00
0F
7F
7F
7F
7F
7F
51
00
00
xx
00
00
00
FE
7F
7F
7F
7F
7F
51
00
00
xx
00
00
00
10
7F
7F
7F
7F
7F
51
00
00
xx
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
36
34
44
31
36
33
30
31
47
55
35
43
20
20
20
36
34
44
33
32
33
30
30
47
55
35
43
20
20
20
37
32
44
33
32
33
30
30
47
55
35
43
20
20
20
36
34
44
36
34
33
32
30
47
55
35
43
20
20
20
37
32
44
36
34
33
32
30
47
55
35
43
20
20
20
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Internet Data Sheet
20
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 14
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
88
89
90
91
92
93
94
Part Number, Char 16
20
20
20
1x
xx
xx
xx
xx
00
20
20
20
1x
xx
xx
xx
xx
00
20
20
20
1x
xx
xx
xx
xx
00
20
20
20
1x
xx
xx
xx
xx
00
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Internet Data Sheet
21
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U–
PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
09
01
40
00
04
60
70
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
01
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
Internet Data Sheet
22
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U–
PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
28
29
30
31
32
33
34
35
t
t
t
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
30
48
2A
20
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
E8
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
01
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
13
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
02
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
14
7F
7F
7F
7F
7F
51
00
00
xx
Module Density per Rank
tAS,
tAH,
t
t
t
t
CS [ns]
CH [ns]
DS [ns]
DH [ns]
36 - 40 Not used
41
42
43
44
45
46
47
t
t
t
t
t
RCmin [ns]
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
Not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
66
67
68
69
70
71
72
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Internet Data Sheet
23
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 15
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U–
PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 1
36
34
44
31
36
33
30
31
47
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
36
34
44
33
32
33
30
30
47
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
37
32
44
33
32
33
30
30
47
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
36
34
44
36
34
33
32
30
47
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
37
32
44
36
34
33
32
30
47
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Internet Data Sheet
24
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 16
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
09
01
40
00
04
50
50
00
82
10
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
80
08
07
0D
0A
01
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
80
08
07
0D
0A
01
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
80
08
07
0D
0A
02
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
80
08
07
0D
0A
02
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
Internet Data Sheet
25
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 16
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
28
t
t
t
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
28
3C
28
20
60
60
40
40
00
37
41
28
28
50
00
00
00
00
E4
7F
7F
7F
7F
7F
51
00
00
xx
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
00
00
00
FD
7F
7F
7F
7F
7F
51
00
00
xx
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
00
00
00
0F
7F
7F
7F
7F
7F
51
00
00
xx
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
00
00
00
FE
7F
7F
7F
7F
7F
51
00
00
xx
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
00
00
00
10
7F
7F
7F
7F
7F
51
00
00
xx
29
30
31
Module Density per Rank
32
tAS,
tAH,
t
t
t
CS [ns]
33
tCH [ns]
34
DS [ns]
35
DH [ns]
36 - 40
41
Not used
t
t
t
t
t
RCmin [ns]
42
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
43
44
45
46
Not used
47
DIMM PCB Height
48 - 61
62
Not used
SPD Revision
63
Checksum of Byte 0-62
64
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
65
66
67
68
69
70
71
72
Internet Data Sheet
26
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 16
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–5–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC3200U– PC3200U– PC3200U– PC3200U– PC3200U–
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
30330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95 - 98
Part Number, Char 1
36
34
44
31
36
33
30
31
48
55
35
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
36
34
44
33
32
33
30
30
48
55
35
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
37
32
44
33
32
33
30
30
48
55
35
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
36
34
44
36
34
33
32
30
48
55
35
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
37
32
44
36
34
33
32
30
48
55
35
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
99 - 127 Not used
Internet Data Sheet
27
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U– PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
09
01
40
00
04
60
70
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
01
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
80
08
07
0D
0A
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
Internet Data Sheet
28
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U– PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
28
t
t
t
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
30
48
2A
20
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
E8
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
01
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
13
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
02
7F
7F
7F
7F
7F
51
00
00
xx
30
48
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
14
7F
7F
7F
7F
7F
51
00
00
xx
29
30
31
Module Density per Rank
32
tAS,
tAH,
t
t
t
CS [ns]
33
tCH [ns]
34
DS [ns]
35
DH [ns]
36 - 40
41
Not used
t
t
t
t
t
RCmin [ns]
42
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
43
44
45
46
Not used
47
DIMM PCB Height
48 - 61
62
Not used
SPD Revision
63
Checksum of Byte 0-62
64
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
65
66
67
68
69
70
71
72
Internet Data Sheet
29
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–6–C
Product Type
Organization
128MB
256MB
256MB
512MB
512MB
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank (×8) 1 Rank (×8) 2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2700U– PC2700U– PC2700U– PC2700U– PC2700U–
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
25330
Rev. 0.0
HEX
JEDEC SPD Revision
Byte#
Description
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95 - 98
Part Number, Char 1
36
34
44
31
36
33
30
31
48
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
36
34
44
33
32
33
30
30
48
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
37
32
44
33
32
33
30
30
48
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
36
34
44
36
34
33
32
30
48
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
37
32
44
36
34
33
32
30
48
55
36
43
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
99 - 127 Not used
Internet Data Sheet
30
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Package Outlines
5
Package Outlines
133.35
0.15
A B C
128.95
2.7 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 2
Package Outlines - Raw Card C 128 MByte, 1 Rank Module
Internet Data Sheet
31
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
2.7 MAX.
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Package Outline - Raw Card A 256 MByte, 1 Rank Module
L-DIM-184-32
Figure 3
Internet Data Sheet
32
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
2.7 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-30
Figure 4
Package Outline - Raw Card A 256 MByte, 1 Rank ECC Module
Internet Data Sheet
33
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
4 MAX.
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Package Outline - Raw Card B 512 MByte, 2 Ranks Module
L-DIM-184-33
Figure 5
Internet Data Sheet
34
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
4 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-31
Figure 6
Package Outline - Raw Card B 512 MByte, 2 Ranks ECC Module
Internet Data Sheet
35
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
4
5
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Internet Data Sheet
36
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
Internet Data Sheet
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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