HYS72T256020EU-3-B [QIMONDA]
240-Pin unbuffered DDR2 SDRAM Modules; 240针无缓冲DDR2 SDRAM模组
| 型号： | HYS72T256020EU-3-B |
| 厂家： | 
QIMONDA AG |
| 描述： | 240-Pin unbuffered DDR2 SDRAM Modules |
| 文件： | 总60页 (文件大小：3289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2006
HYS[64/72]T256020EU–[25F/2.5]–B
HYS[64/72]T256020EU–[3/3S]–B
HYS[64/72]T256020EU–3.7–B
240-Pin unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
UDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
HYS[64/72]T256020EU–[25F/2.5]–B
,
HYS[64/72]T256020EU–[3/3S]–B
,
HYS[64/72]T256020EU–3.7–B
Revision History: 2006-10, Rev. 1.0
Page
Subjects (major changes since last revision)
Adapted internet edition
Updated Clock Load Tables and Notes of Block Diagrams
DD currents update
All
17–18
36–38
I
Previous Revision: 2006-09, Rev. 0.61
All
23
Qimonda update
Modified AC Timing Parameters
Previous Revision: 2006-08, Rev. 0.6
All
Updated for speed -5
43, 44
Added IDD Current Values for speed -3S and -3.7
Previous Revision: Rev. 0.5
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
10262006-SX8C-DEY8
2
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
•
•
•
240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2
SDRAM memory modules.
256M × 64 and 256M ×72 module organization,and
128M × 8 chip organization
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
2 GB Built with 1Gbit DDR2 SDRAMs in and
P-TFBGA-68-6 chipsize packages
All speed grades faster than DDR400 comply with
DDR400 timing specifications.
Programmable CAS Latencies (3, 4, 5 and 6), Burst
Length (8 & 4) and Burst Type
Average Refresh Period 7.8 µs at a TCASE lower than 85°C,
3.9µs between 85°C and 95°C.
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
•
•
•
•
•
•
Serial Presence Detect with E2PROM
UDIMM and EDIMM Dimensions (nominal):
30 mm high, 133.35 mm wide
•
•
Based on standard reference layouts Raw Card “E” and
“G”
RoHS compliant products1)
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
–25F
–2.5
–3
–3S
–3.7
Unit
PC2–6400
5–5–5
PC2–6400
6–6–6
PC2–5300
4–4–4
PC2–5300
5–5–5
PC2–4200
4–4–4
—
Max. Clock Frequency
@CL6 fCK6 400
@CL5 fCK5 400
400
333
266
200
15
–
–
–
MHz
MHz
MHz
MHz
ns
333
333
200
12
333
266
200
15
266
266
200
15
@CL4 fCK4 266
@CL3 fCK3 200
tRCD 12.5
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
tRP 12.5
15
12
15
15
ns
tRAS 45
45
45
45
45
ns
tRC 57.5
60
57
60
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2006-10
3
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
1.2
Description
The QIMONDA HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
module family are unbuffered DIMM modules “UDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 256M × 64 (2 GB) and as
ECC modules in 256M × 72 (2 GB) organization and density,
intended for mounting into 240-pin connector sockets.
are mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E2PROM device using the
2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and are write protected; the second
128 bytes are available to the customer.
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. Decoupling capacitors
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
PC2–6400
HYS64T256020EU–25F–B
HYS72T256020EU–25F–B
PC2–6400
2 GB 2R×8 PC2–6400U–555–12–E0
2 GB 2R×8 PC2–6400E–555–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
HYS64T256020EU–2.5–B
HYS72T256020EU–2.5–B
PC2–5300
2 GB 2R×8 PC2–6400U–666–12–E0
2 GB 2R×8 PC2–6400E–666–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
HYS64T256020EU–3–B
HYS72T256020EU–3–B
PC2–5300
2 GB 2R×8 PC2–5300U–444–12–E0
2 GB 2R×8 PC2–5300E–444–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
HYS64T256020EU–3S–B
HYS72T256020EU–3S–B
PC2–4200
2 GB 2R×8 PC2–5300U–555–12–E0
2 GB 2R×8 PC2–5300E–555–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
HYS64T256020EU–3.7–B
HYS72T256020EU–3.7–B
2 GB 2R×8 PC2–4200U–444–12–E0
2 GB 2R×8 PC2–4200E–444–12–G0
2 Ranks, Non-ECC
2 Ranks, ECC
1 Gbit (×8)
1 Gbit (×8)
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T256020EU–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–E0”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “B”.
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
2 GByte
2 GByte
128M × 64
128M × 72
2
2
Non-ECC
ECC
16
18
14/3/10
14/3/10
E
G
TABLE 4
Components on Modules
DRAM Organisation Note2)
Product Type1)
DRAM Components1)
DRAM Density
HYS64T256020EU
HYB18T1G800BF
HYB18T1G800BF
1 Gbit
1 Gbit
128M × 8
128M × 8
HYS72T256020EU
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
2
Pin Configuration
This chapter contains the pin configuration.
2.1
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used
in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1
for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
TABLE 5
Pin Configuration of UDIMM
Ball No.
Name Pin
Buffer Function
Type Type
Clock Signals
185
137
220
186
138
221
52
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Signals 2:0, Complement Clock Signals 2:0
I
I
I
I
I
I
Clock Enable Rank 1:0
Note: 2 Ranks module
171
I
NC
Not Connected
Note: 1 Rank module
Control Signals
193
76
S0#
S1#
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
Note: 2 Ranks module
I
NC
Not Connected
Note: 1 Rank module
Row Address Strobe
Column Address Strobe
Write Enable
192
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
74
73
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
—
Not Connected
Less than 1Gb DDR2 SDRAMS
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10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name Pin
Buffer Function
Type Type
188
183
63
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 12:0
A1
A2
182
61
A3
A4
60
A5
180
58
A6
A7
179
177
70
A8
A9
A10
AP
A11
A12
A13
57
176
196
Address Signal 13
Note: 1 Gbit based module and 512M ×4/×8
NC
NC
—
Not Connected
Note: Module based on 1 Gbit ×16
Module based on 512 Mbit ×16 or smaller
174
A14
NC
I
SSTL
—
Address Signal 14
Note: Modules based on 2 Gbit
Not Connected
NC
Note: Modules based on 1 Gbit or smaller
Data Signals
3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
4
9
10
122
123
128
129
Rev. 1.0, 2006-10
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10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name Pin
Buffer Function
Type Type
12
DQ8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
13
DQ9
21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name Pin
Buffer Function
Type Type
98
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input/Output pins
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Check Bit Signals
42
CB0
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
SSTL
—
Check Bit 0
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 1
43
CB1
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 2
48
CB2
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 3
49
CB3
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 4
161
162
CB4
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 5
CB5
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: ECC type module only
Rev. 1.0, 2006-10
9
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name Pin
Buffer Function
Type Type
167
CB6
NC
I/O SSTL
Check Bit 6
Note: ECC type module only
Not Connected
NC
—
Note: ECC type module only
Check Bit 7
168
CB7
NC
I/O
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC module
Data Strobe Bus
7
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 8:0
16
28
37
84
93
105
114
46
6
Complement Data Strobe Bus 8:0
15
27
36
83
92
104
113
45
Data Mask Signals
125
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 8:0
134
146
155
202
211
223
232
164
EEPROM
120
SCL
SDA
I
CMOS Serial Bus Clock
119
I/O
OD
Serial Bus Data
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Ball No.
Name Pin
Buffer Function
Type Type
239
SA0
SA1
SA2
I
I
I
CMOS Serial Address Select Bus 2:0
240
CMOS
CMOS
101
Power Supplies
1
VREF
AI
—
—
—
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
238
VDDSPD PWR
51,56,62,72,75,,
78,170,175,181,,
191,194
VDDQ
VDD
VSS
PWR
PWR
GND
53,59,64,67,69,,
172,178,184,187,
189,197
—
—
Power Supply
Ground Plane
2,5,8,11,14,17,,
20,23,26,29,32,
35,38,41,44,47,,
50,65,66,79,82,
85,88,91,94,97,,
100,103,106,
109,112,115,118,
121,124,127,,
130,133,136,139,
142,145,148,,
151,154,157,160,
163,166,169,
198,201,204,207,
210,213,216,,
219,222,225,228,
231,234,237
Other Pins
195
77
ODT0
ODT1
I
I
SSTL
SSTL
On-Die Termination Control 0
On-Die Termination Control 1
Note: 2 Rank modules
Not Connected
NC
NC
NC
—
—
Note: 1 Rank modules
Not connected
18,19,55,68,102,1 NC
26,135,147,
156,165,173,203,
212, 224,233
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 6
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
O
I/O
AI
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
PWR
GND
NC
Ground
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
Rev. 1.0, 2006-10
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10262006-SX8C-DEY8
9ꢀ
66ꢀ
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L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
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ꢂꢁ
ꢂꢁ
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3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
L
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
FIGURE 1
Pin Configuration UDIMM ×64 (240 Pin)
9
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
FIGURE 2
Pin Configuration UDIMM ×72 (240 Pin)
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Rev. 1.0, 2006-10
10262006-SX8C-DEY8
14
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
–1.0
–0.5
–0.5
–0.5
–55
+2.3
+2.3
+2.3
+2.3
+100
V
1)2)
1)2)
1)
VDDQ
VDDL
V
V
VIN, VOUT
TSTG
V
1)2)
°C
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
1)2)3)4)
TOPER
Operating Temperature
0
95
°C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.0, 2006-10
15
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
3.2
DC Operating Conditions
This chapter contains the DC operating conditions tables.
TABLE 10
Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Max.
Operating temperature (ambient)
DRAM Case Temperature
TOPR
TCASE
TSTG
0
+65
+95
+100
+105
90
°C
°C
°C
kPa
%
1)2)3)4)
5)
0
Storage Temperature
– 50
+69
10
Barometric Pressure (operating & storage)
Operating Humidity (relative)
PBar
HOPR
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.
5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
1)
2)
VDDQ
VREF
1.7
1.8
1.9
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDSPD
VIH(DC)
VIL (DC
IL
1.7
—
—
—
—
3.6
V
DC Input Logic High
V
REF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
)
– 0.30
– 5
REF – 0.125
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
Rev. 1.0, 2006-10
16
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
3.3
Timing Characteristics
This chapter describes the timing characteristics.
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with tRAS = 40ns).
Speed Grade Definition: Table 12 for DDR2–800, Table 13 for DDR2–667 and Table 14 DDR2–533C.
TABLE 12
Speed Grade Definition Speed Bins for DDR2–800
Speed Grade
DDR2–800D
DDR2–800E
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–2.5F
–2.5
5–5–5
6–6–6
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
2.5
8
3.75
3
8
tCK
8
8
tCK
2.5
45
8
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
70000
—
57.5
12.5
12.5
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
TABLE 13
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3
–3S
4–4–4
5–5–5
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
tCK
tCK
5
3
3
8
8
8
5
8
8
8
ns
ns
ns
3.75
3
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Speed Grade
DDR2–667C
–3
DDR2–667D
–3S
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
4–4–4
5–5–5
tCK
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70000
—
45
60
15
15
70000
—
ns
ns
ns
ns
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
TABLE 14
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3.7
4–4–4
tCK
Parameter
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3.75
45
8
tCK
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
60
15
—
15
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
3.3.2
Component AC Timing Parameters
Timing Parameters: Table 15 for DDR2–800, Table 16 for DDR2–667 and Table 17 for DDR2–533C.
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–400
–350
0.48
0.48
2500
50
+400
+350
0.52
0.52
8000
––
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
10)11)
12)13)14)
13)14)15)
tCK.AVG
tCK.AVG
ps
DQ and DM input setup time
DQ and DM input hold time
ps
125
––
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
tCK.AVG
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
—
9)16)
9)16)
9)16)
17)
tAC.MAX
tAC.MAX
tAC.MAX
200
tAC.MIN
2 x tAC.MIN
—
ps
ps
DQS-DQ skew for DQS & associated DQ signals tDQSQ
ps
18)
CK half pulse width
tHP
Min(tCH.ABS
,
__
ps
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
300
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL – 1
– 0.25
nCK
tCK.AVG
21)
DQS latching rising transition to associated clock tDQSS
+ 0.25
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
ps
—
21)
21)
—
tDSH
0.2
—
tWPST
tWPRE
tIS.BASE
tIH.BASE
tRPRE
tRPST
tRRD
0.4
0.6
—
Write preamble
0.35
175
250
0.9
22)23)
23)24)
25)26)
25)27)
28)
Address and control input setup time
Address and control input hold time
Read preamble
—
—
ps
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Read postamble
0.4
Active to active command period for 1KB page
size products
7.5
28)
28)
Active to active command period for 2KB page
size products
tRRD
10
35
—
—
ns
ns
Four Activate Window for 1KB page size products tFAW
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–800
Min.
Unit
Note1)2)3)4)5)6)7)
8)
Max.
28)
Four Activate Window for 2KB page size products tFAW
45
—
—
—
—
—
—
—
—
—
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
nCK
ns
28)
15
29)30)
28)31)
28)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
ns
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
ns
28)
t
RFC +10
ns
200
2
nCK
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
tXARD
2
—
—
nCK
nCK
Exit active power-down mode to read command tXARDS
8 – AL
(slow exit, lower power)
32)
CKE minimum pulse width ( high and low pulse tCKE
3
—
nCK
width)
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
tMRD
tMOD
tOIT
2
0
0
—
12
12
––
nCK
ns
28)
28)
ns
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
ns
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 4.
13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
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Unbuffered DDR2 SDRAM Module
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 4.
16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 5.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 5.
25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
Rev. 1.0, 2006-10
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 16
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–450
–400
0.48
0.48
3000
100
+450
+400
0.52
0.52
8000
––
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
tCK.AVG
tCK.AVG
ps
12)13)14)
13)14)15)
DQ and DM input setup time
DQ and DM input hold time
ps
175
––
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
tCK.AVG
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
—
9)16)
9)16)
9)16)
17)
tAC.MAX
tAC.MAX
tAC.MAX
240
tAC.MIN
2 x tAC.MIN
—
ps
ps
DQS-DQ skew for DQS & associated DQ signals tDQSQ
ps
18)
CK half pulse width
tHP
Min(tCH.ABS
,
__
ps
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
340
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL–1
nCK
tCK.AVG
21)
DQS latching rising transition to associated clock tDQSS
– 0.25
+ 0.25
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
ps
—
21)
21)
—
tDSH
0.2
—
tWPST
tWPRE
tIS.BASE
tIH.BASE
tRPRE
tRPST
tRRD
0.4
0.6
—
Write preamble
0.35
200
275
0.9
22)23)
23)24)
25)26)
25)27)
28)
Address and control input setup time
Address and control input hold time
Read preamble
—
—
ps
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Read postamble
0.4
Active to active command period for 1KB page
size products
7.5
28)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
28)
28)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
37.5
50
2
—
—
—
—
ns
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
nCK
ns
28)
15
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–667
Min.
Unit
Note1)2)3)4)5)6)7)
8)
Max.
29)30)
28)31)
28)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
—
—
—
—
—
—
nCK
ns
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
ns
28)
t
RFC +10
ns
200
2
nCK
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
tXARD
2
—
—
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
(slow exit, lower power)
32)
CKE minimum pulse width ( high and low pulse tCKE
3
—
nCK
width)
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
tMRD
tMOD
tOIT
2
0
0
—
12
12
––
nCK
ns
28)
28)
ns
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
ns
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 4.
13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 4.
16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 5.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 5.
25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
Rev. 1.0, 2006-10
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10262006-SX8C-DEY8
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
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Rev. 1.0, 2006-10
25
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
8)18)
9)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
11)
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended data tDS1(base)
strobe)
–25
0.2
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
—
—
tCK
ns
ns
—
Four Activate Window period
tFAW
37.5
13)
12)
13)
11)
50
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
375
0.6
Address and control input pulse width
(each input)
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
—
ps
ps
ps
tCK
ns
—
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
tQH
t
HP –tQHS
—
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–533
Min.
Unit
Note1)2)3)4)5)
6)7)
Max.
Data hold skew factor
tQHS
tREFI
—
400
7.8
3.9
—
ps
µs
µs
ns
14)15)
16)18)
17)
Average periodic refresh Interval
—
—
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
127.5
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
tRP
15 + 1tCK
0.9
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
7.5
14)18)
16)20)
Active bank A to Active bank B command
period
10
—
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
tWPRE
tWPST
tWR
0.25 x tCK
0.40
15
—
19)
20)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
—
tCK
21)
22)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
22)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
tCK
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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Unbuffered DDR2 SDRAM Module
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
3.3.3
ODT AC Electrical Characteristics
ODT AC Character. & Operating Conditions: Table 18 for DDR2–667 & DDR2–800 and Table 19 for DDR2–533 & DDR2–400
TABLE 18
ODT AC Character. and Operating Conditions for DDR2-667 & DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK +
tAC.MAX + 1 ns
ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × tCK.AVG+ tEPR.2PER(MIN)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG
=
3 ns is assumed, tAOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
LOW and by counting the actual input clock edge.
Rev. 1.0, 2006-10
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 19
ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns
(= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
•
•
•
•
Table 20 “IDD Measurement Conditions” on Page 30
Table 22 “IDD Specification for HYS[64/72]T256020EU–[25F/2.5]-B” on Page 32
Table 23 “IDD Specification for HYS[64/72]T256020EU–[3/3S]-B” on Page 33
Table 24 “IDD Specification for HYS[64/72]T256020EU–3.7-B” on Page 34
TABLE 20
DD Measurement Conditions
I
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
6)
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD4R
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
6)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
IDD4W
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol Note
1)2)3)4)5)
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
2)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 21
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
5) For details and notes see the relevant Qimonda component data sheet
6)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 21
Definitions for IDD
Parameter
LOW
Description
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
Inputs are stable at a HIGH or LOW level
Inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 22
DD Specification for HYS[64/72]T256020EU–[25F/2.5]-B
I
Product Type
Units
Note1)
Organization
2 GB
×64
2 GB
×72
2 GB
×64
2 GB
×72
2 Ranks
–25F
2 Ranks
–25F
2 Ranks
–2.5
2 Ranks
–2.5
2)
IDD0
1096
1176
1120
192
1233
1323
1260
216
1096
1176
1120
192
1230
1320
1260
220
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
1040
1440
768
1170
1620
864
1040
1440
768
1170
1620
860
3)
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
240
270
240
270
1696
1696
1896
208
1908
1908
2133
234
1696
1696
1896
208
1910
1910
2130
230
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
160
180
160
180
IDD7
2256
2538
2256
2540
1) Calculated values from component data. ODT disabled. IDD1,
I
DD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.0, 2006-10
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 23
DD Specification for HYS[64/72]T256020EU–[3/3S]-B
I
Product Type
Units
Note1)
Organization
2 GB
×64
2 GB
×72
2 GB
×64
2 GB
×72
2 Ranks
–3
2 Ranks
–3
2 Ranks
–3
2 Ranks
–3
2)
IDD0
976
1098
1188
1170
216
976
1100
1190
1170
220
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
1056
1040
192
1056
1040
192
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
960
1080
1260
810
960
1080
1260
810
3)
1120
720
1120
720
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
240
270
240
270
1456
1456
1776
208
1638
1638
1998
234
1456
1456
1776
208
1640
1640
2000
230
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
160
180
160
180
IDD7
1936
2178
1936
2180
1) Calculated values from component data. ODT disabled. IDD1,
I
DD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 24
DD Specification for HYS[64/72]T256020EU–3.7-B
I
Product Type HYS64T256020EU–3.7–B
HYS72T256020EU–3.7–B
Units
Note1)
Organization
2 GB
×64
2 GB
×72
2 Ranks
–3.7
2 Ranks
–3.7
2)
IDD0
896
936
880
192
800
960
608
240
1296
1296
1696
208
160
1896
1008
1053
990
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
216
3)
IDD2Q
IDD3N
900
3)
1080
684
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
270
1458
1458
1908
234
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
180
IDD7
2133
1) Calculated values from component data. ODT disabled. IDD1,
I
DD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode
3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.0, 2006-10
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
Table 25 “SPD codes for HYS[64/72]T256020EU–25F–B” on Page 35
Table 26 “SPD codes for HYS[64/72]T256020EU–2.5–B” on Page 39
Table 27 “SPD codes for HYS[64/72]T256020EU–3–B” on Page 43
Table 28 “SPD codes for HYS[64/72]T256020EU–3S–B” on Page 47
Table 29 “SPD codes for HYS[64/72]T256020EU–3.7–B” on Page 51
TABLE 25
SPD codes for HYS[64/72]T256020EU–25F–B
Product Type
Organization
HYS64T256020EU–25F–B HYS72T256020EU–25F–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
08
80
08
08
0E
0A
61
48
00
05
25
40
02
82
08
08
00
0C
08
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–25F–B HYS72T256020EU–25F–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
70
00
02
00
07
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
36
39
7F
80
14
1E
00
57
60
5F
40
70
00
02
00
07
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
36
39
7F
80
14
1E
00
57
60
5F
40
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–25F–B HYS72T256020EU–25F–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
∆T2P (DT2P)
2B
2E
49
21
4E
25
39
00
00
00
00
12
AE
7F
7F
7F
7F
7F
51
00
00
xx
2B
2E
49
21
4E
25
39
00
00
00
00
12
C0
7F
7F
7F
7F
7F
51
00
00
xx
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
54
32
35
36
30
32
30
45
55
37
32
54
32
35
36
30
32
30
45
55
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–25F–B HYS72T256020EU–25F–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 12
32
35
46
42
20
20
20
0x
xx
xx
xx
xx
00
FF
32
35
46
42
20
20
20
0x
xx
xx
xx
xx
00
FF
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 1.0, 2006-10
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HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 26
SPD codes for HYS[64/72]T256020EU–2.5–B
Product Type
Organization
HYS64T256020EU–2.5–B HYS72T256020EU–2.5–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–666
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–666
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
08
70
01
02
00
07
30
45
3D
50
3C
1E
3C
80
08
08
0E
0A
61
48
00
05
25
40
02
82
08
08
00
0C
08
70
01
02
00
07
30
45
3D
50
3C
1E
3C
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
Rev. 1.0, 2006-10
39
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–2.5–B HYS72T256020EU–2.5–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–666
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–666
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
RAS.MIN [ns]
Module Density per Rank
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
t
2D
01
17
25
05
12
3C
1E
1E
00
06
3C
7F
80
14
1E
00
57
60
57
40
2B
2E
49
21
4E
25
36
00
00
00
00
12
2D
01
17
25
05
12
3C
1E
1E
00
06
3C
7F
80
14
1E
00
57
60
57
40
2B
2E
49
21
4E
25
36
00
00
00
00
12
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Rev. 1.0, 2006-10
40
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–2.5–B HYS72T256020EU–2.5–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–666
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–666
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
9B
7F
7F
7F
7F
7F
51
00
00
xx
AD
7F
7F
7F
7F
7F
51
00
00
xx
36
34
54
32
35
36
30
32
30
45
55
32
2E
35
42
20
20
20
3x
xx
37
32
54
32
35
36
30
32
30
45
55
32
2E
35
42
20
20
20
3x
xx
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98 Module Serial Number
xx
xx
Rev. 1.0, 2006-10
41
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–2.5–B HYS72T256020EU–2.5–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–6400U–666
Rev. 1.2
HEX
2 Ranks (×8)
PC2–6400E–666
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
99 - 127 Not used
00
00
FF
128 -
255
Blank for customer use
FF
Rev. 1.0, 2006-10
42
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 27
SPD codes for HYS[64/72]T256020EU–3–B
Product Type
Organization
HYS64T256020EU–3–B
HYS72T256020EU–3–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–5300U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–444
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
08
38
01
02
00
07
30
45
50
60
30
1E
30
80
08
08
0E
0A
61
48
00
05
30
45
02
82
08
08
00
0C
08
38
01
02
00
07
30
45
50
60
30
1E
30
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
Rev. 1.0, 2006-10
43
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3–B
HYS72T256020EU–3–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–444
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
RAS.MIN [ns]
Module Density per Rank
HEX
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
t
2D
01
20
27
10
17
3C
1E
1E
00
06
39
7F
80
18
22
00
56
60
47
37
2B
28
3E
21
42
24
2F
00
00
00
00
12
2D
01
20
27
10
17
3C
1E
1E
00
06
39
7F
80
18
22
00
56
60
47
37
2B
28
3E
21
42
24
2F
00
00
00
00
12
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Rev. 1.0, 2006-10
44
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3–B
HYS72T256020EU–3–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–444
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
5F
7F
7F
7F
7F
7F
51
00
00
xx
71
7F
7F
7F
7F
7F
51
00
00
xx
36
34
54
32
35
36
30
32
30
45
55
33
42
20
20
20
20
20
3x
xx
37
32
54
32
35
36
30
32
30
45
55
33
42
20
20
20
20
20
3x
xx
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98 Module Serial Number
xx
xx
Rev. 1.0, 2006-10
45
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3–B
HYS72T256020EU–3–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–444
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
99 - 127 Not used
00
00
FF
128 -
255
Blank for customer use
FF
Rev. 1.0, 2006-10
46
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 28
SPD codes for HYS[64/72]T256020EU–3S–B
Product Type
Organization
HYS64T256020EU–3S–B
HYS72T256020EU–3S–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–555
Rev. 1.2
2 Ranks (×8)
PC2–5300E–555
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
80
08
08
0E
0A
61
48
00
05
30
45
02
82
08
08
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
Rev. 1.0, 2006-10
47
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3S–B
HYS72T256020EU–3S–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–555
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
RAS.MIN [ns]
Module Density per Rank
HEX
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
t
2D
01
20
27
10
17
3C
1E
1E
00
06
3C
7F
80
18
22
00
56
60
3F
37
2B
28
3E
21
42
24
2C
00
00
00
00
12
2D
01
20
27
10
17
3C
1E
1E
00
06
3C
7F
80
18
22
00
56
60
3F
37
2B
28
3E
21
42
24
2C
00
00
00
00
12
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Rev. 1.0, 2006-10
48
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3S–B
HYS72T256020EU–3S–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–555
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
87
7F
7F
7F
7F
7F
51
00
00
xx
36
34
54
32
35
36
30
32
30
45
55
33
53
42
20
20
20
20
3x
xx
99
7F
7F
7F
7F
7F
51
00
00
xx
37
32
54
32
35
36
30
32
30
45
55
33
53
42
20
20
20
20
3x
xx
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98 Module Serial Number
xx
xx
Rev. 1.0, 2006-10
49
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3S–B
HYS72T256020EU–3S–B
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
PC2–5300U–555
Rev. 1.2
HEX
2 Ranks (×8)
PC2–5300E–555
Rev. 1.2
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
99 - 127 Not used
00
00
FF
128 -
255
Blank for customer use
FF
Rev. 1.0, 2006-10
50
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
TABLE 29
SPD codes for HYS[64/72]T256020EU–3.7–B
Product Type
Organization
HYS64T256020EU–3.7–B HYS72T256020EU–3.7–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–4200U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–4200E–444
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
3D
50
00
82
08
00
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
80
08
08
0E
0A
61
48
00
05
3D
50
02
82
08
08
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3.7–B HYS72T256020EU–3.7–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–4200U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–4200E–444
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
RAS.MIN [ns]
Module Density per Rank
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
t
2D
01
25
37
10
22
3C
1E
1E
00
06
3C
7F
80
1E
28
00
52
60
37
2A
2B
20
35
21
36
22
25
00
00
00
00
12
2D
01
25
37
10
22
3C
1E
1E
00
06
3C
7F
80
1E
28
00
52
60
37
2A
2B
20
35
21
36
22
25
00
00
00
00
12
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Rev. 1.0, 2006-10
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3.7–B HYS72T256020EU–3.7–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–4200U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–4200E–444
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
8C
7F
7F
7F
7F
7F
51
00
00
xx
9E
7F
7F
7F
7F
7F
51
00
00
xx
36
34
54
32
35
36
30
32
30
45
55
33
2E
37
42
20
20
20
3x
xx
37
32
54
32
35
36
30
32
30
45
55
33
2E
37
42
20
20
20
3x
xx
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98 Module Serial Number
xx
xx
Rev. 1.0, 2006-10
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10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Product Type
Organization
HYS64T256020EU–3.7–B HYS72T256020EU–3.7–B
2 GByte
×64
2 GByte
×72
2 Ranks (×8)
PC2–4200U–444
Rev. 1.2
HEX
2 Ranks (×8)
PC2–4200E–444
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
99 - 127 Not used
00
00
FF
128 -
255
Blank for customer use
FF
Rev. 1.0, 2006-10
54
10262006-SX8C-DEY8
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 6
Package Outline Raw Card E LG–DIM–240–9
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2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.0, 2006-10
55
10262006-SX8C-DEY8
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
FIGURE 7
Package Outline Raw Card G LG–DIM–240–7
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Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.0, 2006-10
56
10262006-SX8C-DEY8
Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
6
Product Type Nomenclature
Qimonda´s nomenclature uses simple coding combined with some propriatory coding. Table 30 provides examples for module
and component product type number as well as the field number. The detailed field description together with possible values
and coding explanation is listed for modules in Table 31 and for components in Table 32.
TABLE 30
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64/128
0
2
0
0
K
A
M
C
–5
–5
–A
512/1G 16
TABLE 31
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Module Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
D
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
SO-DIMM
Package, Lead-Free Status
Module Type
M
Micro-DIMM
Registered
Unbuffered
Fully Buffered
R
U
F
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Field
Description
Values
Coding
10
Speed Grade
–2.5F
–2.5
–3
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 32
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Qimonda Component Prefix
Interface Voltage [V]
HYB
18
Constant
SSTL_18
DRAM Technology
T
DDR2
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package, Lead-Free Status
Speed Grade
C
FBGA, lead-containing
FBGA, lead-free
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
F
10
–25F
–2.5
–3
–3S
–3.7
–5
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Internet Data Sheet
HYS[64/72]T256020EU-[25F/2.5/3/3S/3.7]-B
Unbuffered DDR2 SDRAM Module
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Rev. 1.0, 2006-10
59
10262006-SX8C-DEY8
Internet Data Sheet
Edition 2006-10
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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