HYS72T256220HP-3.7-A

更新时间:2024-10-29 05:23:59
品牌:QIMONDA
描述:240-Pin Registered DDR2 SDRAM Modules

HYS72T256220HP-3.7-A 概述

240-Pin Registered DDR2 SDRAM Modules 240引脚注册DDR2 SDRAM模组 DRAM

HYS72T256220HP-3.7-A 规格参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM240,40
针数:240Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.71访问模式:DUAL BANK PAGE BURST
最长访问时间:0.5 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):266 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N240内存密度:19327352832 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
湿度敏感等级:3功能数量:1
端口数量:1端子数量:240
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:65 °C
最低工作温度:组织:256MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM240,40
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES子类别:Other Memory ICs
最大压摆率:3.1 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40Base Number Matches:1

HYS72T256220HP-3.7-A 数据手册

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July 2007  
HYS72T64000HP–[3S/3.7]–A  
HYS72T1280x0HP–[3S/3.7]–A  
HYS72T256220HP–[3S/3.7]–A  
HYS72T256040HP–[3S/3.7]–A  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
RDIMM SDRAM  
RoHS Compliant  
Internet Data Sheet  
Rev. 1.02  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
HYS72T64000HP–[3S/3.7]–A, HYS72T1280x0HP–[3S/3.7]–A, HYS72T256220HP–[3S/3.7]–A, HYS72T256040HP–  
[3S/3.7]–A  
Revision History: 2007-07, Rev. 1.02  
Page  
Subjects (major changes since last revision)  
All  
All  
Adapted internet edition  
Editorial changes  
Previous Revision: 2006-09, Rev. 1.01  
All Qimonda update  
Previous Revision: 2006-02, Rev. 1.0  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc@qimonda.com  
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07  
03292006-08VU-L8WK  
2
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
1
Overview  
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules with parity bit product family and  
describes its main characteristics.  
1.1  
Features  
240-Pin PC2–5300 and PC2–4200 DDR2 SDRAM  
memory modules.  
Auto Refresh (CBR) and Self Refresh  
Programmable self refresh rate via EMRS2 setting  
Programmable partial array refresh via EMRS2 settings  
DCC enabling via EMRS2 setting  
One rank 64M ×72, 128M ×72, and two ranks 128M ×72,  
256M ×72, and four rank 256M ×72 module organization  
and 64M ×8, 128M ×4 chip organization  
Registered DIMM Parity bit for address and control bus  
512 MB, 1 GB, and 2 GB module built with 512 Mbit DDR2  
SDRAMs in P-TFBGA-60 chipsize packages.  
Standard Double-Data-Rate-Two Synchronous DRAMs  
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power  
supply  
All speed grades faster than DDR2–400 comply with  
DDR2–400 timing specifications.  
Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4  
& 8)  
All inputs and outputs SSTL_18 compatible  
Off-Chip Driver Impedance Adjustment (OCD) and On-Die  
Termination (ODT)  
Serial Presence Detect with E2PROM  
RDIMM Dimensions (nominal): 30 mm high, 133.35 mm  
wide  
Based on standard reference card layouts Raw Card “G”,  
“H“, “J“, ”N” and “F“  
RoHS compliant products1)  
TABLE 1  
Performance Table  
Product Type Speed Code  
DRAM Speed Grade  
–3S  
–3.7  
Unit  
DDR2–667D  
PC2–5300  
5-5-5  
DDR2–533C  
PC2–4200  
4-4-4  
Module Speed Grade  
CAS-RCD-RP latencies  
tCK  
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
333  
266  
200  
15  
266  
266  
200  
15  
MHz  
MHz  
MHz  
ns  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
15  
ns  
tRAS  
tRC  
45  
45  
ns  
60  
60  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.02, 2007-07  
3
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
1.2  
Description  
The Qimonda HYS72T[64/128/256]xx0HP–[3S/3.7]–A module  
family are Registered DIMM (with parity) modules with 30 mm  
height based on DDR2 technology.  
capacitive loading to the system bus, but adds one cycle to  
the SDRAM timing. Decoupling capacitors are mounted on  
the PCB board. The DIMMs feature serial presence detect  
based on a serial E2PROM device using the 2-pin I2C  
protocol. The first 128 bytes are programmed with  
configuration data and the second 128 bytes are available to  
the customer.  
DIMMs are available as ECC modules in 64M × 72 (512 MB),  
128M × 72 (1 GB), 256M x72 (2GB) organization and density,  
intended for mounting into 240-Pin connector sockets.  
The memory array is designed with 512-Mbit Double-Data-  
Rate-Two (DDR2) Synchronous DRAMs. All control and  
address signals are re-driven on the DIMM using register  
devices and a PLL for the clock distribution. This reduces  
TABLE 2  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description  
SDRAM  
Technology  
PC2–5300-555  
HYS72T64000HP–3S–A  
HYS72T128000HP–3S–A  
HYS72T128020HP–3S–A  
HYS72T256220HP–3S–A  
HYS72T256040HP–3S–A  
PC2–4200-444  
512 MB 1Rx8 PC2-5300P-555-12-F0  
1 GB 1Rx4 PC2-5300P-555-12-H0  
1 GB 2Rx8 PC2-5300P-555-12-G0  
2 GB 2Rx4 PC2-5300P-555-12-J2  
2 GB 4Rx8 PC2-5300P-555-12-N0  
1 Rank ECC  
1 Rank ECC  
2 Ranks, ECC  
2 Ranks, ECC  
4 Ranks, ECC  
512 Mbit (×8)  
512 Mbit (×4)  
512 Mbit (×8)  
512 Mbit (×4)  
512 Mbit (×8)  
HYS72T64000HP–3.7–A  
HYS72T128000HP–3.7–A  
HYS72T128020HP–3.7–A  
HYS72T256220HP–3.7–A  
HYS72T256040HP–3.7–A  
512 MB 1Rx8 PC2-4200P-444-12-F0  
1 GB 1Rx4 PC2-4200P-444-12-H0  
1 GB 2Rx8 PC2-4200P-444-12-G0  
2 GB 2Rx4 PC2-4200P-444-12-J2  
2 GB 4Rx8 PC2-5300P-555-12-N0  
1 Rank ECC  
1 Rank ECC  
2 Ranks, ECC  
2 Ranks, ECC  
4 Ranks, ECC  
512 Mbit (×8)  
512 Mbit (×4)  
512 Mbit (×8)  
512 Mbit (×4)  
512 Mbit (×8)  
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T64000HP–3.7–A, indicating Rev.  
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data  
sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–R0”, where  
4200P means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address  
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD  
Revision 1.2 and produced on the Raw Card “R”  
TABLE 3  
Address Format Table  
DIMM  
Density  
Module  
Organization  
Memory  
Ranks  
ECC/  
Non-ECC  
# of SDRAMs # of row/bank/column  
bits  
Raw  
Card  
512 MB  
1 GB  
64M ×72  
128M ×72  
128M ×72  
1
1
2
ECC  
ECC  
ECC  
9
14/2/10  
14/2/11  
14/2/10  
F
18  
18  
H
G
1 GB  
Rev. 1.02, 2007-07  
4
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
DIMM  
Density  
Module  
Organization  
Memory  
Ranks  
ECC/  
Non-ECC  
# of SDRAMs # of row/bank/column  
bits  
Raw  
Card  
2 GB  
2 GB  
256M ×72  
256M ×72  
2
4
ECC  
ECC  
36  
36  
14/2/11  
14/2/10  
J
N
TABLE 4  
Components on Modules  
Product Type1)  
DRAM Components1)2)  
DRAM Density  
DRAM Organisation  
HYS72T64000HP  
HYS72T128000HP  
HYS72T128020HP  
HYS72T256220HP  
HYB18T512800AF  
HYB18T512400AF  
HYB18T512800AF  
HYB18T512400AF  
HYB18T512800AF  
512 Mbit  
512 Mbit  
512 Mbit  
512 Mbit  
512 Mbit  
64M × 8  
128M × 4  
64M × 8  
128M × 4  
64M × 8  
HYS72T256040HP  
1) Green Product  
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.  
Rev. 1.02, 2007-07  
5
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
2
Pin Configuration  
This chapter contains the pin configuration and block diagrams.  
2.1  
Pin Configuration  
The pin configuration of the Registered DDR2 SDRAM DIMM  
is listed by function in Table 5 (240 pins). The abbreviations  
used in columns Pin and Buffer Type are explained in Table 6  
and Table 7 respectively. The pin numbering is depicted in  
Figure 1.  
TABLE 5  
Pin Configuration of RDIMM  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
Clock Signals  
185  
186  
CK0  
CK0  
I
I
SSTL  
SSTL  
Clock Signal CK0, Complementary Clock Signal CK0  
The system clock inputs. All address and command lines are sampled  
on the cross point of the rising edge of CK and the falling edge of CK.  
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and  
output timing for read operations is synchronized to the input clock.  
52  
CKE0  
CKE1  
I
I
SSTL  
SSTL  
Clock Enables 1:0  
Activates the DDR2 SDRAM CK signal when HIGH and deactivates  
the CK signal when LOW. By deactivating the clocks, CKE0 initiates  
the Power Down Mode or the Self Refresh Mode.  
171  
Note: 2-Ranks module  
Not Connected  
NC  
NC  
Note: 1-Rank module  
Control Signals  
193  
76  
S0  
S1  
I
I
SSTL  
SSTL  
Chip Select  
Enables the associated DDR2 SDRAM command decoder when LOW  
and disables the command decoder when HIGH. When the command  
decoder is disabled, new commands are ignored but previous  
operations continue.  
Rank 0 is selected by S0  
Rank 1 is selected by S1  
The input signals also disable all outputs (except CKE and ODT) of the  
register(s) on the DIMM when both inputs are high. When S is HIGH,  
all register outputs (except CK, ODT and Chip select) remain in the  
previous state.  
Note: 2-Ranks module  
Not Connected  
NC  
NC  
Note: 1-Rank module  
Rev. 1.02, 2007-07  
6
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
220  
S2  
I
SSTL  
Rank 2 is selected by S2  
NC  
NC  
Not Connected  
Note: 1-Rank, 2-Ranks module  
221  
S3  
I
SSTL  
Rank 3 is selected by S3  
Not Connected  
NC  
NC  
Note: 1-Rank, 2-Ranks module  
192  
74  
RAS  
CAS  
WE  
I
I
I
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
When sampled at the cross point of the rising edge of CK, and falling  
edge of CK, RAS, CAS and WE define the operation to be executed by  
the SDRAM.  
73  
18  
RESET  
I
CMOS  
Register Reset  
The RESET pin is connected to the RST pin on the register and to the  
OE pin on the PLL. When LOW, all register outputs will be driven LOW  
and the PLL clocks to the DRAMs and the register(s) will be set to low-  
level. The PLL will remain synchronized with the input clock.  
Address Signals  
71  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
Selects internal SDRAM memory bank  
190  
54  
Bank Address Bus 2  
Greater than 512Mb DDR2 SDRAMS  
NC  
I
SSTL  
Not Connected  
Less than 1Gb DDR2 SDRAMS  
188  
183  
63  
A0  
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Address Bus 12:0, Address Signal 10/AutoPrecharge  
During a Bank Activate command cycle, defines the row address when  
sampled at the crosspoint of the rising edge of CK and falling edge of  
CK. During a Read or Write command cycle, defines the column  
address when sampled at the cross point of the rising edge of CK and  
falling edge of CK. In addition to the column address, AP is used to  
invoke autoprecharge operation at the end of the burst read or write  
cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the  
bank to be precharged. If AP is LOW, autoprecharge is disabled.  
During a Precharge command cycle, AP is used in conjunction with  
BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks  
will be precharged regardless of the state of BA[1:0] inputs. If AP is  
LOW, then BA[1:0] are used to define which bank to precharge.  
A1  
I
A2  
I
182  
61  
A3  
I
A4  
I
60  
A5  
I
180  
58  
A6  
I
A7  
I
179  
177  
70  
A8  
I
A9  
I
A10  
AP  
A11  
A12  
A13  
NC  
I
I
57  
I
176  
196  
I
I
Address Signal 13  
NC  
Not Connected  
Note: Non CA parity modules based on 256 Mbit component  
Rev. 1.02, 2007-07  
7
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
A14  
NC  
Pin  
Type Type  
Buffer  
Function  
174  
I
SSTL  
Address Signal 14  
Note: CA Parity module  
Not Connected  
NC  
I
Note: Non CA parity module. Less than 1 GBit per DRAM die.  
Address Signal 14  
173  
A15  
NC  
SSTL  
Note: CA Parity module  
NC  
Not Connected  
Note: Non CA parity module. Less than 1 GBit per DRAM die.  
Data Signals  
3
DQ0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
4
DQ1  
9
DQ2  
10  
DQ3  
122  
123  
128  
129  
12  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
13  
DQ9  
21  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
22  
131  
132  
140  
141  
24  
25  
30  
31  
143  
144  
149  
150  
33  
34  
39  
40  
152  
153  
158  
Rev. 1.02, 2007-07  
8
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
159  
80  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
81  
86  
87  
199  
200  
205  
206  
89  
90  
95  
96  
208  
209  
214  
215  
98  
99  
107  
108  
217  
218  
226  
227  
110  
111  
116  
117  
229  
230  
235  
236  
Check Bits  
42  
CB0  
CB1  
CB2  
CB3  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Check Bit Input / Output pins  
43  
Note: NC on Non-ECC module  
48  
49  
Rev. 1.02, 2007-07  
9
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
161  
CB4  
CB5  
CB6  
CB7  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Check Bit Input / Output pins  
162  
Note: NC on Non-ECC module  
167  
168  
Data Strobe Bus  
7
DQS0  
DQS0  
DQS1  
DQS1  
DQS2  
DQS2  
DQS3  
DQS3  
DQS4  
DQS4  
DQS5  
DQS5  
DQS6  
DQS6  
DQS7  
DQS7  
DQS8  
DQS8  
DQS9  
DQS9  
DQS10  
DQS10  
DQS11  
DQS11  
DQS12  
DQS12  
DQS13  
DQS13  
DQS14  
DQS14  
DQS15  
DQS15  
DQS16  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
The data strobes, associated with one data byte, sourced with data  
transfers. In Write mode, the data strobe is sourced by the controller  
and is centered in the data window. In Read mode the data strobe is  
sourced by the DDR2 SDRAM and is sent at the leading edge of the  
data window. DQS signals are complements, and timing is relative to  
the crosspoint of respective DQS and DQS. If the module is to be  
operated in single ended strobe mode, all DQS signals must be tied on  
the system board to VSS through a 20 to 10 kresistor and DDR2  
SDRAM mode registers programmed appropriately.  
6
16  
15  
28  
27  
37  
36  
Note: See block diagram for corresponding DQ signals  
84  
83  
93  
92  
105  
104  
114  
113  
46  
45  
125  
126  
134  
135  
146  
147  
155  
156  
202  
203  
211  
212  
223  
224  
232  
Rev. 1.02, 2007-07  
10  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
233  
DQS16  
DQS17  
DQS17  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
164  
165  
Data Mask  
125  
DM0  
DM1  
DM2  
DM3  
DM4  
DM5  
DM6  
DM7  
DM8  
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Masks 8:0  
The data write masks, associated with one data byte. In Write mode,  
DM operates as a byte mask by allowing input data to be written if it is  
LOW but blocks the write operation if it is HIGH. In Read mode, DM  
lines have no effect.  
134  
146  
155  
202  
Note: ×8 based module  
211  
223  
232  
164  
EEPROM  
120  
SCL  
SDA  
I
CMOS  
OD  
Serial Bus Clock  
This signal is used to clock data into and out of the SPD EEPROM.  
119  
I/O  
Serial Bus Data  
This is a bidirectional pin used to transfer data into or out of the SPD  
EEPROM. A resistor must be connected from SDA to VDDSPD on the  
motherboard to act as a pull-up.  
239  
240  
101  
Parity  
55  
SA0  
SA1  
SA2  
I
I
I
CMOS  
CMOS  
CMOS  
Serial Address Select Bus 2:0  
These signals are tied at the system planar to either VSS or VDDSPD to  
configure the serial SPD EEPROM address range  
ERR_OUT  
PAR_IN  
O
I
CMOS  
CMOS  
Parity bits  
Note: Only for modules with parity bit for address and control bus. Not  
connected on non-parity registered modules.  
68  
Power Supplies  
1
VREF  
AI  
I/O Reference Voltage  
Reference voltage for the SSTL-18 inputs.  
238  
VDDSPD  
PWR  
EEPROM Power Supply  
Serial EEPROM positive power supply, wired to a separated power pin  
at the connector which supports from 1.7 Volt to 3.6 Volt.  
51, 56, 62, 72, 75, VDDQ  
78, 170, 175, 181,  
191, 194  
PWR  
PWR  
I/O Driver Power Supply  
Power and ground for the DDR SDRAM  
53, 59, 64, 67, 69, VDD  
172, 178, 184, 187,  
189, 197  
Power Supply  
Power and ground for the DDR SDRAM  
Rev. 1.02, 2007-07  
11  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
2, 5, 8, 11, 14, 17, VSS  
20, 23, 26, 29, 32,  
35, 38, 41, 44, 47,  
50, 65, 66, 79, 82,  
85, 88, 91, 94, 97,  
100, 103, 106, 109,  
112, 115, 118, 121,  
124, 127, 130, 133,  
136, 139, 142, 145,  
148, 151, 154, 157,  
160, 163, 166, 169,  
198, 201, 204, 207,  
210, 213, 216, 219,  
222, 225, 228, 231,  
234, 237  
GND —  
Ground Plane  
Power and ground for the DDR SDRAM  
Other Pins  
19, 102, 137, 138, NC  
NC  
Not connected  
Pins not connected on Qimonda RDIMM’s  
195  
77  
ODT0  
I
I
SSTL  
SSTL  
On-Die Termination Control 1:0  
Asserts on-die termination for DQ, DM, DQS, and DQS signals if  
enabled via the DDR2 SDRAM mode register.  
ODT1  
Note: 2-Ranks module  
NC  
NC  
Note: 1-Rank modules  
TABLE 6  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
CMOS  
OD  
Serial Stub Terminated Logic (SSTL_18)  
CMOS Levels  
Open Drain. The corresponding pin has 2 operational states, active low and tristate,  
and allows multiple devices to share as a wire-OR.  
Rev. 1.02, 2007-07  
12  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
TABLE 7  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard input-only pin. Digital levels.  
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
O
I/O  
AI  
PWR  
GND  
NU  
NC  
Ground  
Not Usable  
Not Connected  
Rev. 1.02, 2007-07  
13  
03292006-08VU-L8WK  
                                        
                                        
                                         
                                                                                                                   
                                                                                                                   
                                                                                                                    
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
FIGURE 1  
Pin Configuration for RDIMM (240 pins)  
95()  
'4ꢀ  
966  
'46ꢀ  
'4ꢈ  
966  
'4ꢇ  
'46ꢁ  
966  
1&  
'4ꢁꢀ  
966  
'4ꢁꢂ  
'46ꢈ  
966  
'4ꢁꢇ  
'4ꢈꢉ  
966  
'46ꢅ  
'4ꢈꢊ  
966  
&%ꢁ  
'46ꢋ  
966  
&%ꢅ  
9''4  
9''  
1&ꢌ(35B287  
 3LQꢄꢀꢀꢁ  
 3LQꢄꢀꢀꢅ  
 3LQꢄꢀꢀꢆ  
 3LQꢄꢀꢀꢂ  
 3LQꢄꢀꢀꢇ  
 3LQꢄꢀꢁꢁ  
 3LQꢄꢀꢁꢅ  
 3LQꢄꢀꢁꢆ  
 3LQꢄꢀꢁꢂ  
 3LQꢄꢀꢁꢇ  
3LQꢄꢁꢈꢁ  966  
3LQꢄꢁꢈꢈ  '4ꢉ  
966  
'4ꢁ  
'46ꢀ  3LQꢄꢀꢀꢊ  
966  
'4ꢅ  
'4ꢋ  
966  
'46ꢁ  3LQꢄꢀꢁꢊ  
5(6(7  3LQꢄꢀꢁꢋ  
 3LQꢄꢀꢀꢈ  
 3LQꢄꢀꢀꢉ  
3LQꢄꢁꢈꢅ  '4ꢆ  
3LQꢄꢁꢈꢉ  966  
3LQꢄꢁꢈꢆ  '0ꢀꢌ'46ꢇ  
3LQꢄꢁꢈꢊ  1&ꢌ'46ꢇ  
3LQꢄꢁꢈꢂ  966  
 3LQꢄꢀꢀꢋ  
 3LQꢄꢀꢁꢀ  
 3LQꢄꢀꢁꢈ  
 3LQꢄꢀꢁꢉ  
3LQꢄꢁꢈꢋ  '4ꢊ  
3LQꢄꢁꢈꢇ  '4ꢂ  
3LQꢄꢁꢅꢀ  966  
3LQꢄꢁꢅꢁ  '4ꢁꢈ  
3LQꢄꢁꢅꢈ  '4ꢁꢅ  
3LQꢄꢁꢅꢅ  966  
3LQꢄꢁꢅꢉ  '0ꢁꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢆ  1&ꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢊ  966  
3LQꢄꢁꢅꢂ  1&  
3LQꢄꢁꢅꢇ  966  
3LQꢄꢁꢉꢁ  '4ꢁꢆ  
3LQꢄꢁꢉꢅ  '4ꢈꢀ  
3LQꢄꢁꢉꢆ  966  
3ꢄLQꢄꢁꢉꢂ  1&ꢌ'46ꢁꢁ  
3LQꢄꢁꢉꢇ  '4ꢈꢈ  
3LQꢄꢁꢆꢁ  966  
3LQꢄꢁꢆꢅ  '4ꢈꢇ  
3LQꢄꢁꢆꢆ  '0ꢅꢌ'46ꢁꢈ  
3LQꢄꢁꢆꢂ  966  
3LQꢄꢁꢆꢇ  '4ꢅꢁ  
3LQꢄꢁꢊꢁ  &%ꢉ  
3LQꢄꢁꢊꢅ  966  
3LQꢄꢁꢊꢆ  1&ꢌ'46ꢁꢂ  
3LQꢄꢁꢊꢂ  &%ꢊ  
3LQꢄꢁꢊꢇ  966  
3LQꢄꢁꢂꢁ  1&ꢌ&.(ꢁ  
3LQꢄꢁꢂꢅ  1&ꢄꢌꢄ$ꢁꢆ  
3LQꢄꢁꢂꢆ  9''4  
3LQꢄꢁꢂꢂ  $ꢇ  
3LQꢄꢁꢂꢇ  $ꢋ  
3LQꢄꢁꢋꢁ  9''4  
3LQꢄꢁꢋꢅ  $ꢁ  
3LQꢄꢁꢅꢋ  1&  
3LQꢄꢁꢉꢀ  '4ꢁꢉ  
3LQꢄꢁꢉꢈ 966  
966  
 3LQꢄꢀꢈꢀ  
3LQꢄꢀꢈꢁ  
3LQꢄꢀꢈꢅ  
'4ꢁꢁ  
'4ꢁꢊ  
966  
'46ꢈ  
'4ꢁꢋ  
966  
'4ꢈꢆ  
'46ꢅ  
966  
'4ꢈꢂ  
&%ꢀ  
966  
'46ꢋ  
&%ꢈ  
966  
&.(ꢀ  
3LQꢄꢀꢈꢈ  
3LQꢄꢀꢈꢉ  
3LQꢄꢁꢉꢉ '4ꢈꢁ  
 3LQꢄꢀꢈꢆ  
3LQꢄꢀꢈꢂ  
3LQꢄꢁꢉꢊ '0ꢈꢌ'46ꢁꢁ  
3LQꢄꢀꢈꢊ  
3LQꢄꢀꢈꢋ  
3LQꢄꢀꢅꢀ  
3LQꢄꢀꢅꢈ  
3LQꢄꢀꢅꢉ  
3LQꢄꢀꢅꢊ  
3LQꢄꢀꢅꢋ  
3LQꢄꢀꢉꢀ  
3LQꢄꢀꢉꢈ  
3LQꢄꢀꢉꢉ  
3LQꢄꢀꢉꢊ  
3LQꢄꢀꢉꢋ  
3LQꢄꢀꢆꢀ  
3LQꢄꢀꢆꢈ  
3LQꢄꢁꢉꢋ 966  
 3LQꢄꢀꢈꢇ  
 3LQꢄꢀꢅꢁ  
 3LQꢄꢀꢅꢅ  
 3LQꢄꢀꢅꢆ  
 3LQꢄꢀꢅꢂ  
 3LQꢄꢀꢅꢇ  
 3LQꢄꢀꢉꢁ  
 3LQꢄꢀꢉꢅ  
 3LQꢄꢀꢉꢆ  
 3LQꢄꢀꢉꢂ  
 3LQꢄꢀꢉꢇ  
 3LQꢄꢀꢆꢁ  
 3LQꢄꢀꢆꢅ  
 3LQꢄꢀꢆꢆ  
 3LQꢄꢀꢆꢂ  
 3LQꢄꢀꢆꢇ  
 3LQꢄꢀꢊꢁ  
 3LQꢄꢀꢊꢅ  
3LQꢄꢁꢆꢀ '4ꢈꢅ  
3LQꢄꢁꢆꢈ '4ꢈꢋ  
3LQꢄꢁꢆꢉ 966  
3LQꢄꢁꢆꢊ 1&ꢌ'46ꢁꢈ  
3LQꢄꢁꢆꢋ '4ꢅꢀ  
3LQꢄꢁꢊꢀ 966  
3LQꢄꢁꢊꢈ &%ꢆ  
3LQꢄꢁꢊꢉ '0ꢋꢌ'46ꢁꢂ  
3LQꢄꢁꢊꢊ 966  
3LQꢄꢁꢊꢋ &%ꢂ  
3LQꢄꢁꢂꢀ 9''4  
3LQꢄꢁꢂꢈ 9''  
1&ꢌ%$ꢈ 3LQꢄꢀꢆꢉ  
9''4  
$ꢂ  
$ꢆ  
9''4  
9''  
3LQꢄꢁꢂꢉ 1&ꢌ$ꢁꢉ  
3LQꢄꢁꢂꢊ $ꢁꢈ  
3LQꢄꢀꢆꢊ  
3LQꢄꢀꢆꢋ  
3LQꢄꢀꢊꢀ  
3LQꢄꢀꢊꢈ  
3LQꢄꢀꢊꢉ  
$ꢁꢁ  
9''  
$ꢉ  
3LQꢄꢁꢂꢋ 9''  
3LQꢄꢁꢋꢀ $ꢊ  
3LQꢄꢁꢋꢈ $ꢅ  
$ꢈ  
3LQꢄꢁꢋꢉ 9''  
966  
9''  
9''  
%$ꢀ  
 3LQꢄꢀꢊꢆ  
 3LQꢄꢀꢊꢂ  
 3LQꢄꢀꢊꢇ  
 3LQꢄꢀꢂꢁ  
 3LQꢄꢀꢂꢅ  
 3LQꢄꢀꢂꢆ  
 3LQꢄꢀꢂꢂ  
 3LQꢄꢀꢂꢇ  
 3LQꢄꢀꢋꢁ  
 3LQꢄꢀꢋꢅ  
 3LQꢄꢀꢋꢆ  
 3LQꢄꢀꢋꢂ  
 3LQꢄꢀꢋꢇ  
 3LQꢄꢀꢇꢁ  
 3LQꢄꢀꢇꢅ  
 3LQꢄꢀꢇꢆ  
 3LQꢄꢀꢇꢂ  
 3LQꢄꢀꢇꢇ  
 3LQꢄꢁꢀꢁ  
 3LQꢄꢁꢀꢅ  
 3LQꢄꢁꢀꢆ  
 3LQꢄꢁꢀꢂ  
 3LQꢄꢁꢀꢇ  
 3LQꢄꢁꢁꢁ  
 3LQꢄꢁꢁꢅ  
 3LQꢄꢁꢁꢆ  
 3LQꢄꢁꢁꢂ  
 3LQꢄꢁꢁꢇ  
3LQꢄꢁꢋꢆ  &.ꢀ  
3LQꢄꢁꢋꢂ  9''  
3LQꢄꢁꢋꢇ  9''  
3LQꢄꢁꢇꢁ  9''4  
3LQꢄꢁꢇꢅ  6ꢀ  
3LQꢄꢁꢇꢆ  2'7ꢀ  
3LQꢄꢁꢇꢂ  9''  
3LQꢄꢁꢇꢇ  '4ꢅꢊ  
3LQꢄꢈꢀꢁ  966  
3LQꢄꢈꢀꢅ  1&ꢌ'46ꢁꢅ  
3LQꢄꢈꢀꢆ  '4ꢅꢋ  
3LQꢄꢈꢀꢂ  966  
3LQꢄꢈꢀꢇ  '4ꢉꢆ  
3LQꢄꢈꢁꢁ  '0ꢆꢌ'46ꢁꢉ  
3LQꢄꢈꢁꢅ  966  
3LQꢄꢈꢁꢆ  '4ꢉꢂ  
3LQꢄꢈꢁꢂ  '4ꢆꢈ  
3LQꢄꢈꢁꢇ  966  
3LQꢄꢈꢈꢁ  1&ꢌ6ꢅ  
3LQꢄꢈꢈꢅ  '0ꢊꢌ'46ꢁꢆ  
3LQꢄꢈꢈꢆ  966  
3LQꢄꢈꢈꢂ  '4ꢆꢆ  
3LQꢄꢈꢈꢇ  '4ꢊꢀ  
3LQꢄꢈꢅꢁ  966  
3LQꢄꢈꢅꢅ  1&ꢌ'46ꢁꢊ  
3LQꢄꢈꢅꢆ  '4ꢊꢈ  
3LQꢄꢈꢅꢂ 966  
3LQꢄꢈꢅꢇ 6$ꢀ  
0337ꢀꢁꢂꢀ  
3LQꢄꢁꢋꢊ &.ꢀ  
966  
3LQꢄꢀꢊꢊ  
3LQꢄꢀꢊꢋ  
3LQꢄꢀꢂꢀ  
3LQꢄꢀꢂꢈ  
3LQꢄꢀꢂꢉ  
3LQꢄꢀꢂꢊ  
3LQꢄꢀꢂꢋ  
3LQꢄꢀꢋꢀ  
3LQꢄꢀꢋꢈ  
3LQꢄꢀꢋꢉ  
3LQꢄꢀꢋꢊ  
3LQꢄꢀꢋꢋ  
3LQꢄꢀꢇꢀ  
3LQꢄꢀꢇꢈ  
3LQꢄꢀꢇꢉ  
3LQꢄꢀꢇꢊ  
3LQꢄꢀꢇꢋ  
3LQꢄꢁꢀꢀ  
3LQꢄꢁꢀꢈ  
3LQꢄꢁꢀꢉ  
3LQꢄꢁꢀꢊ  
3LQꢄꢁꢀꢋ  
3LQꢄꢁꢁꢀ  
3LQꢄꢁꢁꢈ  
3LQꢄꢁꢁꢉ  
3LQꢄꢁꢁꢊ  
3LQꢄꢁꢁꢋ  
3LQꢄꢁꢈꢀ  
1&ꢌ3$5B,1  
3LQꢄꢁꢋꢋ $ꢀ  
$ꢁꢀꢌ$3  
9''4  
&$6  
1&ꢌ6ꢁ  
9''4  
'4ꢅꢈ  
966  
'46ꢉ  
'4ꢅꢉ  
966  
'4ꢉꢁ  
'46ꢆ  
966  
'4ꢉꢅ  
'4ꢉꢋ  
966  
1&  
'46ꢊ  
966  
'4ꢆꢁ  
'4ꢆꢊ  
966  
'46ꢂ  
'4ꢆꢋ  
966  
3LQꢄꢁꢇꢀ %$ꢁ  
3LQꢄꢁꢇꢈ 5$6  
:(  
3LQꢄꢁꢇꢉ 9''4  
9''4  
1&ꢌ2'7ꢁ  
966  
'4ꢅꢅ  
'46ꢉ  
966  
'4ꢅꢆ  
'4ꢉꢀ  
966  
'46ꢆ  
'4ꢉꢈ  
966  
'4ꢉꢇ  
6$ꢈ  
966  
'46ꢊ  
'4ꢆꢀ  
966  
'4ꢆꢂ  
'46ꢂ  
966  
3LQꢄꢁꢇꢊ 1&ꢌ$ꢁꢅ  
3LQꢄꢁꢇꢋ 966  
3LQꢄꢈꢀꢀ '4ꢅꢂ  
3LQꢄꢈꢀꢈ '0ꢉꢌ'46ꢁꢅ  
3LQꢄꢈꢀꢉ 966  
3LQꢄꢈꢀꢊ '4ꢅꢇ  
3LQꢄꢈꢀꢋ '4ꢉꢉ  
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3LQꢄꢈꢈꢋ 966  
3LQꢄꢈꢅꢀ '4ꢊꢁ  
3LQꢄꢈꢅꢈ '0ꢂꢌ'46ꢁꢊ  
3LQꢄꢈꢅꢉ 966  
3LQꢄꢈꢅꢊ '4ꢊꢅ  
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6'$  
3LQꢄꢈꢅꢋ 9''63'  
3LQꢄꢈꢉꢀ 6$ꢁ  
6&/  
Rev. 1.02, 2007-07  
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HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
3
Electrical Characteristics  
This chapter lists the electrical characteristics.  
3.1  
Absolute Maximum Ratings  
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.  
TABLE 8  
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
Min.  
Unit  
Note  
Max.  
1)  
VDD  
Voltage on VDD pin relative to VSS  
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
–1.0  
–0.5  
–0.5  
–0.5  
–55  
+2.3  
+2.3  
+2.3  
+2.3  
+100  
V
1)2)  
1)2)  
1)  
VDDQ  
VDDL  
V
V
VIN, VOUT  
TSTG  
V
1)2)  
°C  
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.  
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.  
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods may affect reliability.  
TABLE 9  
DRAM Component Operating Temperature Range  
Symbol  
Parameter  
Rating  
Unit  
Note  
Min.  
Max.  
1)2)3)4)  
TOPER  
Operating Temperature  
0
95  
°C  
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.  
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case  
temperature must be maintained between 0 - 95 °C under all other specification parameters.  
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%  
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3.2  
DC Operating Conditions  
This chapter contains the DC operating condition tables.  
TABLE 10  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Max.  
Operating temperature (ambient)  
DRAM Case Temperature  
TOPR  
TCASE  
TSTG  
PBar  
HOPR  
HSTG  
0
+65  
+95  
+100  
+105  
90  
°C  
°C  
°C  
kPa  
%
1)2)3)4)  
5)  
0
Storage Temperature  
– 50  
+69  
10  
5
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
Storage Humidity (without condensation)  
95  
%
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported  
3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.  
5) Up to 3000 m.  
TABLE 11  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Typ.  
Max.  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
1.9  
V
1)  
2)  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
0.49 × VDDQ  
0.5 × VDDQ  
0.51 × VDDQ  
V
VDDSPD  
VIH(DC)  
VIL (DC  
IL  
1.7  
3.6  
V
DC Input Logic High  
V
REF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
)
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ  
3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
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3.3  
Timing Characteristics  
This chapter describes the AC characteristics tables.  
3.3.1  
Speed Grades Definitions  
Speed Grade Definitions for: DDR2–667D (Table 12), DDR2–533C (Table 13)  
TABLE 12  
Speed Grade Definition Speed Bins for DDR2–667D  
Speed Grade  
DDR2–667D  
Unit  
Notes  
QAG Sort Name  
CAS-RCD-RP latencies  
–3S  
5–5–5  
Min.  
tCK  
Parameter  
Symbol  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
3.75  
3
8
tCK  
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
45  
60  
15  
15  
70000  
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal  
OCD drive strength (EMRS(1) A1 = 0)  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT  
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
t
.
TABLE 13  
Speed Grade Definition Speed Bins for DDR2–533C  
Speed Grade  
DDR2–533C  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
–3.7  
4–4–4  
tCK  
Parameter  
Symbol  
Min.  
Max.  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
tCK  
tCK  
tRAS  
tRC  
5
8
ns  
ns  
ns  
ns  
ns  
3.75  
3.75  
45  
8
8
Row Active Time  
Row Cycle Time  
70000  
60  
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Speed Grade  
DDR2–533C  
–3.7  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
Parameter  
4–4–4  
tCK  
Symbol  
Min.  
Max.  
1)2)3)4)  
1)2)3)4)  
RAS-CAS-Delay  
tRCD  
tRP  
15  
15  
ns  
ns  
Row Precharge Time  
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal  
OCD drive strength (EMRS(1) A1 = 0)  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode.  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT  
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
t
.
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3.3.2  
Component AC Timing Parameters  
Speed Grade Definitions for: DDR2–667 (Table 14), DDR2–533C (Table 15)  
TABLE 14  
DRAM Component Timing Parameter by Speed Grade - DDR2–667  
Parameter  
Symbol  
DDR2–667  
Unit  
Notes1)2)3)4)5)6)  
7)8)  
Min.  
Max.  
9)  
DQ output access time from CK / CK  
CAS to CAS command delay  
Average clock high pulse width  
Average clock period  
tAC  
–450  
2
+450  
ps  
tCCD  
nCK  
tCK.AVG  
ps  
10)11)  
12)  
tCH.AVG  
tCK.AVG  
0.48  
3000  
3
0.52  
8000  
CKE minimum pulse width ( high and low pulse tCKE  
nCK  
width)  
10)11)  
13)14)  
Average clock low pulse width  
tCL.AVG  
0.48  
0.52  
tCK.AVG  
nCK  
ns  
Auto-Precharge write recovery + precharge time tDAL  
WR + tnRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK .AVG  
tIH  
+
––  
19)20)15)  
9)  
DQ and DM input hold time  
tDH.BASE  
tDIPW  
tDQSCK  
tDQSH  
175  
––  
ps  
DQ and DM input pulse width for each input  
DQS output access time from CK / CK  
DQS input high pulse width  
0.35  
–400  
0.35  
0.35  
tCK.AVG  
ps  
+400  
tCK.AVG  
tCK.AVG  
ps  
DQS input low pulse width  
tDQSL  
16)  
17)  
DQS-DQ skew for DQS & associated DQ signals tDQSQ  
240  
+ 0.25  
DQS latching rising transition to associated clock tDQSS  
– 0.25  
tCK.AVG  
edges  
18)19)20)  
17)  
DQ and DM input setup time  
DQS falling edge hold time from CK  
DQS falling edge to CK setup time  
CK half pulse width  
tDS.BASE  
100  
0.2  
0.2  
––  
__  
ps  
tDSH  
tDSS  
tHP  
tCK.AVG  
tCK.AVG  
ps  
17)  
21)  
Min(tCH.ABS  
,
tCL.ABS  
)
9)22)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
25)23)  
tIH.BASE  
275  
0.6  
ps  
Control & address input pulse width for each input tIPW  
tCK.AVG  
ps  
24)25)  
9)22)  
9)22)  
35)  
Address and control input setup time  
DQ low impedance time from CK/CK  
DQS/DQS low-impedance time from CK / CK  
MRS command to ODT update delay  
Mode register set command cycle time  
OCD drive mode output delay  
tIS.BASE  
200  
tLZ.DQ  
tLZ.DQS  
tMOD  
tMRD  
tOIT  
2 x tAC.MIN  
tAC.MAX  
tAC.MAX  
12  
ps  
tAC.MIN  
ps  
0
2
0
ns  
nCK  
ns  
35)  
26)  
27)  
12  
DQ/DQS output hold time from DQS  
DQ hold skew factor  
tQH  
t
HP tQHS  
ps  
tQHS  
340  
ps  
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Registered DDR2 SDRAM Modules  
Parameter  
Symbol  
DDR2–667  
Min.  
Unit  
Notes1)2)3)4)5)6)  
7)8)  
Max.  
28)29)  
29)30)  
31)  
Average periodic refresh Interval  
tREFI  
7.8  
3.9  
µs  
µs  
ns  
Auto-Refresh to Active/Auto-Refresh command tRFC  
105  
period  
Precharge-All (4 banks) command period  
Read preamble  
tRP  
tRP  
ns  
32)33)  
32)34)  
35)  
tRPRE  
tRPST  
tRTP  
0.9  
0.4  
7.5  
0.35  
0.4  
15  
1.1  
0.6  
tCK.AVG  
tCK.AVG  
ns  
Read postamble  
Internal Read to Precharge command delay  
Write preamble  
tWPRE  
tWPST  
tWR  
tCK.AVG  
tCK.AVG  
ns  
Write postamble  
0.6  
35)  
Write recovery time  
35)36)  
Internal write to read command delay  
Exit power down to read command  
tWTR  
tXARD  
7.5  
2
ns  
nCK  
nCK  
Exit active power-down mode to read command tXARDS  
7 – AL  
(slow exit, lower power)  
Exit precharge power-down to any valid  
command (other than NOP or Deselect)  
tXP  
2
nCK  
35)  
Exit self-refresh to a non-read command  
Exit self-refresh to read command  
tXSNR  
tXSRD  
t
RFC +10  
ns  
200  
nCK  
nCK  
Write command to DQS associated clock edges WL  
RL–1  
1) For details and notes see the relevant Qimonda component data sheet  
2)  
VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.  
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode.  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
7) The output timing reference voltage level is VTT  
.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock  
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and  
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command  
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)  
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output  
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272  
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and  
tDQSCK.MAX(DERATED) = tDQSCK.MAX tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)  
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)  
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to  
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.  
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and  
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).  
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the  
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during  
the time period of tIS + 2 x tCK + tIH.  
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13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result  
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For  
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.  
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.  
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to  
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing  
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and  
VIH.DC.MIN. See Figure 3.  
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output  
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.  
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.  
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal  
crossing. That is, these parameters should be met whether clock jitter is present or not.  
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level  
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe  
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See  
Figure 3.  
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.  
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal  
((L/U/R)DQS / DQS) crossing.  
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.  
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the  
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the  
minimum of the actual instantaneous clock low time.  
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level  
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .  
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied  
to the device under test. See Figure 4.  
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied  
to the device under test. See Figure 4.  
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to  
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC  
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should  
be met whether clock jitter is present or not.  
26) tQH = tHP tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under  
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}  
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system  
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.  
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is  
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next  
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation  
of the output drivers.  
28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C  
and 95 °C.  
29) 0 °CTCASE 85 °C  
30) 85 °C < TCASE 95 °C  
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.  
32) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving  
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins  
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the  
calculation is consistent.  
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output  
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps  
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX  
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).  
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output  
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps  
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX  
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).  
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock  
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in  
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support  
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at  
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.  
36) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.  
FIGURE 2  
Method for calculating transitions and endpoint  
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W+=ꢄ  
W536 QG  
W/=ꢄ  
W53  
7ꢁꢄ 7ꢈꢄ  
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FIGURE 3  
Differential input waveform timing - tDS and tDS  
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'46  
W'+ꢄ  
W'6ꢄ  
9' '4  
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FIGURE 4  
Differential input waveform timing - tlS and tlH  
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9' '4  
9,+ꢐDF ꢄPLQꢄ  
9,+ꢐGF ꢄPLQꢄ  
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96 6ꢄ  
Rev. 1.02, 2007-07  
22  
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
TABLE 15  
DRAM Component Timing Parameter by Speed Grade - DDR2–533  
Parameter  
Symbol  
DDR2–533  
Unit  
Notes1)2)3)4)5)  
6)7)  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–500  
2
+500  
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
8)18)  
9)  
Auto-Precharge write recovery + precharge  
time  
tDAL  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK + tIH  
225  
––  
––  
ns  
ps  
ps  
10)  
11)  
DQ and DM input hold time (differential data  
strobe)  
tDH(base)  
DQ and DM input hold time (single ended data tDH1(base)  
–25  
strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDIPW  
0.35  
–450  
0.35  
tCK  
ps  
tCK  
ps  
tDQSCK  
+450  
DQS input low (high) pulse width (write cycle) tDQSL,H  
11)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
tDQSQ  
300  
Write command to 1st DQS latching transition tDQSS  
– 0.25  
100  
+ 0.25  
tCK  
11)  
11)  
DQ and DM input setup time (differential data  
strobe)  
t
DS(base)  
ps  
DQ and DM input setup time (single ended data tDS1(base)  
strobe)  
–25  
0.2  
ps  
DQS falling edge hold time from CK (write  
cycle)  
tDSH  
tCK  
tCK  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
12)  
13)  
11)  
Clock half period  
tHP  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
ps  
tCK  
tIH(base)  
tIPW  
375  
0.6  
Address and control input pulse width  
(each input)  
11)  
14)  
14)  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
MRS command to ODT update delay  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMOD  
250  
ps  
ps  
ps  
ns  
tCK  
ns  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
12  
tAC.MIN  
0
2
0
tMRD  
tOIT  
12  
Data output hold time from DQS  
Data hold skew factor  
tQH  
t
HP tQHS  
tQHS  
400  
ps  
Rev. 1.02, 2007-07  
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Parameter  
Symbol  
DDR2–533  
Min.  
Unit  
Notes1)2)3)4)5)  
6)7)  
Max.  
14)15)  
16)18)  
17)  
Average periodic refresh Interval  
Average periodic refresh Interval  
tREFI  
tREFI  
tRFC  
7.8  
3.9  
µs  
µs  
ns  
Auto-Refresh to Active/Auto-Refresh  
command period  
105  
Precharge-All (4 banks) command period  
Read preamble  
tRP  
tRP  
ns  
tCK  
tCK  
ns  
14)  
tRPRE  
tRPST  
tRRD  
0.9  
0.40  
7.5  
1.1  
0.60  
14)  
Read postamble  
14)18)  
Active bank A to Active bank B command  
period  
16)22)  
Active bank A to Active bank B command  
period  
tRRD  
10  
ns  
Internal Read to Precharge command delay  
Write preamble  
tRTP  
7.5  
ns  
tCK  
tCK  
ns  
tWPRE  
tWPST  
tWR  
0.25  
0.40  
15  
19)  
Write postamble  
0.60  
Write recovery time for write without Auto-  
Precharge  
20)  
21)  
Internal Write to Read command delay  
tWTR  
7.5  
2
ns  
Exit power down to any valid command  
(other than NOP or Deselect)  
tXARD  
tCK  
21)  
Exit active power-down mode to Read  
command (slow exit, lower power)  
tXARDS  
tXP  
6 – AL  
2
tCK  
tCK  
Exit precharge power-down to any valid  
command (other than NOP or Deselect)  
Exit Self-Refresh to non-Read command  
Exit Self-Refresh to Read command  
tXSNR  
tXSRD  
WR  
t
RFC +10  
200  
WR/tCK  
ns  
tCK  
tCK  
22)  
Write recovery time for write with Auto-  
Precharge  
t
1) For details and notes see the relevant Qimonda component data sheet  
2) DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.  
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,  
input reference level is the crosspoint when in differential strobe mode.  
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
7) The output timing reference voltage level is VTT  
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to  
the WR parameter stored in the MR.  
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.  
10) For timing definition, refer to the Component data sheet.  
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate  
mis-match between DQS / DQS and associated DQ in any given cycle.  
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can  
be greater than the minimum specification limits for tCL and tCH).  
Rev. 1.02, 2007-07  
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HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving  
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These  
parameters are verified by design and characterization, but not subject to production test.  
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C  
and 95 °C.  
15) 0 °CTCASE 85 °C  
16) 85 °C < TCASE 95 °C  
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.  
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS  
Compliant Products” on Page 4.  
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system  
performance (bus turnaround) degrades accordingly.  
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.  
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-  
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow  
power-down exit timing tXARDS has to be satisfied.  
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded  
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK  
refers to the application clock period. WR refers to the WR parameter stored in the MRS.  
3.3.3  
ODT AC Electrical Characteristics  
This chapter contains the ODT AC characteristic tables.  
TABLE 16  
ODT AC Character. and Operating Conditions for DDR2-667  
Symbol  
Parameter / Condition  
Values  
Unit  
Note  
Min.  
Max.  
1)  
tAOND  
tAON  
ODT turn-on delay  
2
2
nCK  
ns  
1)2)  
1)  
ODT turn-on  
tAC.MIN  
tAC.MAX + 0.7 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns  
2 tCK +  
t
AC.MAX + 1 ns  
ns  
1)  
2.5  
2.5  
nCK  
ns  
1)3)  
1)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
ODT to Power Down Mode Entry Latency  
ODT Power Down Exit Latency  
t
AC.MIN + 2 ns  
2.5 tCK +  
tAC.MAX + 1 ns  
ns  
1)  
3
8
nCK  
nCK  
1)  
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock  
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and  
DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may  
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × tCK.AVG+ tEPR.2PER(MIN)  
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the  
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock  
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.  
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.  
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG  
=
3 ns is assumed, tAOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT  
LOW and by counting the actual input clock edge.  
Rev. 1.02, 2007-07  
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
TABLE 17  
ODT AC Character. and Operating Conditions for DDR2-533  
Symbol  
Parameter / Condition  
Values  
Unit  
Note  
Min.  
Max.  
tAOND  
tAON  
ODT turn-on delay  
2
2
tCK  
ns  
ns  
tCK  
ns  
ns  
tCK  
tCK  
1)  
2)  
ODT turn-on  
tAC.MIN  
tAC.MAX + 1 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns  
2 tCK + tAC.MAX + 1 ns  
2.5  
2.5  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
ODT to Power Down Mode Entry Latency  
ODT Power Down Exit Latency  
t
AC.MIN + 2 ns  
2.5 tCK + tAC.MAX + 1 ns  
3
8
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the  
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns  
(= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.  
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.  
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is  
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.  
Rev. 1.02, 2007-07  
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03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
3.4  
IDD Specifications and Conditions  
This chapter describes the IDD Specifications and Conditions.  
Table 18 “IDD Measurement Conditions” on Page 27  
Table 19 “Definitions for IDD” on Page 28  
Table 20 “IDD Specification for HYS72T[64/128/256]xx0HP-3S-A” on Page 29  
Table 21 “IDD Specification for HYS72T[64/128/256]xx0HP-3.7-A” on Page 30  
TABLE 18  
DD Measurement Conditions  
I
Parameter  
Symbol Note  
1)2)3)4)5)  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between  
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.  
6)  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,  
Databus inputs are SWITCHING.  
Precharge Power-Down Current  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
IDD2P  
IDD2Q  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Standby Current  
IDD3N  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
IDD3P(0)  
IDD3P(1)  
IDD4R  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
6)  
Operating Current - Burst Read  
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX  
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data  
bus inputs are SWITCHING; IOUT = 0mA.  
Operating Current - Burst Write  
IDD4W  
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Burst Refresh Current  
IDD5B  
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Rev. 1.02, 2007-07  
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03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Parameter  
Symbol Note  
1)2)3)4)5)  
Distributed Refresh Current  
IDD5D  
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Self-Refresh Current  
IDD6  
CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data  
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.  
6)  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.  
1)  
2)  
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD see Table 19  
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down  
Mode  
5) For details and notes see the relevant Qimonda component data sheet  
6)  
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output  
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.  
TABLE 19  
Definitions for IDD  
Parameter  
LOW  
Description  
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN  
Inputs are stable at a HIGH or LOW level  
Inputs are VREF = VDDQ /2  
STABLE  
FLOATING  
SWITCHING  
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control  
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ  
signals not including mask or strobes  
Rev. 1.02, 2007-07  
28  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
TABLE 20  
DD Specification for HYS72T[64/128/256]xx0HP-3S-A  
I
Product Type  
Units  
Note1)  
Organization 512 MB  
1 GB  
×72  
1 GB  
×72  
2 GB  
×72  
2 GB  
×72  
×72  
1 Ranks  
–3S  
1 Ranks  
–3S  
2 Ranks  
–3S  
2 Ranks  
–3S  
4 Ranks  
–3S  
2)  
IDD0  
1020  
1150  
430  
1870  
2130  
690  
1280  
1410  
690  
1960  
2220  
780  
1370  
1500  
780  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
3)  
IDD2P  
3)  
IDD2N  
840  
1500  
1320  
940  
1500  
1320  
940  
2400  
2040  
1280  
810  
2400  
2040  
1280  
810  
3)  
IDD2Q  
IDD3P_0 (fast)  
IDD3P_1 (slow)  
IDD3N  
750  
3)  
560  
3)4)  
3)5)  
2)  
440  
700  
700  
840  
1500  
2940  
3120  
3120  
700  
1500  
1810  
1900  
1900  
700  
2400  
3030  
3210  
3210  
810  
2400  
1900  
1990  
1990  
810  
IDD4R  
1560  
1650  
1650  
440  
2)  
IDD4W  
IDD5B  
2)  
3)6)  
3)6)  
2)  
IDD5D  
IDD6  
45  
90  
90  
180  
180  
IDD7  
1710  
3240  
1960  
3330  
2050  
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1,  
I
DD4R, and IDD7, are  
defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Current mode  
3) Both ranks are in the same IDDcurrent mode  
4) Fast: MRS(12)=0  
5) Slow: MRS(12)=1  
6)  
IDD5D and IDD6 values are for 0°C TCase 85°C  
Rev. 1.02, 2007-07  
29  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
TABLE 21  
DD Specification for HYS72T[64/128/256]xx0HP-3.7-A  
I
Product Type  
Units  
Note1)  
Organization 512 MB  
1 GB  
×72  
1 GB  
×72  
2 GB  
×72  
2 GB  
×72  
×72  
1 Ranks  
–3.7  
1 Ranks  
–3.7  
2 Ranks  
–3.7  
2 Ranks  
–3.7  
4 Ranks  
–3.7  
2)  
IDD0  
920  
1010  
370  
690  
600  
470  
380  
690  
1140  
1190  
1500  
380  
36  
1670  
1850  
570  
1120  
1210  
570  
1740  
1920  
640  
1370  
1500  
780  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
3)  
IDD2P  
3)  
IDD2N  
1220  
1040  
790  
1220  
1040  
790  
1940  
1580  
1080  
680  
2400  
2040  
1280  
810  
3)  
IDD2Q  
IDD3P_0 (fast)  
IDD3P_1 (slow)  
IDD3N  
3)  
3)4)  
3)5)  
2)  
590  
590  
1220  
2120  
2210  
2840  
610  
1220  
1350  
1390  
1710  
610  
1940  
2190  
2280  
2910  
720  
2400  
1900  
1990  
1990  
810  
IDD4R  
2)  
IDD4W  
IDD5B  
2)  
3)6)  
3)6)  
2)  
IDD5D  
IDD6  
72  
72  
144  
180  
IDD7  
1590  
3030  
1800  
3100  
2050  
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1,  
I
DD4R, and IDD7, are  
defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Current mode  
3) Both ranks are in the same IDDcurrent mode  
4) Fast: MRS(12)=0  
5) Slow: MRS(12)=1  
6)  
IDD5D and IDD6 values are for 0°C TCase 85°C  
Rev. 1.02, 2007-07  
30  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
4
SPD Codes  
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands  
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.  
List of SPD Code Tables  
Table 22 “HYS72T[64/128/256]xx0HP-3S-A” on Page 31  
Table 23 “HYS72T[64/128/256]xx0HP-3.7-A” on Page 36  
TABLE 22  
HYS72T[64/128/256]xx0HP-3S-A  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
0
Programmed SPD Bytes in EEPROM  
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
80  
08  
08  
0E  
0A  
60  
48  
00  
05  
30  
45  
06  
80  
08  
08  
0E  
0B  
60  
48  
00  
05  
30  
45  
06  
80  
08  
08  
0E  
0A  
61  
48  
00  
05  
30  
45  
06  
80  
08  
08  
0E  
0B  
61  
48  
00  
05  
30  
45  
06  
80  
08  
08  
0E  
0A  
63  
48  
00  
05  
30  
45  
06  
1
2
3
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
4
5
6
7
Not used  
8
Interface Voltage Level  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
10  
11  
AC SDRAM @ CLMAX (Byte 18) [ns]  
Error Correction Support (non-ECC, ECC)  
Rev. 1.02, 2007-07  
31  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
82  
08  
08  
00  
0C  
04  
38  
01  
01  
04  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
80  
20  
27  
10  
17  
82  
04  
04  
00  
0C  
04  
38  
01  
01  
05  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
20  
27  
10  
17  
82  
08  
08  
00  
0C  
04  
38  
01  
01  
05  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
80  
20  
27  
10  
17  
82  
04  
04  
00  
0C  
04  
38  
01  
01  
07  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
20  
27  
10  
17  
82  
08  
08  
00  
0C  
04  
38  
01  
01  
07  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
80  
20  
27  
10  
17  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
Rev. 1.02, 2007-07  
32  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
t
t
t
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
18  
22  
0F  
53  
78  
4B  
2E  
26  
26  
2B  
1B  
4A  
20  
22  
C4  
8C  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
18  
22  
0F  
53  
78  
4B  
2E  
26  
26  
2B  
1B  
4A  
20  
22  
C4  
8C  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
18  
22  
0F  
53  
78  
4B  
2E  
26  
26  
2B  
1B  
4A  
20  
22  
C4  
8C  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
18  
22  
0F  
53  
78  
4B  
2E  
26  
26  
2B  
1B  
4A  
20  
22  
C4  
8C  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
18  
22  
0F  
53  
78  
4B  
2E  
26  
26  
2B  
1B  
4A  
20  
22  
C4  
8C  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
PLL Relock Time  
CASE.MAX Delta / T4R4W Delta  
T
Psi(T-A) DRAM  
T0 (DT0)  
T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM)  
T2P (DT2P)  
T3N (DT3N)  
T3P.fast (DT3P fast)  
T3P.slow (DT3P slow)  
T4R (DT4R) / T4R4W Sign (DT4R4W)  
T5B (DT5B)  
T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
Rev. 1.02, 2007-07  
33  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
TPLL (DTPLL)  
68  
94  
12  
47  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
68  
94  
12  
C2  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
68  
94  
12  
49  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
68  
94  
12  
C5  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
68  
94  
12  
4D  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
Manufacturer’s JEDEC ID Code (1)  
Manufacturer’s JEDEC ID Code (2)  
Manufacturer’s JEDEC ID Code (3)  
Manufacturer’s JEDEC ID Code (4)  
Manufacturer’s JEDEC ID Code (5)  
Manufacturer’s JEDEC ID Code (6)  
Manufacturer’s JEDEC ID Code (7)  
Manufacturer’s JEDEC ID Code (8)  
Module Manufacturer Location  
Product Type, Char 1  
37  
32  
54  
36  
34  
30  
30  
30  
48  
50  
33  
37  
32  
54  
31  
32  
38  
30  
30  
30  
48  
50  
37  
32  
54  
31  
32  
38  
30  
32  
30  
48  
50  
37  
32  
54  
32  
35  
36  
32  
32  
30  
48  
50  
37  
32  
54  
32  
35  
36  
30  
34  
30  
48  
50  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Rev. 1.02, 2007-07  
34  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
PC2–  
5300P–  
555  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
Product Type, Char 12  
53  
41  
20  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
00  
FF  
33  
53  
41  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
00  
FF  
33  
53  
41  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
00  
FF  
33  
53  
41  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
00  
FF  
33  
53  
41  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
00  
FF  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
95 - 98 Module Serial Number  
99 - 127 Not used  
128 -  
255  
Blank for customer use  
Rev. 1.02, 2007-07  
35  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
TABLE 23  
HYS72T[64/128/256]xx0HP-3.7-A  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
0
Programmed SPD Bytes in EEPROM  
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
80  
08  
08  
0E  
0A  
60  
48  
00  
05  
3D  
50  
06  
82  
08  
08  
00  
0C  
04  
38  
01  
01  
80  
08  
08  
0E  
0B  
60  
48  
00  
05  
3D  
50  
06  
82  
04  
04  
00  
0C  
04  
38  
01  
01  
80  
08  
08  
0E  
0A  
61  
48  
00  
05  
3D  
50  
06  
82  
08  
08  
00  
0C  
04  
38  
01  
01  
80  
08  
08  
0E  
0B  
61  
48  
00  
05  
3D  
50  
06  
82  
04  
04  
00  
0C  
04  
38  
01  
01  
80  
08  
08  
0E  
0A  
63  
48  
00  
05  
3D  
50  
06  
82  
08  
08  
00  
0C  
04  
38  
01  
01  
1
2
3
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
4
5
6
7
Not used  
8
Interface Voltage Level  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
AC SDRAM @ CLMAX (Byte 18) [ns]  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
Rev. 1.02, 2007-07  
36  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
DIMM Attributes  
04  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
80  
25  
37  
10  
22  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
1E  
05  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
25  
37  
10  
22  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
1E  
05  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
80  
25  
37  
10  
22  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
1E  
07  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
25  
37  
10  
22  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
1E  
07  
03  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
80  
25  
37  
10  
22  
3C  
1E  
1E  
00  
00  
3C  
69  
80  
1E  
Component Attributes  
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
Rev. 1.02, 2007-07  
37  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
QHS.MAX [ns]  
PLL Relock Time  
CASE.MAX Delta / T4R4W Delta  
HEX  
HEX  
HEX  
HEX  
HEX  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
t
28  
0F  
51  
78  
3F  
22  
1E  
1E  
24  
17  
34  
1E  
20  
C4  
8C  
61  
78  
12  
19  
7F  
7F  
7F  
7F  
7F  
28  
0F  
51  
78  
3F  
22  
1E  
1E  
24  
17  
34  
1E  
20  
C4  
8C  
61  
78  
12  
94  
7F  
7F  
7F  
7F  
7F  
28  
0F  
51  
78  
3F  
22  
1E  
1E  
24  
17  
34  
1E  
20  
C4  
8C  
61  
78  
12  
1B  
7F  
7F  
7F  
7F  
7F  
28  
0F  
51  
78  
3F  
22  
1E  
1E  
24  
17  
34  
1E  
20  
C4  
8C  
61  
78  
12  
97  
7F  
7F  
7F  
7F  
7F  
28  
0F  
51  
78  
3F  
22  
1E  
1E  
24  
17  
34  
1E  
20  
C4  
8C  
61  
78  
12  
1F  
7F  
7F  
7F  
7F  
7F  
T
Psi(T-A) DRAM  
T0 (DT0)  
T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM)  
T2P (DT2P)  
T3N (DT3N)  
T3P.fast (DT3P fast)  
T3P.slow (DT3P slow)  
T4R (DT4R) / T4R4W Sign (DT4R4W)  
T5B (DT5B)  
T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
TPLL (DTPLL)  
TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
Manufacturer’s JEDEC ID Code (1)  
Manufacturer’s JEDEC ID Code (2)  
Manufacturer’s JEDEC ID Code (3)  
Manufacturer’s JEDEC ID Code (4)  
Manufacturer’s JEDEC ID Code (5)  
Rev. 1.02, 2007-07  
38  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
Manufacturer’s JEDEC ID Code (6)  
Manufacturer’s JEDEC ID Code (7)  
Manufacturer’s JEDEC ID Code (8)  
Module Manufacturer Location  
Product Type, Char 1  
51  
00  
00  
xx  
51  
00  
00  
xx  
51  
00  
00  
xx  
51  
00  
00  
xx  
51  
00  
00  
xx  
37  
32  
54  
36  
34  
30  
30  
30  
48  
50  
33  
2E  
37  
41  
20  
20  
20  
20  
2x  
xx  
37  
32  
54  
31  
32  
38  
30  
30  
30  
48  
50  
33  
2E  
37  
41  
20  
20  
20  
2x  
xx  
37  
32  
54  
31  
32  
38  
30  
32  
30  
48  
50  
33  
2E  
37  
41  
20  
20  
20  
2x  
xx  
37  
32  
54  
32  
35  
36  
32  
32  
30  
48  
50  
33  
2E  
37  
41  
20  
20  
20  
2x  
xx  
37  
32  
54  
32  
35  
36  
30  
34  
30  
48  
50  
33  
2E  
37  
41  
20  
20  
20  
2x  
xx  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Rev. 1.02, 2007-07  
39  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
512MB  
1 GByte 1 GByte 2 GByte 2 GByte  
×72  
×72  
×72  
×72  
×72  
1 Rank  
1 Rank  
2 Ranks 2 Ranks 4 Ranks  
(×8)  
(×4)  
(×8)  
(×4)  
(×8)  
Label Code  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
PC2–  
4200P–  
444  
JEDEC SPD Revision  
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2  
Byte#  
Description  
HEX  
HEX  
HEX  
HEX  
HEX  
93  
94  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
xx  
xx  
xx  
00  
FF  
xx  
xx  
xx  
00  
FF  
xx  
xx  
xx  
00  
FF  
xx  
xx  
xx  
00  
FF  
xx  
xx  
xx  
00  
FF  
95 - 98 Module Serial Number  
99 - 127 Not used  
128 -  
255  
Blank for customer use  
Rev. 1.02, 2007-07  
40  
03292006-08VU-L8WK  
                                                                                                                   
                                                                                                                    
                                                                                                                      
                                                                                                                       
                                                               
                                                                
                                                                  
                                                                   
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
5
Package Outlines  
This chapter contains the package outlines of the products.  
FIGURE 5  
Package Outline Raw Card F L-DIM-240-11  
                                                               
                                                                
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Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
Rev. 1.02, 2007-07  
41  
03292006-08VU-L8WK  
                                                                                                                   
                                                                                                                     
                                                                                                                      
                                                               
                                                                
                                                                  
                                                                   
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
FIGURE 6  
Package Outline Raw Card G L-DIM-240-12  
                                                               
                                                                
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Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
Rev. 1.02, 2007-07  
42  
03292006-08VU-L8WK  
                                                                                                                   
                                                                                                                     
                                                                                                                      
                                                               
                                                                
                                                                  
                                                                   
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
FIGURE 7  
Package Outline Raw Card H L-DIM-240-13  
                                                               
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Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
Rev. 1.02, 2007-07  
43  
03292006-08VU-L8WK  
                                                                                                                   
                                                                                                                     
                                                                                                                      
                                                                
                                                                
                                                                  
                                                                   
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Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
FIGURE 8  
Package Outline Raw Card J L-DIM-240-20  
                                                                
                                                                
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Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
Rev. 1.02, 2007-07  
44  
03292006-08VU-L8WK  
                                                                                                                   
                                                                                                                    
                                                                                                                      
                                                               
                                                                
                                                                 
                                                                  
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/'ꢀꢁ  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
FIGURE 9  
Package Outline Raw Card N L-DIM-240-44  
                                                               
                                                                
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Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
Rev. 1.02, 2007-07  
45  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
6
Product Type Nomenclature  
Qimonda’s nomenclature uses simple coding combined with  
some propriatory coding. Table 24 provides examples for  
module and component product type number as well as the  
field number. The detailed field description together with  
possible values and coding explanation is listed for modules  
in Table 25 and for components in Table 26.  
TABLE 24  
Nomenclature Fields and Examples  
Example for  
Field Number  
1
2
3
4
5
6
7
8
9
10  
11  
Micro-DIMM  
DDR2 DRAM  
HYS  
HYB  
64  
18  
T
T
64/128  
0
2
0
0
K
A
M
C
–5  
–5  
–A  
512/1G 16  
TABLE 25  
DDR2 DIMM Nomenclature  
Field  
Description  
Values  
Coding  
1
2
Qimonda Module Prefix  
Module Data Width [bit]  
HYS  
64  
Constant  
Non-ECC  
ECC  
72  
3
4
DRAM Technology  
T
DDR2  
Memory Density per I/O [Mbit];  
Module Density1)  
32  
256 MByte  
512 MByte  
1 GByte  
2 GByte  
4 GByte  
64  
128  
256  
512  
0 .. 9  
0, 2, 4  
0 .. 9  
A .. Z  
D
5
6
7
8
9
Raw Card Generation  
Number of Module Ranks  
Product Variations  
Look up table  
1, 2, 4  
Look up table  
Look up table  
SO-DIMM  
Package, Lead-Free Status  
Module Type  
M
Micro-DIMM  
Registered  
Unbuffered  
Fully Buffered  
R
U
F
Rev. 1.02, 2007-07  
46  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Field  
Description  
Values  
Coding  
10  
Speed Grade  
–2.5F  
–2.5  
–3  
PC2–6400 5–5–5  
PC2–6400 6–6–6  
PC2–5300 4–4–4  
PC2–5300 5–5–5  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
First  
–3S  
–3.7  
–5  
11  
Die Revision  
–A  
–B  
Second  
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall  
module memory density in MBytes as listed in column “Coding”.  
TABLE 26  
DDR2 DRAM Nomenclature  
Field  
Description  
Values  
Coding  
1
2
3
4
Qimonda Component Prefix  
Interface Voltage [V]  
HYB  
18  
Constant  
SSTL_18  
DRAM Technology  
T
DDR2  
Component Density [Mbit]  
256  
512  
1G  
2G  
40  
256 Mbit  
512 Mbit  
1 Gbit  
2 Gbit  
5+6  
Number of I/Os  
×4  
80  
×8  
16  
×16  
7
8
Product Variations  
Die Revision  
0 .. 9  
A
Look up table  
First  
B
Second  
9
Package, Lead-Free Status  
Speed Grade  
C
FBGA, lead-containing  
FBGA, lead-free  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 4-4-4  
DDR2-667 5-5-5  
DDR2-533 4-4-4  
DDR2-400 3-3-3  
F
10  
–25F  
–2.5  
–3  
–3S  
–3.7  
–5  
Rev. 1.02, 2007-07  
47  
03292006-08VU-L8WK  
Internet Data Sheet  
HYS72T[64/128/256]xx0HP–[3S/3.7]–A  
Registered DDR2 SDRAM Modules  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
2.1  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
3.1  
3.2  
3.3  
3.3.1  
3.3.2  
3.3.3  
3.4  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Rev. 1.02, 2007-07  
48  
03292006-08VU-L8WK  
Internet Data Sheet  
Edition 2007-07  
Published by Qimonda AG  
Gustav-Heinemann-Ring 212  
D-81739 München, Germany  
© Qimonda AG 2007.  
All Rights Reserved.  
Legal Disclaimer  
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics  
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any  
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation warranties of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in question please  
contact your nearest Qimonda Office.  
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a  
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human  
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health  
of the user or other persons may be endangered.  
www.qimonda.com  

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