HYS72T64020HR_技术文档

March 2007

HYS72T32000HR–[2.5/3/3S/3.7/5]–A

HYS72T64001HR–[2.5/3/3S/3.7/5]–A

HYS72T64020HR–[2.5/3/3S/3.7/5]–A

240-Pin Registered DDR2 SDRAM Modules

DDR2 SDRAM

RDIMM SDRAM

RoHS Compliant

Internet Data Sheet

Rev. 1.21

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

HYS72T32000HR–[2.5/3/3S/3.7/5]–A, HYS72T64001HR–[2.5/3/3S/3.7/5]–A, HYS72T64020HR–[2.5/3/3S/3.7/5]–A

Revision History: 2007-03, Rev. 1.21

Page

Subjects (major changes since last revision)

All

Qimonda update

Adapted internet edition

Previous Revision: 2005-09, Rev. 1.2

Chapter 4 SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types

Chapter 5 Package Outlines updated

Previous Revision: 2005-06, Rev. 1.1

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev400 / 3.2 QAG / 2006-08-07

09152006-J5FK-C565

2

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

1

Overview

This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules product family and describes its main

characteristics.

1.1

Features

•

240-pin PC2-6400, PC2-5300, PC2-4200 and PC2-3200

DDR2 SDRAM memory modules for PC, Workstation and

Server main memory applications

One rank 32M x 72, 64M x 72 and two ranks 64M × 72

module organization and 32M × 8, 64M × 4 chip

organization

Standard Double-Data-Rate-Two Synchronous DRAMs

(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power

supply

•

Programmable CAS Latencies (3, 4, 5 & 6), Burst Length

(4 & 8) and Burst Type

•

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_18 compatible

Off-Chip Driver Impedance Adjustment (OCD) and On-Die

Termination (ODT)

•

Serial Presence Detect with E²PROM

RDIMM Dimensions (nominal): 30 mm high, 133.35 mm

wide

•

All Speed Grades faster than DDR2–400 comply with

DDR2–400 timing specifications

Built with 256-Mbit DDR2 SDRAMs in P-TFBGA-60

chipsize packages.

•

Based on Standard reference layouts Raw Card “A-F”, “B-

G” & “C-H”

RoHS compliant products¹⁾

TABLE 1

Performance for –2.5 & –3 (S)

Product Type Speed Code

–2.5

–3

–3S

Unit

Speed Grade

PC2–6400 6–6–6

PC2–5300 4–4–4

PC2–5300 5–5–5

—

max. Clock Frequency

@CL6

@CL5

@CL4

@CL3

f_CK6

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

400

333

266

200

15

333

200

12

333

266

200

15

MHz

ns

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

15

12

15

ns

t_RAS

t_RC

45

ns

60

57

60

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.21, 2007-03

3

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 2

Performance for DDR2-533 and DDR2-400

Product Type Speed Code

–3.7

–5

Units

Speed Grade

PC2–4200 4–4–4

PC2–3200 3–3–3

—

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

266

200

15

200

15

MHz

ns

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

15

ns

t_RAS

t_RC

45

40

ns

60

55

ns

Rev. 1.21, 2007-03

4

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

1.2

Description

The QIMONDA HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

module family are Registered DIMM modules “RDIMMs” with

30 mm height based on DDR2 technology. DIMMs are

available as ECC modules in 32M x 72 (256 MByte) and

64M x 72 (512 MByte) organization and density, intended for

mounting into 240-pin connector sockets.

devices and a PLL for the clock distribution. This reduces

capacitive loading to the system bus, but adds one cycle to

the SDRAM timing. Decoupling capacitors are mounted on

the PCB board. The DIMMs feature serial presence detect

based on a serial E²PROM device using the 2-pin I²C

protocol. The first 128 bytes are programmed with

configuration data and are write-protected; the second

128 bytes are available to the customer.

The memory array is designed with 256-Mbit Double-Data-

Rate-Two (DDR2) Synchronous DRAMs. All control and

address signals are re-driven on the DIMM using register

TABLE 3

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM Technology

PC2-6400

HYS72T32000HR–2.5–A

HYS72T64001HR–2.5–A

HYS72T64020HR–2.5–A

PC2-5300

256 MB 1R×8 PC2–6400R–666–12–F0

512 MB 1R×4 PC2–6400R–666–12–H0

512 MB 2R×8 PC2–6400R–666–12–G0

1 Rank, ECC

2 Rank, ECC

256 Mbit (×8)

256 Mbit (×4)

256 Mbit (×8)

HYS72T32000HR–3–A

HYS72T64001HR–3–A

HYS72T64020HR–3–A

HYS72T32000HR–3S–A

HYS72T64001HR–3S–A

HYS72T64020HR–3S–A

PC2–4200

256 MB 1R×8 PC2–5300R–444–12–F0

512 MB 1R×4 PC2–5300R–444–12–H0

512 MB 2R×8 PC2–5300R–444–12–G0

256 MB 1R×8 PC2–5300R–555–12–F0

512 MB 1R×4 PC2–5300R–555–12–H0

512 MB 2R×8 PC2–5300R–555–12–G0

1 Rank, ECC

2 Rank, ECC

1 Rank, ECC

2 Rank, ECC

256 Mbit (×8)

256 Mbit (×4)

256 Mbit (×8)

256 Mbit (×4)

256 Mbit (×8)

HYS72T32000HR–3.7–A

HYS72T64001HR–3.7–A

HYS72T64020HR–3.7–A

PC2-3200

256 MB 1R×8 PC2–4200R–444–11–F0

512 MB 1R×4 PC2–4200R–444–11–H0

512 MB 2R×8 PC2–4200R–444–11–G0

1 rank, ECC

2 rank, ECC

256 Mbit (×8)

256 Mbit (×4)

256 Mbit (×8)

HYS72T32000HR–5–A

HYS72T64001HR–5–A

HYS72T64020HR–5–A

256 MB 1R×8 PC2–3200R–333–11–F0

512 MB 1R×4 PC2–3200R–333–11–H0

512 MB 2R×8 PC2–3200R–333–11–G0

1 Rank, ECC

2 Rank, ECC

256 Mbit (×8)

256 Mbit (×4)

256 Mbit (×8)

1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T32000HR–5–A, indicating Rev. “A” dies are

used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–F0”, where

4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency

= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced

on the Raw Card “F”

Rev. 1.21, 2007-03

5

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 4

Address Format

DIMM

Density

Module

Organization

Memory

Ranks

ECC/

Non-ECC

# of

SDRAMs

# of row/bank/columns bits

Raw Card

256 MB

512 MB

32M ×72

64M ×72

1

2

ECC

9

13/2/10

13/2/11

13/2/10

A-F

C-H

B-G

18

TABLE 5

Components on Modules

DRAM Organization Note²⁾

Product Type¹⁾

DRAM Components¹⁾

DRAM Density

HYS72T32000HR

HYS72T64001HR

HYB18T256800AF

HYB18T256400AF

HYB18T256800AF

256 Mbit

32M × 8

64M × 4

32M × 8

—

HYS72T64020HR

1) Green Product

2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.

Rev. 1.21, 2007-03

6

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

2

Pin Configuration

The pin configuration of the Registered DDR2 SDRAM DIMM

is listed by function in Table 6 (240 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 7

and Table 8 respectively. The pin numbering is depicted in

Figure 1.

TABLE 6

Pin Configuration of RDIMM

Ball No.

Name

Buffer

Function

Type Type

Clock Signals

185

186

52

CK0

CKE0

CKE1

NC

I

SSTL

—

Clock Signal CK0, Complementary Clock Signal CK0

I

Clock Enables 1:0

Note: 2-Ranks module

171

I

NC

Not Connected

Note: 1-Rank module

Control Signals

193

76

S0

S1

NC

I

SSTL

—

Chip Select Rank 1:0

Note: 2-Ranks module

I

NC

Not Connected

Note: 1-Rank module

192

RAS

I

SSTL

CMOS

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

74

CAS

73

WE

18

RESET

Register Reset

Address Signals

71

BA0

BA1

BA2

I

SSTL

Bank Address Bus 1:0

190

54

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

NC

I

SSTL

Not Connected

Less than 1Gb DDR2 SDRAMS

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

188

183

63

A0

I

SSTL

—

Address Bus 12:0, Address Signal 10/AutoPrecharge

A1

I

A2

I

182

61

A3

I

A4

I

60

A5

I

180

58

A6

I

A7

I

179

177

70

A8

I

A9

I

A10

AP

A11

A12

A13

NC

I

57

I

176

196

I

Address Signal 13

NC

Not Connected

Note: Non CA parity modules based on 256 Mbit component

Address Signal 14

174

173

A14

NC

I

SSTL

—

Note: CA Parity module

NC

I

Not Connected

Note: Non CA parity module. Less than 1 GBit per DRAM die.

Address Signal 14

A15

NC

SSTL

—

Note: CA Parity module

NC

Not Connected

Note: Non CA parity module. Less than 1 GBit per DRAM die.

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Data Signals

3

DQ0

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

4

DQ1

9

DQ2

10

DQ3

122

123

128

129

12

DQ4

DQ5

DQ6

DQ7

DQ8

13

DQ9

21

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

81

86

87

199

200

205

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

206

89

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

90

95

96

208

209

214

215

98

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bits

42

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O

SSTL

Check Bits 7:0

Check Bit Input / Output pins

43

Note: NC on Non-ECC module

48

49

161

162

167

168

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Data Strobe Bus

7

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DQS9

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

DQS17

I/O

SSTL

Data Strobes 17:0

6

16

15

28

27

37

36

84

83

93

92

105

104

114

113

46

45

125

126

134

135

146

147

155

156

202

203

211

212

223

224

232

233

164

165

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Data Mask

125

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

SSTL

Data Masks 8:0

Note: ×8 based module

134

146

155

202

211

223

232

164

EEPROM

120

SCL

SDA

SA0

SA1

SA2

I

CMOS

OD

Serial Bus Clock

Serial Bus Data

119

I/O

239

I

CMOS

Serial Address Select Bus 2:0

240

101

Parity

55

ERR_OUT

PAR_IN

O

I

CMOS

Parity bits

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

EEPROM Power Supply

I/O Driver Power Supply

238

V_DDSPD

PWR

51, 56, 62, 72, 75, V_DDQ

78, 170, 175, 181,

191, 194

53, 59, 64, 67, 69, V_DD

172, 178, 184, 187,

189, 197

PWR

GND

—

Power Supply

Ground Plane

2, 5, 8, 11, 14, 17, V_SS

20, 23, 26, 29, 32,

35, 38, 41, 44, 47,

50, 65, 66, 79, 82,

85, 88, 91, 94, 97,

100, 103, 106, 109,

112, 115, 118, 121,

124, 127, 130, 133,

136, 139, 142, 145,

148, 151, 154, 157,

160, 163, 166, 169,

198, 201, 204, 207,

210, 213, 216, 219,

222, 225, 228, 231,

234, 237

Rev. 1.21, 2007-03

12

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Other Pins

19, 55, 68, 102,

137, 138, 173, 220,

221

NC

—

Not connected

195

77

ODT0

ODT1

NC

I

SSTL

—

On-Die Termination Control 1:0

Note: 2-Ranks module

I

NC

Note: 1-Rank modules

TABLE 7

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

CMOS

OD

Serial Stub Terminated Logic (SSTL_18)

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate,

and allows multiple devices to share as a wire-OR.

TABLE 8

Abbreviations for Pin Type

Abbreviation

Description

I

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

O

I/O

AI

PWR

GND

NU

NC

Ground

Not Usable

Not Connected

Rev. 1.21, 2007-03

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09152006-J5FK-C565

ꢃ

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

FIGURE 1

Pin Configuration for RDIMM (240 pins)

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6&/

Rev. 1.21, 2007-03

14

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

3

Electrical Characteristics

This chapter lists the electrical characteristics.

3.1

Absolute Maximum Ratings

Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 9 at any time.

TABLE 9

Absolute Maximum Ratings

Symbol

Parameter

Rating

Min.

Unit

Note

Max.

1)

V_DD

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

–1.0

–0.5

–55

+2.3

+100

V

1)2)

1)

V_DDQ

V_DDL

V

V_IN, V_OUT

T_STG

V

1)2)

°C

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REFmay be equal to or less than 300 mV.

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

TABLE 10

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Unit

Note

Min.

Max.

1)2)3)4)

T_OPER

Operating Temperature

0

95

°C

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case

temperature must be maintained between 0 - 95 °C under all other specification parameters.

3) Above 85 °C the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50 %

Rev. 1.21, 2007-03

15

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

3.2

DC Operating Conditions

This chapter contains the DC operating conditions tables.

TABLE 11

Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Max.

Operating temperature (ambient)

DRAM Case Temperature

T_OPR

T_CASE

T_STG

P_Bar

0

+65

+95

+100

+105

90

°C

kPa

%

—

1)2)3)4)

0

Storage Temperature

– 50

+69

10

—

5)

Barometric Pressure (operating & storage)

Operating Humidity (relative)

H_OPR

—

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported

3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C T_CASEtemperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50 %.

5) Up to 3000 m.

TABLE 12

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Typ.

Max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

1.9

V

—

1)

V_DDQ

V_REF

1.7

1.8

1.9

V

2)

0.49 × V_DDQ

0.5 × V_DDQ

0.51 × V_DDQ

V

V_DDSPD

V_IH(DC)

V_{IL (DC}

I_L

1.7

—

3.6

V

—

DC Input Logic High

V

_REF+ 0.125

V

5

_DDQ+ 0.3

V

DC Input Logic Low

)

– 0.30

– 5

_REF– 0.125

V

—

3)

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

.

Rev. 1.21, 2007-03

16

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

3.3

AC Characteristics

This chapter describes the AC characteristics.

3.3.1

Speed Grades Definitions

This chapter contains the Speed Grades Definitions tables.

TABLE 13

Speed Grade Definition Speed Bins for DDR2–800E

Speed Grade

DDR2–800E

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–2.5

6–6–6

t_CK

Parameter

Symbol

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

@ CL = 6

t_CK

5

8

ns

t_CK

3.75

3

8

t_CK

8

t_CK

2.5

45

60

15

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

Rev. 1.21, 2007-03

17

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 14

Speed Grade Definition Speed Bins for DDR2–667

Speed Grade

DDR2–667C

DDR2–667D

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–3

–3S

4–4–4

5–5–5

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

5

8

5

8

ns

t_CK

3

8

3.75

3

8

t_CK

3

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

45

57

12

70000

—

45

60

15

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

TABLE 15

Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400

Speed Grade

DDR2–533C

DDR2–400B

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–3.7

–5

4–4–4

3–3–3

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

5

8

5

8

ns

t_CK

3.75

45

8

5

8

t_CK

8

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

40

55

15

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

Rev. 1.21, 2007-03

18

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

3.3.2

AC Timing Parameters

This chapter contains the AC Timing Parameters.

TABLE 16

Timing Parameter by Speed Grade - DDR2–800

Parameter

Symbol

DDR2–800

Unit

Note^{1)2)3)4)5)6)7)}

8)

Min.

Max.

9)

DQ output access time from CK / CK

DQS output access time from CK / CK

Average clock high pulse width

Average clock low pulse width

Average clock period

t_AC

–400

–350

0.48

+400

+350

0.52

8000

—

ps

9)

t_DQSCK

t_CH.AVG

t_CL.AVG

t_CK.AVG

t_DS.BASE

t_DH.BASE

ps

10)11)

12)13)14)

12)13)15)

t_CK.AVG

ps

0.48

2500

50

DQ and DM input setup time

DQ and DM input hold time

ps

125

—

ps

Control & address input pulse width for each input t_IPW

0.6

—

t_CK.AVG

ps

—

DQ and DM input pulse width for each input

Data-out high-impedance time from CK / CK

DQS/DQS low-impedance time from CK / CK

DQ low impedance time from CK/CK

t_DIPW

t_HZ

t_LZ.DQS

t_LZ.DQ

0.35

—

9)16)

—

t_AC.MAX

200

9)16)

17)

t_AC.MIN

2 x t_AC.MIN

—

ps

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

ps

18)

CK half pulse width

t_HP

Min (t_CH.ABS

,

__

ps

t_CL.ABS

)

19)

20)

DQ hold skew factor

t_QHS

t_QH

—

300

—

ps

DQ/DQS output hold time from DQS

t

_HP– t_QHS

ps

Write command to DQS associated clock edges WL

RL – 1

– 0.25

nCK

t_CK.AVG

—

21)

DQS latching rising transition to associated clock t_DQSS

+ 0.25

edges

DQS input high pulse width

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Write postamble

t_DQSH

t_DQSL

t_DSS

0.35

0.2

—

t_CK.AVG

ps

—

21)

—

21)

t_DSH

0.2

—

t_WPST

t_WPRE

t_LS.BASE

t_LH.BASE

t_RPRE

t_RPST

t_RAS

0.4

0.6

—

Write preamble

0.35

175

250

0.9

—

22)23)

Address and control input setup time

Address and control input hold time

Read preamble

—

23)24)

25)26)

25)27)

28)

—

ps

1.1

0.6

70000

—

t_CK.AVG

ns

Read postamble

0.4

Active to precharge command

45

28)

Active to active command period for 1KB page

size products

t_RRD

7.5

ns

28)

Active to active command period for 2KB page

size products

t_RRD

10

—

ns

Rev. 1.21, 2007-03

19

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Parameter

Symbol

DDR2–800

Min.

Unit

Note^{1)2)3)4)5)6)7)}

8)

Max.

28)

Four Activate Window for 1KB page size products t_FAW

Four Activate Window for 2KB page size products t_FAW

35

—

ns

45

ns

CAS to CAS command delay

Write recovery time

t_CCD

t_WR

2

nCK

ns

—

28)

15

29)30)

28)31)

28)

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

7.5

nCK

ns

Internal write to read command delay

Internal Read to Precharge command delay

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_WTR

t_RTP

t_XSNR

t_XSRD

t_XP

7.5

ns

28)

t

_RFC+10

ns

200

2

nCK

—

Exit precharge power-down to any valid

command (other than NOP or Deselect)

Exit power down to read command

t_XARD

2

—

nCK

—

Exit active power-down mode to read command t_XARDS

8 – AL

(slow exit, lower power)

32)

CKE minimum pulse width ( high and low pulse t_CKE

width)

3

—

2

nCK

ODT turn-on delay

t_AOND

t_AON

2

nCK

ns

—

9)33)

ODT turn-on

t_AC.MIN

t

_AC.MAX+ 0.7

2 x t_CK.AVG

_AC.MAX+ 1

2.5

_AC.MAX+ 0.6

2.5 x t_CK.AVG

_AC.MAX+ 1

ODT turn-on (Power down mode)

t_AONPD

t

_AC.MIN+ 2

+

ns

—

t

ODT turn-off delay

t_AOFD

t_AOF

2.5

nCK

ns

—

34)35)

ODT turn-off

t_AC.MIN

t

ODT turn-off (Power down mode)

t_AOFPD

t

_AC.MIN+ 2

+

ns

—

t

ODT to power down entry latency

ODT to power down exit latency

Mode register set command cycle time

MRS command to ODT update delay

OCD drive mode output delay

t_ANPD

t_AXPD

t_MRD

t_MOD

t_OIT

3

8

2

0

––

nCK

ns

—

12

––

—

28)

ns

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t

_LS+ t_{CK .AVG}

+

ns

—

t_LH

1) For details and notes see the relevant Qimonda component data sheet

2)

_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V. See notes ^5)6)7)8)

V

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

.

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

8) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVGof the input clock

under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and

DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

.

9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per)of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272

ps and t_{ERR(6- 10PER).MAX}= + 293 ps, then t_{DQSCK.MIN(DERATED)}= t_DQSCK.MIN– t_{ERR(6-10PER).MAX}= – 400 ps – 293 ps = – 693 ps and

t_{DQSCK.MAX(DERATED)}= t_DQSCK.MAX– t_{ERR(6-10PER).MIN}= 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQfor DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}

= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)}= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to

DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.

11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and

the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).

12) Input waveform timing t_DSwith differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AClevel

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AClevel to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAXand V_ih(DC)MIN. See

Figure 2.

13) If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

15) Input waveform timing t_DHwith differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the V_IH.DClevel for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the V_IL.DClevel for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAXand

V_IH.DC.MIN. See Figure 2.

16) t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .

17) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

18) t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not an input specification parameter.

It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The value to be used for t_QHcalculation is determined by the

following equation; t_HP= MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABSis the minimum of the actual instantaneous clock high time; t_CL.ABSis the

minimum of the actual instantaneous clock low time.

19) t_QHSaccounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation

of the output drivers.

20) t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis the specification value under

the max column. {The less half-pulse width distortion present, the larger the t_QHvalue is; and the larger the valid data eye will be.}

Examples: 1) If the system provides t_HPof 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 975 ps minimum. 2) If the system

provides t_HPof 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 1080 ps minimum.

21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

22) Input waveform timing is referenced from the input signal crossing at the V_IH.AClevel for a rising signal and V_IL.ACfor a falling signal applied

to the device under test. See Figure 3.

23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC

,

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should

be met whether clock jitter is present or not.

24) Input waveform timing is referenced from the input signal crossing at the V_IL.DClevel for a rising signal and V_IH.DCfor a falling signal applied

to the device under test. See Figure 3.

25) t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the device output is no longer driving

(t_RPST), or begins driving (t_RPRE). Figure 1 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins

driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the

calculation is consistent.

26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PERof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN= – 72 ps

and t_JIT.PER.MAX= + 93 ps, then t_{RPRE.MIN(DERATED)}= t_RPRE.MIN+ t_JIT.PER.MIN= 0.9 x t_CK.AVG– 72 ps = + 2178 ps and t_{RPRE.MAX(DERATED)}= t_RPRE.MAX

+ t_JIT.PER.MAX= 1.1 x t_CK.AVG+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

Rev. 1.21, 2007-03

21

09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTYof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN= – 72 ps

and t_JIT.DUTY.MAX= + 93 ps, then t_{RPST.MIN(DERATED)}= t_RPST.MIN+ t_JIT.DUTY.MIN= 0.4 x t_CK.AVG– 72 ps = + 928 ps and t_{RPST.MAX(DERATED)}= t_RPST.MAX

+ t_JIT.DUTY.MAX= 0.6 x t_CK.AVG+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

28) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM= RU{t_PARAM/ t_CK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP= RU{t_RP/ t_CK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP= 15 ns, the device will support

t_nRP= RU{t_RP/ t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

29) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result

of the division is not already an integer, round up to the next highest integer. t_CKrefers to the application clock period. Example: For

DDR2–533 at t_CK= 3.75 ns with t_WRprogrammed to 4 clocks. t_DAL= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

30) t_DAL.nCK= WR [nCK] + t_nRP.nCK= WR + RU{t_RP[ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.

31) t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

32) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 x t_CK+ t_IH.

33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measured from t_AOND

34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

Both are measured from t_AOFD

.

35) When the device is operated with input clock jitter, this parameter needs to be derated by {–t_JIT.DUTY.MAX– t_{ERR(6-10PER).MAX}} and {–t_JIT.DUTY.MIN

– t_{ERR(6-10PER).MIN}} of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter

into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272 ps, t_{ERR(6- 10PER).MAX}= + 293 ps, t_JIT.DUTY.MIN= – 106 ps and t_JIT.DUTY.MAX= + 94 ps,

then t_{AOF.MIN(DERATED)}= t_AOF.MIN+ {– t_JIT.DUTY.MAX– t_{ERR(6-10PER).MAX}} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and t_{AOF.MAX(DERATED)}= t_AOF.MAX

+ {– t_JIT.DUTY.MIN– t_{ERR(6-10PER).MIN}} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)

TABLE 17

Timing Parameter by Speed Grade - DDR2–667

Parameter

Symbol

DDR2–667

Unit

Note^{1)2)3)4)5)6)7)}

8)

Min.

Max.

9)

DQ output access time from CK / CK

DQS output access time from CK / CK

Average clock high pulse width

Average clock low pulse width

Average clock period

t_AC

–450

–400

0.48

+450

+400

0.52

8000

—

ps

9)

t_DQSCK

t_CH.AVG

t_CL.AVG

t_CK.AVG

t_DS.BASE

t_DH.BASE

ps

10)11)

t_CK.AVG

ps

0.48

3000

100

—

12)13)14)

DQ and DM input setup time

DQ and DM input hold time

ps

13)14)15)

175

—

ps

Control & address input pulse width for each input t_IPW

0.6

—

t_CK.AVG

ps

—

DQ and DM input pulse width for each input

Data-out high-impedance time from CK / CK

DQS/DQS low-impedance time from CK / CK

DQ low impedance time from CK/CK

t_DIPW

t_HZ

t_LZ.DQS

t_LZ.DQ

0.35

—

9)16)

—

t_AC.MAX

240

9)16)

17)

t_AC.MIN

2 x t_AC.MIN

—

ps

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

ps

18)

CK half pulse width

t_HP

Min (t_CH.ABS

,

__

ps

t_CL.ABS

)

19)

20)

DQ hold skew factor

t_QHS

t_QH

—

340

—

ps

DQ/DQS output hold time from DQS

t

_HP– t_QHS

ps

Write command to DQS associated clock edges WL

RL–1

nCK

—

Rev. 1.21, 2007-03

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09152006-J5FK-C565

Internet Data Sheet

HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A

Registered DDR2 SDRAM Modules

Parameter

Symbol

DDR2–667

Unit

Note^{1)2)3)4)5)6)7)}

8)

Min.

Max.

21)

DQS latching rising transition to associated clock t_DQSS

– 0.25

+ 0.25

t_CK.AVG

edges

DQS input high pulse width

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Write postamble

t_DQSH

t_DQSL

t_DSS

0.35

0.2

—

t_CK.AVG

ps

—

21)

—

21)

t_DSH

0.2

—

t_WPST

t_WPRE

t_LS.BASE

t_LH.BASE

t_RPRE

t_RPST

t_RAS

0.4

0.6

—

Write preamble

0.35

200

275

0.9

—

22)23)

Address and control input setup time

Address and control input hold time

Read preamble

—

23)24)

25)26)

25)27)

28)

—

ps

1.1

0.6

70000

—

t_CK.AVG

ns

Read postamble

0.4

Active to precharge command

45

28)

Active to active command period for 1KB page

size products

t_RRD

7.5

ns

28)

Active to active command period for 2KB page

size products

t_RRD

10

—

ns

28)

Four Activate Window for 1KB page size products t_FAW

Four Activate Window for 2KB page size products t_FAW

37.5

—

ns

50

ns

CAS to CAS command delay

Write recovery time

t_CCD

t_WR

2

nCK

ns

—

28)

15

29)30)

28)31)

28)

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

7.5

nCK

ns

Internal write to read command delay

Internal Read to Precharge command delay

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_WTR

t_RTP

t_XSNR

t_XSRD

t_XP

7.5

ns

28)

t

_RFC+10

ns

200

2

nCK

—

Exit precharge power-down to any valid

command (other than NOP or Deselect)

Exit power down to read command

t_XARD

2

—

nCK

—

Exit active power-down mode to read command t_XARDS

7 – AL

(slow exit, lower power)

32)

CKE minimum pulse width ( high and low pulse t_CKE

width)

3

—

2

nCK

ODT turn-on delay

t_AOND

t_AON

2

nCK

ns

—

9)33)

ODT turn-on

t_AC.MIN

t

_AC.MAX+ 0.7

2 x t_CK.AVG

_AC.MAX+ 1

2.5

_AC.MAX+ 0.6

2.5 x t_CK.AVG

_AC.MAX+ 1

ODT turn-on (Power down mode)

t_AONPD

t

_AC.MIN+ 2

+

ns

—

t

ODT turn-off delay

t_AOFD

t_AOF

2.5

nCK

ns

—

34)35)

ODT turn-off

t_AC.MIN

t

ODT turn-off (Power down mode)

t_AOFPD

t

_AC.MIN+ 2

+

ns

—

t

Rev. 1.21, 2007-03

23