HYS72T64400HFA-2.5-B [QIMONDA]
240-Pin Fully-Buffered DDR2 SDRAM Modules; 240针全缓冲DDR2 SDRAM模组
| 型号： | HYS72T64400HFA-2.5-B |
| 厂家： | 
QIMONDA AG |
| 描述： | 240-Pin Fully-Buffered DDR2 SDRAM Modules |
| 文件： | 总47页 (文件大小：2630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2007
HYS72T64400HFA–[2.5/3S/3.7]–B
HYS72T128420HFA–[2.5/3S/3.7]–B
HYS72T256420HFA–[2.5/3S/3.7]–B
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev.1.01
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.1.01, 2007-06-20
Page 5
Added product type to “Ordering Information for RoHS Compliant Products” on Page 5
Previous Revision: Rev. 1.00, 2006-10-06
All
Converted to QAG template
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
10062006-RQWY-GI6S
2
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
1
Overview
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
1.1
Features
•
•
•
240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM
Module for PC, Workstation and Server main memory
applications.
One rank 64M × 72 and , two rank 128M × 72, 256M × 72
module organization, and 64M × 8, 128M × 4 chip
organization
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
2GB, 1GB, 512MB Modules built with chipsize packages
PG-TFBGA-60
Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
High-Speed Differential Point-to-Point Link Interface at 1.5
V (Jedec standard pending).
Host Interface and AMB component industry standard
compliant.
•
Detects errors on the channel and reports them to the host
memory controller.
Automatic DDR2 DRAM Bus Calibration.
Automatic Channel Calibration.
•
•
•
•
•
•
•
•
•
Full Host Control of the DDR2 DRAMs.
Over-Temperature Detection and Alert.
Hot Add-on and Hot Remove Capability.
MBIST and IBIST Test Functions.
Transparent Mode for DRAM Test Support.
Low profile: 133.35mm x 30.35 mm
240 Pin gold plated card connector with 1.00mm contact
centers (JEDEC standard pending).
Based on JEDEC standard reference card designs (Jedec
standard pending).
•
•
•
•
•
•
•
•
SPD (Serial Presence Detect) with 256 Byte serial
E2PROM.Performance:
RoHS Compliant Products1)
Supports SMBus protocol interface for access to the AMB
configuration registers.
TABLE 1
Performance Table
QAG Speed Code
–2.5
–3S
–3.7
Unit
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
DDR2–800E
PC2–6400E
6–6–6
DDR2–667D
PC2–5300D
5–5–5
DDR2–533C
PC2–4200C
4–4–4
Max. Clock Frequency CL3
fCK3
fCK5
fCK4
fCK6
tRCD
tRP
200
333
266
400
15
200
333
266
–
200
266
266
–
MHz
MHz
MHz
MHz
ns
CL5
CL4
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
15
15
15
15
15
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
3
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
QAG Speed Code
–2.5
–3S
–3.7
Unit
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
DDR2–800E
PC2–6400E
6–6–6
DDR2–667D
PC2–5300D
5–5–5
DDR2–533C
PC2–4200C
4–4–4
Min. Row Active Time
Min. Row Cycle Time
tRAS
tRC
45
60
45
60
45
60
ns
ns
1.2
Description
This document describes the electrical and mechanical
features of a 240-pin, PC2-4200F, PC2-5300F, ECC type,
Fully Buffered Double-Data-Rate Two Synchronous DRAM
Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).
Fully Buffered DIMMs use commodity DRAMs isolated from
the memory channel behind a buffer on the DIMM. They are
intended for use as main memory when installed in systems
such as servers and workstations. PC2-4200F, PC2-5300F,
refers to the DIMM naming convention indicating the DDR2
SDRAMs running at 266, 333, MHz clock speed and offering
4200, 5300, MB/s peak bandwidth. FB-DIMM features a
novel architecture including the Advanced Memory Buffer.
This single chip component, located in the center of each
DIMM, acts as a repeater and buffer for all signals and
commands which are exchanged between the host controller
and the DDR2 SDRAMs including data in- and output. The
AMB communicates with the host controller and / or the
adjacent DIMMs on a system board using an Industry
Standard High-Speed Differential Point-to-Point Link
Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
4
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
PC2-6400
Compliance Code2)
Description
SDRAM Technology
HYS72T64400HFA–2.5–B 512MB 1R×8 PC2–6400F–666–11–A0
HYS72T128020HFA–2.5–B 1GB 2R×8 PC2–6400F–666–11–B0
HYS72T256020HFA–2.5–B 2GB 2R×4 PC2–6400F–666–11–H0
PC2-5300
1 Rank, ECC
2 Ranks, ECC
2 Ranks, ECC
512Mbit (×8)
512Mbit (×8)
512Mbit (×4)
HYS72T128020HFA–3S–B 1GB 2R×8 PC2–5300F–555–11–B0
HYS72T256020HFA–3S–B 2GB 2R×4 PC2–5300F–555–11–H0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
HYS72T64400HFA–3S–B
512MB 1R×8 PC2–5300F–555–11–A0
PC2-4200
HYS72T128020HFA–3.7–B 1GB 2R×8 PC2–4200F–444–11–B0
HYS72T256020HFA–3.7–B 2GB 2R×4 PC2–4200F–444–11–H0
HYS72T64400HFA–3.7–B 512MB 1R×8 PC2–4200F–444–11–A0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400F–666–11–A0" where 6400F
means Fully-Buffered DIMM modules with 6.40 GB/sec Module Bandwidth and "666–11" means Column Address Strobe (CAS) latency
=6, Row Column Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the latest JEDEC SPD Revision 1.1 and produced
on the Raw Card "A".
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
2GB
256M × 72
128M × 72
64M × 72
2
2
1
ECC
ECC
ECC
36
18
9
14/2/11
14/2/10
14/2/10
H, H
B, B
A, A
1GB
512MB
TABLE 4
Components on Modules
DRAM Organisation
Product Type1)2)
DRAM Components1)
DRAM Density
HYS72T256020HFA
HYS72T128020HFA
HYB18T512400BF
HYB18T512800BF
HYB18T512800BF
512Mbit
512Mbit
512Mbit
128M × 4
64M × 8
64M × 8
HYS72T64400HFA
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
5
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns
Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of FB-DIMM
Pin#
Nam Pin
Type
Buffer
Type
Function
e
Clock Signals
228
229
SCK
SCK
I
I
HSDL_15
HSDL_15
System Clock Input, positive line
System Clock Input, negative line
Control Signals
17
RES
I
LV-CMOS
AMB reset signal
ET
Northbound
22
25
28
31
34
37
51
54
57
60
63
66
48
40
23
26
29
32
35
38
52
55
58
61
64
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
O
O
O
O
O
O
O
O
O
O
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Northbound Data, positive lines
PN10 O
PN11 O
PN12 O
PN13 O
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
O
O
O
O
O
O
O
O
O
O
PN10 O
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
6
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Pin#
Nam Pin
Buffer
Type
Function
e
Type
67
PN11 O
PN12 O
PN13 O
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
49
41
142
145
148
151
154
157
171
174
177
180
183
186
168
160
143
146
149
152
155
158
172
175
178
181
184
187
169
161
Southbound
70
SN0
SN1
SN2
SN3
SN4
SN5
SN6
SN7
SN8
SN9
I
I
I
I
I
I
I
I
I
I
Secondary Northbound Data, positive lines
SN10 I
SN11 I
SN12 I
SN13 I
SN0
SN1
SN2
SN3
SN4
SN5
SN6
SN7
SN8
SN9
I
I
I
I
I
I
I
I
I
I
SN10 I
SN11 I
SN12 I
SN13 I
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
I
I
I
I
I
I
I
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Southbound Data, positive lines
73
76
79
82
93
96
99
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
7
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Pin#
Nam Pin
Buffer
Type
Function
e
Type
102
90
PS8
PS9
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
I
71
I
Primary Southbound Data, negative lines
Secondary Southbound data, positive lines
Secondary Southbound data, negative lines
74
I
77
I
80
I
83
I
94
I
97
I
100
103
91
I
I
I
190
193
196
199
202
213
216
219
222
210
191
194
197
200
203
214
217
220
223
211
EEPROM
120
119
239
240
118
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SCL
I
CMOS
OD
Serial Bus Clock
SDA I/O
Serial Bus Data
SA0
SA1
SA2
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
Power
Supplies
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
8
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Pin#
Nam Pin
Buffer
Type
Function
e
Type
238
VDDSP PWR
–
EEPROM Power Supply
D
9,10,12,13,1 VCC
29,130,132,
133
PWR
–
AMB Core Power / Channel Interface Power
15,117,135, VTT
237
PWR
PWR
–
–
Address/Command/Clock Termination Power
Power Supply
1,2,3,5,6,7,1 VDD
08,109,111,
112,113,115
,116,121,12
2,123,125,1
26,
127,231,232
,233,235,23
6
4,8,11,14,18 VSS
,21,24,27,30
,33,36,
GND
–
Ground Plane
39,42,43,46,
47,50,53,56,
59,62,
65,68,69,72,
75,78,81,84,
85,88,
89,92,95,98,
101,104,107
,110,
114,124,128
,131,134,13
8,141,
144,147,150
,153,156,15
9,162,
163,166,167
,170,173,17
6,179,
182,185,188
,189,192,19
5,198,
201,204,205
,208,209,21
2,215,
218,221,224
,227,230,23
4
Other Pins
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
9
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Pin#
Nam Pin
Type
Buffer
Type
Function
e
19,20,44,45, RFU NC
86,87,105,1
06,139,
–
Not connected
Pins not connected on Infineon FB-DIMM’s. Pin positions are reserved for
future architecture flexibility.
140,164,165
,206,207,22
5,226
136
16
VID0
VID1
–
–
–
–
Voltage ID
Note: These Pins must be unconnected for DDR2-based Fully Buffered
DIMMs VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is
VCC value: OPEN = 1.5 V, GND = 1.2 V
137
Test AI
–
VREF
Note: Pin must be unconnected for normal operation
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
HSDL_15
LV-CMOS
CMOS
High-Speed Differential Point-to-Point Link Interface at 1.5 V
Low Voltage CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple
devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
10
66 ꢀ 3ꢁLQꢁꢂꢈꢆ
3ꢁLQꢁꢃꢉꢆ ꢀ 966
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for FB-DIMM (240 pin)
9
9
9
9
9
'' ꢀ 3LQꢁꢂꢂꢃ
'' ꢀ 3LQꢁꢂꢂꢄ
'' ꢀ 3LQꢁꢂꢂꢅ
'' ꢀ 3LQꢁꢂꢂꢆ
&& ꢀ 3LQꢁꢂꢂꢇ
3LQꢁꢃꢈꢃ ꢀ 9''
3LQꢁꢃꢈꢈ ꢀ 9''
3LQꢁꢃꢈꢄ ꢀ 9''
3LQꢁꢃꢈꢉ ꢀ 966
3LQꢁꢃꢈꢅ ꢀ 9''
3LQꢁꢃꢈꢊ ꢀ 9''
3LQꢁꢃꢈꢆ ꢀ 9''
3LQꢁꢃꢈꢋ ꢀ 966
3LQꢁꢃꢈꢇ ꢀ 9&&
3LQꢁꢃꢄꢂ ꢀ 9&&
3LQꢁꢃꢄꢃ ꢀ 966
3LQꢁꢃꢄꢈ ꢀ 9&&
3LQꢁꢃꢄꢄ ꢀ 9&&
3LQꢁꢃꢄꢉ ꢀ 966
3LQꢁꢃꢄꢅ ꢀ 977
9'' ꢀ 3LQꢁꢂꢂꢈ
966 ꢀ 3LQꢁꢂꢂꢉ
9'' ꢀ 3LQꢁꢂꢂꢊ
966 ꢀ 3LQꢁꢂꢂꢋ
9&& ꢀ 3LQꢁꢂꢃꢂ
9&& ꢀ 3LQꢁꢂꢃꢈ
966 ꢀ 3LQꢁꢂꢃꢉ
9,'ꢃ ꢀ 3LQꢁꢂꢃꢊ
966 ꢀ 3LQꢁꢂꢃꢋ
1& ꢀ 3LQꢁꢂꢈꢂ
9
9
9
66 ꢀ 3LQꢁꢂꢃꢃ
&& ꢀ 3LQꢁꢂꢃꢄ
77 ꢀ 3LQꢁꢂꢃꢅ
3LQꢁꢃꢄꢊ ꢀ 9,'ꢂ
3LQꢁꢃꢄꢆ ꢀ 7(67
3LQꢁꢃꢄꢋ ꢀ 966
3LQꢁꢃꢄꢇ ꢀ 1&
5(6(7 ꢀ 3LQꢁꢂꢃꢆ
1& ꢀ 3LQꢁꢂꢃꢇ
966 3LQꢁꢂꢈꢃ
31ꢂ 3LQꢁꢂꢈꢄ
31ꢃ ꢀ 3LQꢁꢂꢈꢅ
9
31ꢈ ꢀ 3LQꢁꢂꢈꢇ
31ꢄ ꢀ 3LQꢁꢂꢄꢃ
9
3LQꢁꢃꢉꢂ ꢀ 1&
ꢀ
ꢀ
3LQꢁꢃꢉꢃ ꢀ 966
3LQꢁꢃꢉꢄ ꢀ 61ꢂ
3LQꢁꢃꢉꢅ ꢀ 61ꢃ
ꢀ
ꢀ
31ꢂ 3LQꢁꢂꢈꢈ
3LQꢁꢃꢉꢈ 61ꢂ
ꢀ
ꢀ
3LQꢁꢃꢉꢉ 966
966 3LQꢁꢂꢈꢉ
)
5
2
1
7
6
,
%
$
&
.
6
,
ꢀ
ꢀ
31ꢃ 3LQꢁꢂꢈꢊ
3LQꢁꢃꢉꢊ 61ꢃ
ꢀ
ꢀ
3LQꢁꢃꢉꢋ 61ꢈ
31ꢈ 3LQꢁꢂꢈꢋ
3LQꢁꢃꢉꢇ ꢀ 61ꢈ
3LQꢁꢃꢅꢃ ꢀ 61ꢄ
3LQꢁꢃꢅꢄ ꢀ 966
3LQꢁꢃꢅꢅ ꢀ 61ꢉ
3LQꢁꢃꢅꢆ ꢀ 61ꢅ
3LQꢁꢃꢅꢇ ꢀ 966
3LQꢁꢃꢊꢃ ꢀ 61ꢃꢄ
3LQꢁꢃꢊꢄ ꢀ 966
3LQꢁꢃꢊꢅ ꢀ 1&
3LQꢁꢃꢊꢆ ꢀ 966
3LQꢁꢃꢊꢇ ꢀ 61ꢃꢈ
3LQꢁꢃꢆꢃ ꢀ 61ꢊ
3LQꢁꢃꢆꢄ ꢀ 966
3LQꢁꢃꢆꢅ ꢀ 61ꢆ
3LQꢁꢃꢆꢆ ꢀ 61ꢋ
3LQꢁꢃꢆꢇ ꢀ 966
3LQꢁꢃꢋꢃ ꢀ 61ꢇ
3LQꢁꢃꢋꢄ ꢀ 61ꢃꢂ
3LQꢁꢃꢋꢅ ꢀ 966
3LQꢁꢃꢋꢆ ꢀ 61ꢃꢃ
ꢀ
ꢀ
966 3LQꢁꢂꢄꢂ
3LQꢁꢃꢅꢂ 966
ꢀ
ꢀ
31ꢄ 3LQꢁꢂꢄꢈ
3LQꢁꢃꢅꢈ 61ꢄ
66 ꢀ 3LQꢁꢂꢄꢄ
ꢀ
ꢀ
31ꢉ 3LQꢁꢂꢄꢉ
3LQꢁꢃꢅꢉ 61ꢉ
31ꢉ ꢀ 3LQꢁꢂꢄꢅ
31ꢅ ꢀ 3LQꢁꢂꢄꢆ
ꢀ
ꢀ
3LQꢁꢃꢅꢊ 966
966 3LQꢁꢂꢄꢊ
'
(
'
(
ꢀ
ꢀ
31ꢅ 3LQꢁꢂꢄꢋ
3LQꢁꢃꢅꢋ 61ꢅ
9
66 ꢀ 3LQꢁꢂꢄꢇ
31ꢃꢄ ꢀ 3LQꢁꢂꢉꢃ
66 ꢀ 3LQꢁꢂꢉꢄ
1& ꢀ 3LQꢁꢂꢉꢅ
66 ꢀ 3LQꢁꢂꢉꢆ
ꢀ
ꢀ
3LQꢁꢃꢊꢂ 61ꢃꢄ
31ꢃꢄ 3LQꢁꢂꢉꢂ
ꢀ
ꢀ
966 3LQꢁꢂꢉꢈ
3LQꢁꢃꢊꢈ 966
9
ꢀ
ꢀ
3LQꢁꢃꢊꢉ 1&
1& 3LQꢁꢂꢉꢉ
ꢀ
ꢀ
966 3LQꢁꢂꢉꢊ
3LQꢁꢃꢊꢊ 966
9
ꢀ
ꢀ
3LQꢁꢃꢊꢋ 61ꢃꢈ
31ꢃꢈ 3LQꢁꢂꢉꢋ
31ꢃꢈ ꢀ 3LQꢁꢂꢉꢇ
31ꢊ ꢀ 3LQꢁꢂꢅꢃ
9
31ꢆ ꢀ 3LQꢁꢂꢅꢅ
31ꢋ ꢀ 3LQꢁꢂꢅꢆ
9
31ꢇ ꢀ 3LQꢁꢂꢊꢃ
31ꢃꢂ ꢀ 3LQꢁꢂꢊꢄ
9
ꢀ
ꢀ
966 3LQꢁꢂꢅꢂ
3LQꢁꢃꢆꢂ 966
ꢀ
ꢀ
3LQꢁꢃꢆꢈ 61ꢊ
31ꢊ 3LQꢁꢂꢅꢈ
66 ꢀ 3LQꢁꢂꢅꢄ
ꢀ
ꢀ
31ꢆ 3LQꢁꢂꢅꢉ
3LQꢁꢃꢆꢉ 61ꢆ
ꢀ
ꢀ
3LQꢁꢃꢆꢊ 966
966 3LQꢁꢂꢅꢊ
ꢀ
ꢀ
31ꢋ 3LQꢁꢂꢅꢋ
3LQꢁꢃꢆꢋ 61ꢋ
66 ꢀ 3LQꢁꢂꢅꢇ
ꢀ
ꢀ
3LQꢁꢃꢋꢂ 61ꢇ
31ꢇ 3LQꢁꢂꢊꢂ
ꢀ
ꢀ
966 3LQꢁꢂꢊꢈ
3LQꢁꢃꢋꢈ 966
ꢀ
ꢀ
3LQꢁꢃꢋꢉ 61ꢃꢂ
31ꢃꢂ 3LQꢁꢂꢊꢉ
66 ꢀ 3LQꢁꢂꢊꢅ
ꢀ
ꢀ
31ꢃꢃ 3LQꢁꢂꢊꢊ
3LQꢁꢃꢋꢊ 61ꢃꢃ
31ꢃꢃ ꢀ 3LQꢁꢂꢊꢆ
ꢀ
ꢀ
3LQꢁꢃꢋꢋ 966
966 3LQꢁꢂꢊꢋ
9
66 ꢀ 3LQꢁꢂꢊꢇ
3LQꢁꢃꢋꢇ ꢀ 966
3LQꢁꢃꢇꢃ ꢀ 66ꢂ
3LQꢁꢃꢇꢄ ꢀ 66ꢃ
3LQꢁꢃꢇꢅ ꢀ 966
3LQꢁꢃꢇꢆ ꢀ 66ꢈ
3LQꢁꢃꢇꢇ ꢀ 66ꢄ
3LQꢁꢈꢂꢃ ꢀ 966
3LQꢁꢈꢂꢄ ꢀ 66ꢉ
3LQꢁꢈꢂꢅ ꢀ 966
3LQꢁꢈꢂꢆ ꢀ 1&
3LQꢁꢈꢂꢇ ꢀ 966
3LQꢁꢈꢃꢃ ꢀ 66ꢇ
3LQꢁꢈꢃꢄ ꢀ 66ꢅ
3LQꢁꢈꢃꢅ ꢀ 966
3LQꢁꢈꢃꢆ ꢀ 66ꢊ
3LQꢁꢈꢃꢇ ꢀ 66ꢆ
3LQꢁꢈꢈꢃ ꢀ 966
3LQꢁꢈꢈꢄ ꢀ 66ꢋ
3LQꢁꢈꢈꢅ ꢀ 1&
3LQꢁꢈꢈꢆ ꢀ 966
3LQꢁꢈꢈꢇ ꢀ 6&.
3LQꢁꢈꢄꢃ ꢀ 9''
3LQꢁꢈꢄꢄ ꢀ 9''
3LQꢁꢈꢄꢅ ꢀ 9''
3LQꢁꢈꢄꢆ 977
3LQꢁꢈꢄꢇ 6$ꢂ
ꢀ
ꢀ
3LQꢁꢃꢇꢂ 66ꢂ
36ꢂ 3LQꢁꢂꢆꢂ
36ꢂ ꢀ 3LQꢁꢂꢆꢃ
36ꢃ ꢀ 3LQꢁꢂꢆꢄ
ꢀ
ꢀ
966 3LQꢁꢂꢆꢈ
3LQꢁꢃꢇꢈ 966
ꢀ
ꢀ
3LQꢁꢃꢇꢉ 66ꢃ
36ꢃ 3LQꢁꢂꢆꢉ
9
66 ꢀ 3LQꢁꢂꢆꢅ
ꢀ
ꢀ
36ꢈ 3LQꢁꢂꢆꢊ
3LQꢁꢃꢇꢊ 66ꢈ
36ꢈ ꢀ 3LQꢁꢂꢆꢆ
36ꢄ ꢀ 3LQꢁꢂꢆꢇ
ꢀ
ꢀ
3LQꢁꢃꢇꢋ 966
966 3LQꢁꢂꢆꢋ
ꢀ
ꢀ
36ꢄ 3LQꢁꢂꢋꢂ
3LQꢁꢈꢂꢂ 66ꢄ
9
66 ꢀ 3LQꢁꢂꢋꢃ
36ꢉ ꢀ 3LQꢁꢂꢋꢄ
66 ꢀ 3LQꢁꢂꢋꢅ
1& ꢀ 3LQꢁꢂꢋꢆ
66 ꢀ 3LQꢁꢂꢋꢇ
ꢀ
ꢀ
3LQꢁꢈꢂꢈ 66ꢉ
36ꢉ 3LQꢁꢂꢋꢈ
ꢀ
ꢀ
966 3LQꢁꢂꢋꢉ
3LQꢁꢈꢂꢉ 966
9
ꢀ
ꢀ
3LQꢁꢈꢂꢊ 1&
1& 3LQꢁꢂꢋꢊ
ꢀ
ꢀ
966 3LQꢁꢂꢋꢋ
3LQꢁꢈꢂꢋ 966
9
ꢀ
ꢀ
3LQꢁꢈꢃꢂ 66ꢇ
36ꢇ 3LQꢁꢂꢇꢂ
36ꢇ ꢀ 3LQꢁꢂꢇꢃ
36ꢅ ꢀ 3LQꢁꢂꢇꢄ
ꢀ
ꢀ
966 3LQꢁꢂꢇꢈ
3LQꢁꢈꢃꢈ 966
ꢀ
ꢀ
3LQꢁꢈꢃꢉ 66ꢅ
36ꢅ 3LQꢁꢂꢇꢉ
9
66 ꢀ 3LQꢁꢂꢇꢅ
ꢀ
ꢀ
36ꢊ 3LQꢁꢂꢇꢊ
3LQꢁꢈꢃꢊ 66ꢊ
36ꢊ ꢀ 3LQꢁꢂꢇꢆ
36ꢆ ꢀ 3LQꢁꢂꢇꢇ
ꢀ
ꢀ
3LQꢁꢈꢃꢋ 966
966 3LQꢁꢂꢇꢋ
ꢀ
ꢀ
36ꢆ 3LQꢁꢃꢂꢂ
3LQꢁꢈꢈꢂ 66ꢆ
9
66 ꢀ 3LQꢁꢃꢂꢃ
ꢀ
ꢀ
3LQꢁꢈꢈꢈ 66ꢋ
36ꢋ 3LQꢁꢃꢂꢈ
36ꢋ ꢀ 3LQꢁꢃꢂꢄ
1& ꢀ 3LQꢁꢃꢂꢅ
ꢀ
ꢀ
966 3LQꢁꢃꢂꢉ
3LQꢁꢈꢈꢉ 966
ꢀ
ꢀ
3LQꢁꢈꢈꢊ 1&
1& 3LQꢁꢃꢂꢊ
9
66 ꢀ 3LQꢁꢃꢂꢆ
ꢀ
ꢀ
9'' 3LQꢁꢃꢂꢋ
3LQꢁꢈꢈꢋ 6&.
9
'' ꢀ 3LQꢁꢃꢂꢇ
9
'' ꢀ 3LQꢁꢃꢃꢃ
9
'' ꢀ 3LQꢁꢃꢃꢄ
9
'' ꢀ 3LQꢁꢃꢃꢅ
ꢀ
ꢀ
3LQꢁꢈꢄꢂ 966
966 3LQꢁꢃꢃꢂ
ꢀ
ꢀ
9'' 3LQꢁꢃꢃꢈ
3LQꢁꢈꢄꢈ 9''
ꢀ
ꢀ
3LQꢁꢈꢄꢉ 966
966 3LQꢁꢃꢃꢉ
ꢀ
ꢀ
9'' 3LQꢁꢃꢃꢊ
3LQꢁꢈꢄꢊ 9''
9
77 ꢀ 3LQꢁꢃꢃꢆ
ꢀ
6$ꢈ 3LQꢁꢃꢃꢋ
3LQꢁꢈꢄꢋ 9''63'
3LQꢁꢈꢉꢂ 6$ꢃ
6'$ ꢀ 3LQꢁꢃꢃꢇ
0337ꢂꢅꢈꢂ
ꢀ
6&/ 3LQꢁꢃꢈꢂ
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
11
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
3
Basic Functionality
This chapter describes the basic functionality.
3.1
Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.
3.2
Advanced Memory Buffer Functionality
The Advanced Memory Buffer will perform the following FB-
DIMM channel functions:
•
•
•
Detects errors on the channel and reports them to the host
memory controller.
Support the FB-DIMM configuration register set as defined
in the register chapters.
Acts as DRAM memory buffer for all read, write, and
configuration accesses addressed to the DIMM.
Provides a read buffer FIFO and a write buffer FIFO.
Supports an SMBus protocol interface for access to the
AMB configuration registers.
Provides logic to support MEMBIST and IBIST Design for
Test functions.
Provides a register interface for the thermal sensor and
status indicator.
Functions as a repeater to extend the maximum length of
FB-DIMM Links.
•
Supports channel initialization procedures as defined in
the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame
boundaries, verify channel connectivity, and identify AMB
DIMM position.
•
•
•
•
Supports the forwarding of southbound and northbound
frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the
return data into the northbound frames.
If the AMB resides on the last DIMM in the channel, the
AMB initializes northbound frames.
•
•
•
Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower
speed tester access to DRAM pins through the FB-DIMM I/O
pins. This allows the tester to send an arbitrary test pattern to
the DRAMs. Transparent mode only supports a maximum
DRAM frequency equivalent to DDR2 400. Transparent mode
functionality:
•
Reconfigures FB-DIMM inputs from differential high speed
link receivers to two single ended lower speed receivers
(~200 MHz)
These inputs directly control DDR2 Command/Address
and input data that is replicated to all DRAMs
Uses low speed direct drive FB-DIMM outputs to bypass
high speed Parallel/Serial circuitry and provide test results
back to tester
•
•
DDR2 SDRAM Interface
•
•
Supports DDR2 at speeds of 533, 667, 800 MT/s
Supports 256Mb, 512Mb and 1Gb devices in x4 and x8
configurations
•
72-bit DDR2 SDRAM memory array
3.3
Interfaces
Figure 2 illustrates the Advanced Memory Buffer and all of its
interfaces. They consist of two FB-DIMM links, one DDR2
channel and an SMBus interface. Each FB-DIMM link
connects the Advanced Memory Buffer to a host memory
controller or an adjacent FB-DIMM. The DDR2 channel
supports direct connection to the DDR2 SDRAMs on a Fully
Buffered DIMM.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
12
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
FIGURE 2
Block Diagram Advanced Memory Buffer Interface
-EMORY )NTERFACE
." &"$
IN ,INK
." &"$
OUT ,INK
0RIMARY OR (OST
$IRECTION
3ECONDARY OR TO
OPTIONAL NEXT &"$
3" &"$
IN ,INK
3" &"$
OUT ,INK
!-"
3-"
-0"4ꢀꢁꢂꢀ
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide
expansion from a single DIMM per channel to up to 8 DIMMs
per channel. The host sends data on the southbound link to
the first DIMM where it is received and redriven to the second
DIMM. On the southbound data path each DIMM receives the
data and again re-drives the data to the next DIMM until the
last DIMM receives the data. The last DIMM in the chain
initiates the transmission of data in the direction of the host
(a.k.a. northbound). On the northbound data path each DIMM
receives the data and re-drives the data to the next DIMM
until the host is reached.
FIGURE 3
Block Diagram of Channel Southbound and Northbound Paths
(OST
3OUTHBOUND
.OURTHBOUND
!-"
!-"
!-"
!-"
NꢄC
NꢄC
-0"4ꢀꢁꢃꢀ
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
13
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
3.4
High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces
The Advanced Memory Buffer supports one FB-DIMM
Channel consisting of two bidirectional link interfaces using
highspeed differential point-to-point electrical signaling. The
southbound input link is 10 lanes wide and carries commands
and write data from the host memory controller or the
adjacent DIMM in the host direction. The southbound output
link forwards this same data to the next FB-DIMM. The
northbound input link is 14 lanes wide and carries read return
data or status information from the next FB-DIMM in the chain
back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any
read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel
southbound on 10 primary differential signal line pairs. Data
received from the DRAMs and status information travel
northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated
and travel further southbound on 10 secondary differential
pairs. Data and status information received from the adjacent
DIMM upstream travel further northbound on 14 secondary
differential pairs.
3.4.1
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports
direct connection to DDR2 SDRAMs. The DDR2 channel
supports two ranks of eight banks with 16 row/column
request, 64 data, and eight check-bit signals. There are two
copies of address and command signals to support DIMM
routing and electrical requirements. Four transfer bursts are
driven on the data and check-bit lines at 800 MHz.
Propagation delays between read data/check-bit strobe lanes
on a given channel can differ. Each strobe can be calibrated
by hardware state machines using write/read trial and error.
Hardware aligns the read data and check-bits to a single core
clock. The Advanced Memory Buffer provides four copies of
the command clock phase references (CLK[3:0]) and write
data/check-bit strobes (DQSs) for each DRAM nibble.
3.4.2
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface
to allow system access to configuration registers independent
of the FB-DIMM link. The Advanced Memory Buffer will never
be a master on the SMBus, only a slave. Serial SMBus data
transfer is supported at 100 kHz. SMBus access to the
Advanced Memory Buffer may be a requirement to boot and
to set link strength, frequency and other parameters needed
to insure robust configurations. It is also required for
diagnostic support when the link is down. The SMBus
address straps located on the DIMM connector are used by
the unique ID.
3.4.3
Channel Latency
FB-DIMM channel latency is measured from the time a read
request is driven on the FB-DIMM channel pins to the time
when the first 16 bytes (2nd chunk) of read completion data is
sampled by the memory controller. When not using the
Variable Read Latency capability, the latency for a specific
DIMM on a channel is always equal to the latency for any
other DIMM on that channel. However, the latency for each
DIMM in a specific configuration with some number of DIMMs
installed may not be equal to the latency for each FB-DIMM
in a configuration with some different number of DIMMs
installed. As more DIMMs are added to the channel,
additional latency is required to read from each DIMM on the
channel. Because the channel is based on the point-to-point
interconnection of buffer components between DIMMs,
memory requests are required to travel through N-1 buffers
before reaching the Nth buffer. The result is that a 4 DIMM
channel configuration will have greater idle read latency
compared to a 1 DIMM channel configuration. The Variable
Read Latency capability can be used to reduce latency for
DIMMs closer to the host. The idle latencies listed in this
section are representative of what might be achieved in
typical AMB designs. Actual implementations with latencies
less than the values listed will have higher application
performance and vice versa.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
14
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
3.4.4
Peak Theoretical Channel Throughput
An FB-DIMM channel transfers read completion data on the
Northbound data connection. 144 bits of data are transferred
for every Northbound data frame. This matches the 18-byte
data transfer of an ECC DDR DRAM in a single DRAM
command clock. A DRAM burst of 8 from a single channel or
a DRAM burst of four from two lock stepped channels
provides a total of 72 bytes of data (64 bytes plus 8 bytes
ECC). The FB-DIMM frame rate matches the DRAM
command clock because of the fixed 6:1 ratio of the FB-DIMM
channel clock to the DRAM command clock. Therefore, the
Northbound data connection will exhibit the same peak
theoretical throughput as a single DRAM channel. For
example, when using DDR2 533 DRAMs, the peak theoretical
bandwidth of the Northbound data connection is 4.267
GB/sec. Write data is transferred on the Southbound
command and data connection, via Command+Wdata
frames. 72 bits of data are transferred for every
Command+Wdata frame. Two Command+Wdata frames
match the 18-byte data transfer of an ECC DDR DRAM in a
single DRAM command clock. A DRAM burst of 8 transfers
from a single channel, or a burst of 4 from two lock-step
channels provides a total of 72 bytes of data (64 bytes plus 8
bytes ECC). When the frame rate matches the DRAM
command clock, the Southbound command and data
connection will exhibit one half the peak theoretical
throughput of a single DRAM channel. For example, when
using DDR2 533 DRAMs, the peak theoretical bandwidth of
the Southbound command and data connection is 2.133
GB/sec. The total peak theoretical throughput for a single FB-
DIMM channel is defined as the sum of the peak theoretical
throughput of the Northbound data connection and the
Southbound command and data connection. When the frame
rate matches the DRAM command clock, this is equal to 1.5
times the peak theoretical throughput of a single DRAM
channel. For example, when using DDR2 533 DRAMs, the
peak theoretical throughput of a single DDR2-533 channel
would be 4.267 GB/sec., while the peak theoretical
throughput of the entire FB-DIMM PC4200F channel would
be 6.4GB/sec.
3.5
Hot-add
The FB-DIMM channel does not provide a mechanism to
automatically detect and report the addition of a new DIMM
south of the currently active last DIMM. It is assumed the
system will be notified through some means of the addition of
one or more new DIMMs so that specific commands can be
sent to the host controller to initialize the newly added
DIMM(s) and perform a Hot-Add Reset to bring them into the
channel timing domain. It should be noted that the power to
the DIMM socket must be removed before a “hot-add” DIMM
is inserted or removed. Applying or removing the power to a
DIMM socket is a system platform function.
3.6
Hot-remove
In order to accomplish removal of DIMMs the host must
perform a Fast Reset sequence targeted at the last DIMM that
will be retained on the channel. The Fast Reset re-establish
the appropriate last DIMM so that the Southbound Tx outputs
of the last active DIMM and the Southbound and Northbound
outputs of the DIMMs beyond the last active DIMM are
disabled. Once the appropriate outputs are disabled the
system can coordinate the procedure to remove power in
preparation for physical removal of the DIMM if needed. It
should be noted that the power to the DIMM socket must be
removed before a “hot-add” DIMM is inserted or removed.
Applying or removing the power to a DIMM socket is a system
platform function.
3.7
Hot-replace
Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
15
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
4
Electrical Characteristics
This chapter describes the electrical characteristics.
4.1
Operating Conditions
This chapter describes the operating conditions.
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Notes
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VCC pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
–0.5
–0,3
–0.5
–0.5
–0.3
–55
+2.3
1.75
+2.3
+2.3
+1.75
+100
2.3
V
V
V
V
V
°C
V
VCC
–
1)2)
VDDQ
VDDL
VIN, VOUT
TSTG
VTT
1)2)
1)
1)2)
Voltage on VTT pin relative to VSS
–0.5
–
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
Operating Temperature Range
Symbol
Parameter
Values
Unit
Note
Min.
Max.
1)2)3)
1)
TCASE
TCASE
DRAM Component Case Temperature Range
AMB Component Case Temperature Range
0
0
+95
°C
°C
+110
1) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
2) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85C case
temperature before initiating self-refresh operation.
3) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
16
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
Min.
Nom.
Max.
AMB Supply Voltage
VCC
1.455
1.7
1.5
1.575
1.9
V
–
–
–
DRAM Supply Voltage
VDD
1.8
V
Termination Voltage
VTT
0.48 ×VDD
3.0
0.50 ×VDD
0.52 ×VDD
3.6
V
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
DC Input Logic High(RESET)
DC Input Logic Low(RESET)
Leakage Current (RESET)
Leakage Current (Link)
VDDSPD
VIH(DC)
VIL(DC)
VIH(DC)
VIL(DC)
IL
3.3
—
—
—
—
—
—
V
–
1)
2.1
VDDSPD
0.8
V
1)
2)
1)
2)
3)
—
V
1.0
—
V
—
+0.5
+90
V
–90
–5
µΑ
µΑ
IL
+5
1) Applies for SMB and SPD Bus Signals
2) Applies for AMB CMOS Signal RESET
3) For all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications
TABLE 11
Timing Parameters
Parameter
Symbol
EI Propagatet
tEID
tEI
Min.
Typ.
Max.
Units
Notes
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
t
—
—
100
—
—
—
—
—
—
—
—
4
clks
clks
clks
ns
—
—
Bitlock
—
2
1)2)
—
3)
FBD Cmd to DDR Clk out that latches Cmd
FBD Cmd to DDR Write
—
8.1
TBD
5.0
1.075
2.075
—
—
—
—
ns
4)
DDR Read to FBD (last DIMM)
Resample Pass-Thru time
ResynchPass-Thru time
—
—
ns
—
—
ns
—
—
ns
1)
1)
Bit Lock Interval
tBitLock
tFrameLock
119
154
frames
frames
Frame Lock Interval
—
1) Defined in FB-DIMM Architecture and Protocol Spec
2) Clocks defined as core clocks = 2x SCK input
3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to
the DRAMs
4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
17
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
TABLE 12
Environmental Parameters
Parameter
Symbol
Rating
Units
Notes
1)
Operating Temperature
TOPR
HOPR
TSTG
HSTG
PBAR
PBAR
See Note
10 to 90
-50 to +100
5 to 95
2)
2)
2)
2)
2)
Operating Humidity (relative)
Storage Temperature
%
°C
%
m
m
Storage Humidity (without condensation)
Barometric pressure (operating)
Barometric pressure (storage)
3050
14240
1) The designer must meet the case temperature specifications for individual module components.
2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
18
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
5
Current Spec. and Conditions
The following table provides an overview of the measurement conditions.
TABLE 13
DD Measurement Conditions
I
Parameter
Symbol
Idle Current, single or last DIMM
L0 state, idle (0 BW)
ICC_Idle_0
IDD_Idle_0
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
Idle Current, first DIMM
L0 state, idle (0 BW)
ICC_Idle_1
IDD_Idle_1
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
Active Power
L0 state
ICC_Active_1
IDD_Active_1
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Active Power, data pass through
L0 state
ICC_Active_2
IDD_Active_2
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Training
ICC_Training
IDD_Training
Primary and Secondary channels enabled.
100% toggle on all channels lanes.
DRAMs idle (0 BW).
CKE high. Command and address lines stable.
DRAM clock active.
IBIST
ICC_IBIST
Over all IBIST modesDRAM Idle (0 BW)Primary channel EnabledSecondary channel EnabledCKE high.
Command and Address lines stableDRAM clock active
IDD_IBIST
MemBIST
ICC_MEMBIST
IDD_MEMBIST
Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)Primary channel EnabledSecondary
channel EnabledCKE high. Command and Address lines stableDRAM clock active
Electrical Idle
ICC_EI
DRAM Idle (0 BW)Primary channel DisabledSecondary channel DisabledCKE low. Command and Address IDD_EI
lines FloatedDRAM clock active, ODT and CKE driven low
Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
19
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.
7. Termination is referenced to VTT = VDD / 2.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
20
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
5.1
ICC/IDD Conditions
In the following table you can find the Measurement Conditions and Power Supply Currents1)2)
Note: Conditions for 2.5 has TBD
TABLE 14
ICC/IDD Specification for PC2-5300F
Product Type
Unit Note
Speed Grade PC2-5300F
PC2-5300F
Typ.
PC2-5300F
Symbol
Typ.
Typ.
ICC_Idle_0
1.65
2.51
0.82
1.46
2.5
1.67
2.54
1.16
2.05
2.88
4.64
2.69
4.03
1.15
2.03
3.88
6.1
1.67
2.54
2.04
3.6
A
PCC_Idle_0
IDD_Idle_0
W
A
PDD_Idle_0
ITOT_Idle_0
PTOT_Idle_0
ICC_Idle_1
W
A
3.8
3.99
2.67
4
6.22
2.67
4.01
2.01
3.54
4.78
7.64
2.84
4.25
3.99
6.98
6.91
11.3
2.81
4.21
1.92
W
A
PCC_Idle_1
IDD_Idle_1
W
A
0.82
1.46
3.51
5.48
2.81
4.21
1.93
3.4
PDD_Idle_1
ITOT_Idle_1
PTOT_Idle_1
ICC_Active_1
PCC_Active_1
IDD_Active_1
PDD_Active_1
ITOT_Active_1
PTOT_Active_1
ICC_Active_2
PCC_Active_2
IDD_Active_2
W
A
W
A
2.83
4.24
2.3
W
A
4.04
5.18
8.33
2.76
4.14
0.66
W
A
4.76
7.63
2.76
4.13
0.66
W
A
W
A
1) Measured currents on raw card A/B/H/D according to the INTEL/ JEDEC specifcation.The measurements are done in a INTEL Blackford
system.
2) The Power is calculated as follows: Pcc = Vcc x Icc where = 1.5 V
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
21
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Unit Note
Speed Grade PC2-5300F
PC2-5300F
Typ.
PC2-5300F
Typ.
Symbol
Typ.
PDD_Active_2
ITOT_Active_2
PTOT_Active_2
ICC_IBIST
1.17
3.42
5.3
1.17
3.46
5.34
3.24
4.84
0.96
1.7
3.38
4.75
7.6
W
A
W
A
3.21
4.79
0.65
1.14
3.86
5.94
2.99
4.47
0.65
1.14
3.64
5.62
2.07
3.12
0.09
0.16
2.21
3.32
2.82
4.22
2.13
3.76
4.96
7.99
3.23
4.82
1.72
3.03
5.03
7.92
3.01
4.5
PCC_IBIST
IDD_IBIST
W
A
PDD_IBIST
ITOT_IBIST
PTOT_IBIST
ICC_Training
PCC_Training
IDD_Trainig
PDD_Training
ITOT_Trainig
PTOT_Training
ICC_EI
W
A
4.23
6.56
3.02
4.51
0.96
1.7
W
A
W
A
1.72
3.04
4.8
W
A
4.02
6.25
2.1
7.6
W
A
2.1
PCC_EI
3.16
0.12
0.2
3.16
0.2
W
A
IDD_EI
PDD_EI
0.36
2.4
W
A
ITOT_EI
2.28
3.42
2.85
4.26
2.48
4.37
5.34
8.65
PTOT_EI
3.6
W
A
ICC_MEMBIST
PCC_MEMBIST
IDD_MEMBIST
PDD_MEMBIST
ITOT_MEMBIST
PTOT_MEMBIST
2.86
4.29
3.98
6.97
6.88
11.28
W
A
W
A
W
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
22
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
TABLE 15
ICC/IDD Specification for PC2-4200F
Product Type
Unit Note
Speed Grade PC2-4200F
PC2-4200F
Typ.
PC2-4200F
Typ.
Symbol
Typ.
ICC_Idle_0
1.49
2.27
0.79
1.4
1.5
1.52
2.28
1.92
3.34
3.52
5.71
2.45
3.63
1.79
3.13
4.31
6.83
2.6
A
PCC_Idle_0
IDD_Idle_0
2.29
1.09
1.93
2.65
4.27
2.43
3.65
1.09
1.92
3.57
5.62
2.56
3.85
2.3
W
A
PDD_Idle_0
ITOT_Idle_0
PTOT_Idle_0
ICC_Idle_1
W
A
2.29
3.67
2.41
3.63
0.79
1.4
W
A
PCC_Idle_1
IDD_Idle_1
W
A
PDD_Idle_1
ITOT_Idle_1
PTOT_Idle_1
ICC_Active_1
PCC_Active_1
IDD_Active_1
PDD_Active_1
ITOT_Active_1
PTOT_Active_1
ICC_Active_2
PCC_Active_2
IDD_Active_2
PDD_Active_2
ITOT_Active_2
PTOT_Active_2
ICC_IBIST
W
A
3.22
5.04
2.54
3.82
1.97
3.47
4.53
7.31
2.53
3.8
W
A
3.86
4.2
W
A
4.06
4.92
7.96
2.51
3.78
0.62
1.09
3.15
4.89
2.89
4.33
0.88
1.56
6.69
6.87
10.62
2.5
W
A
W
A
3.75
0.75
1.24
3.27
5
W
A
0.62
1.09
3.15
4.89
2.86
4.29
0.6
W
A
W
A
2.91
4.31
1.51
2.76
PCC_IBIST
W
A
IDD_IBIST
PDD_IBIST
1.06
W
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
23
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Unit Note
Speed Grade PC2-4200F
PC2-4200F
Typ.
PC2-4200F
Typ.
Symbol
Typ.
ITOT_IBIST
PTOT_IBIST
ICC_Training
PCC_Training
IDD_Trainig
PDD_Training
ITOT_Trainig
PTOT_Training
ICC_EI
3.5
3.81
5.92
2.71
4.06
0.88
1.56
3.63
5.65
1.86
2.82
0.11
0.2
4.47
7.12
2.73
4.04
1.51
2.76
4.3
A
5.39
2.68
4.03
0.6
W
A
W
A
1.06
3.33
5.13
1.85
2.79
0.09
0.15
1.98
2.99
2.54
3.82
2.06
3.64
4.66
7.51
W
A
6.86
1.89
2.82
0.26
0.36
2.25
3.26
2.61
3.86
3.99
6.42
6.63
10.3
W
A
PCC_EI
W
A
IDD_EI
PDD_EI
W
A
ITOT_EI
2.04
3.07
2.56
3.84
2.38
4.19
4.95
8.04
PTOT_EI
W
A
ICC_MEMBIST
PCC_MEMBIST
IDD_MEMBIST
PDD_MEMBIST
ITOT_MEMBIST
PTOT_MEMBIST
W
A
W
A
W
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
24
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
6
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
Table 16 “PC2–6400–666” on Page 25
Table 17 “PC2–6400–666” on Page 30
Table 18 “PC2–6400–666” on Page 35
TABLE 16
PC2–6400–666
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–6400F–666 PC2–6400F–666 PC2–6400F–666
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
SPD Size CRC / Total / Used
SPD Revision
92
11
09
12
44
23
07
09
00
01
04
0A
20
92
11
09
12
44
23
07
11
00
01
04
0A
20
92
11
09
12
48
23
07
10
00
01
04
0A
20
1
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
3
4
5
Module Physical Attributes
Module Type
6
7
Module Organization
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
9
10
11
12
t
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
25
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–6400F–666 PC2–6400F–666 PC2–6400F–666
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
CAS Latencies Supported
43
3C
52
3C
92
60
3C
1E
3C
00
B4
DC
A4
01
1E
43
3C
52
3C
92
60
3C
1E
3C
00
B4
DC
A4
01
1E
1E
03
07
01
C2
50
7A
58
34
36
2E
43
3C
52
3C
92
60
3C
1E
3C
00
B4
DC
A4
01
1E
1E
03
07
01
C2
50
7A
58
34
36
2E
t
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
t
t
t
t
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
RFC.MIN LSB (min. Refresh Recovery Time Delay)
RFC.MIN MSB (min. Refresh Recovery Time Delay)
WTR.MIN (min. Internal Write to Read Cmd Delay)
RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
50
7A
58
34
36
2E
t
REFI (avg. SDRAM Refresh Period)
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
26
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–6400F–666 PC2–6400F–666 PC2–6400F–666
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
39
40
41
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
5A
22
25
00
01
00
02
00
20
54
50
44
26
3F
50
54
57
53
00
00
11
CA
00
D5
60
08
5A
22
25
00
21
00
02
00
20
54
50
44
26
3F
50
54
57
53
00
00
11
49
00
D5
60
08
5A
22
25
00
21
00
02
00
20
54
50
44
26
3F
50
54
57
53
00
00
11
49
00
D5
60
08
∆T7 (DT7) DRAM
42 - 78 Not used
FBDIMM ODT Values
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
27
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–6400F–666 PC2–6400F–666 PC2–6400F–666
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
02
00
00
4c
00
00
00
00
00
00
00
85
51
85
51
xx
xx
xx
xx
02
00
00
4c
00
00
00
00
00
00
00
85
51
85
51
xx
xx
xx
xx
02
00
00
4c
00
00
00
00
00
00
00
85
51
85
51
xx
xx
xx
xx
Module Manufacturing Date Year
Module Manufacturing Date Week
122 -
125
Module Serial Number
126
127
128
129
130
131
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
CC
A9
37
32
54
36
11
7B
37
32
54
31
C1
3F
37
32
54
32
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
28
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–6400F–666 PC2–6400F–666 PC2–6400F–666
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
34
34
30
30
48
46
41
32
2E
35
42
20
20
20
6x
xx
32
38
30
32
30
48
46
41
32
2E
35
42
20
20
7x
xx
35
36
30
32
30
48
46
41
32
2E
35
42
20
20
6x
xx
Test Program Revision Code
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
85
51
43
10
00
85
51
43
10
00
85
51
43
10
00
152 -
175
176 -
255
Blank for customer use
FF
FF
FF
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
29
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
TABLE 17
PC2–6400–666
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
SPD Size CRC / Total / Used
SPD Revision
92
11
09
12
44
23
07
09
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
3C
00
92
11
09
12
44
23
07
11
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
3C
00
92
11
09
12
48
23
07
10
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
3C
00
1
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
3
4
5
Module Physical Attributes
Module Type
6
7
Module Organization
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
9
10
11
12
13
14
15
16
17
18
19
20
21
22
t
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
t
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
30
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
t
t
t
t
t
t
RAS.MIN (min. Active to Precharge Time)
B4
F0
A4
01
1E
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
20
23
00
22
00
02
00
10
54
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
20
23
00
22
00
02
00
10
54
RC.MIN (min. Active to Active / Refresh Time)
RFC.MIN LSB (min. Refresh Recovery Time Delay)
RFC.MIN MSB (min. Refresh Recovery Time Delay)
WTR.MIN (min. Internal Write to Read Cmd Delay)
RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
50
7A
48
2E
36
27
4C
20
23
00
01
00
02
00
10
54
t
REFI (avg. SDRAM Refresh Period)
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
31
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
85
86
87
88
89
90
91
92
93
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
50
44
26
3F
50
54
57
53
00
00
11
CA
00
D5
60
08
02
00
00
4c
00
00
00
00
00
00
50
44
26
3F
50
54
57
53
00
00
11
49
00
D5
60
08
02
00
00
4c
00
00
00
00
00
00
50
44
26
3F
50
54
57
53
00
00
11
49
00
D5
60
08
02
00
00
4c
00
00
00
00
00
00
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
104
105
106
107
108
109
110
111
112
113
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
32
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
114
115
116
117
118
119
120
121
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
00
85
51
85
51
xx
xx
xx
xx
00
85
51
85
51
xx
xx
xx
xx
00
85
51
85
51
xx
xx
xx
xx
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
122 -
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
83
68
37
32
54
36
34
34
30
30
48
46
41
33
53
42
D2
87
37
32
54
31
32
38
30
32
30
48
46
41
33
53
02
C3
37
32
54
32
35
36
30
32
30
48
46
41
33
53
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
33
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
20
20
20
20
8x
xx
85
51
43
10
00
42
20
20
20
0x
xx
85
51
43
10
00
42
20
20
20
0x
xx
85
51
43
10
00
Test Program Revision Code
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
152 -
175
176 -
255
Blank for customer use
FF
FF
FF
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
34
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
TABLE 18
PC2–6400–666
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
SPD Size CRC / Total / Used
SPD Revision
92
11
09
12
44
23
07
09
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
00
92
11
09
12
44
23
07
11
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
00
92
11
09
12
48
23
07
10
00
01
04
0F
20
33
3C
32
3C
72
50
3C
1E
3C
00
1
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
3
4
5
Module Physical Attributes
Module Type
6
7
Module Organization
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
9
10
11
12
13
14
15
16
17
18
19
20
21
22
t
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
t
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
35
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
t
t
t
t
t
t
RAS.MIN (min. Active to Precharge Time)
B4
F0
A4
01
1E
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
40
29
36
21
40
1E
22
00
22
00
02
00
10
54
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
40
29
36
21
40
1E
22
00
22
00
02
00
10
54
RC.MIN (min. Active to Active / Refresh Time)
RFC.MIN LSB (min. Refresh Recovery Time Delay)
RFC.MIN MSB (min. Refresh Recovery Time Delay)
WTR.MIN (min. Internal Write to Read Cmd Delay)
RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
50
7A
40
29
36
21
40
1E
22
00
01
00
02
00
10
54
t
REFI (avg. SDRAM Refresh Period)
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
36
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
85
86
87
88
89
90
91
92
93
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
50
44
26
3F
50
54
57
53
00
00
11
CA
00
D5
60
08
02
00
00
4c
00
00
00
00
00
00
50
44
26
3F
50
54
57
53
00
00
11
49
00
D5
60
08
02
00
00
4c
00
00
00
00
00
00
50
44
26
3F
50
54
57
53
00
00
11
49
00
D5
60
08
02
00
00
4c
00
00
00
00
00
00
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
104
105
106
107
108
109
110
111
112
113
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
37
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
114
115
116
117
118
119
120
121
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
00
85
51
85
51
xx
xx
xx
xx
00
85
51
85
51
xx
xx
xx
xx
00
85
51
85
51
xx
xx
xx
xx
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
122 -
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
27
07
37
32
54
36
34
34
30
30
48
46
41
33
2E
37
76
E8
37
32
54
31
32
38
30
32
30
48
46
41
33
2E
A6
AC
37
32
54
32
35
36
30
32
30
48
46
41
33
2E
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
38
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–4200F–444 PC2–4200F–444 PC2–4200F–444
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
42
20
20
20
9x
xx
85
51
43
10
00
37
42
20
20
0x
xx
85
51
43
10
00
37
42
20
20
0x
xx
85
51
43
10
00
Test Program Revision Code
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
152 -
175
176 -
255
Blank for customer use
FF
FF
FF
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
39
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
7
Package Outline
All Components are surface mounted on one or both sides of
the PCB and positioned on the PCB to meet the minimum and
maximum trace lengths required for DDR2 SDRAM signals.
Bypass capacitors for DDR2 SDRAM devices are located
near the device power pins. The AMB device in the center of
the DIMM has a metal Heat Sink.
TABLE 19
Raw Card Reference
PCB
Dimensions
Width [mm]
Height [mm]
Thickness [mm]
Notes
1)2)3)4)5)
L-DIM-240-21
L-DIM-240-22
L-DIM-240-25
Figure 4
Figure 5
Figure 6
133.35
133.35
133.35
30.35
30.35
30.35
8.2
8.2
8.2
1)2)3)4)5)
1)2)3)4)5)
1) Thickness includes Heat Sink. Some early production modules with Heatspreader may be thicker up to 8.2mm.
2) Please contact your sales or marketing representative for more details on package dimensions
3) Drawing according to ISO 8015.
4) Dimensions in mm.
5) General tolerances +/- 0.15.
Attention: Heat Sink heat up during operation. When unplugging a DIMM from a system direct skin contact should be
avoided until the Heat Sink has reached room temperature.
Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries.
Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while plugging or
unplugging the module may permanently damage the DIMM.
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
40
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
FIGURE 4
Package Outline L-DIM-240-21 with Full Module Heat Sink
ꢇꢁꢁꢅꢁꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢂꢃꢅꢃꢁ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢇꢂꢅꢉꢇ
ꢁꢅꢇꢉꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢉꢅꢋ
ꢈꢅꢆ -!8ꢅ
ꢉꢅꢋ
ꢇ
ꢇꢆꢀ
ꢀꢅꢇ
ꢆꢅꢃ
ꢃ
ꢈ
#
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢇꢅꢆꢉ
ꢀꢅꢇ
ꢀꢅꢇ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢆꢅꢇꢉꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢃꢇ
ꢊꢉ
!
ꢀꢅꢇ
ꢇꢅꢃ
"
ꢇꢆꢇ
ꢆꢂꢀ
ꢆꢅꢃ -).ꢅ
$ETAIL OF CONTACTS
ꢇ
ꢀꢅꢀꢃ
ꢀꢅꢈ
ꢀꢅꢇ ! " #
"URR MAXꢅ ꢀꢅꢂ ALLOWED
',$ꢀꢇꢀꢆꢈ
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
41
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
FIGURE 5
Package Outline L-DIM-240-22 with Full Module Heat Sink
ꢇꢁꢁꢅꢁꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢂꢃꢅꢃꢁ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢇꢂꢅꢉꢇ
ꢁꢅꢇꢉꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢉꢅꢋ
ꢈꢅꢆ -!8ꢅ
ꢉꢅꢋ
ꢇ
ꢇꢆꢀ
ꢀꢅꢇ
ꢆꢅꢃ
ꢃ
ꢈ
#
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢇꢅꢆꢉ
ꢀꢅꢇ
ꢀꢅꢇ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢆꢅꢇꢉꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢃꢇ
ꢊꢉ
!
ꢀꢅꢇ
ꢇꢅꢃ
"
ꢇꢆꢇ
ꢆꢂꢀ
ꢆꢅꢃ -).ꢅ
$ETAIL OF CONTACTS
ꢇ
ꢀꢅꢀꢃ
ꢀꢅꢈ
ꢀꢅꢇ ! " #
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
42
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
FIGURE 6
Package Outline L-DIM-240-25 with Full Module Heat Sink
ꢇꢁꢁꢅꢁꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢂꢃꢅꢃꢁ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢁꢅꢇꢉꢃ
ꢇꢂꢅꢉꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢉꢅꢋ
ꢈꢅꢆ -!8ꢅ
ꢉꢅꢋ
ꢇ
ꢇꢆꢀ
ꢀꢅꢇ
ꢆꢅꢃ
ꢃ
ꢈ
#
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢀꢅꢇ
ꢇꢂꢅꢉꢇ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢇꢅꢆꢉ
ꢀꢅꢇ
ꢀꢅꢇ
ꢂꢃꢅꢃꢁ
ꢀꢅꢇ
ꢆꢅꢇꢉꢃ
ꢀꢅꢇ
ꢀꢅꢇ
ꢃꢇ
ꢊꢉ
!
ꢀꢅꢇ
ꢇꢅꢃ
"
ꢇꢆꢇ
ꢆꢂꢀ
ꢆꢅꢃ -).ꢅ
$ETAIL OF CONTACTS
ꢇ
ꢀꢅꢀꢃ
ꢀꢅꢈ
ꢀꢅꢇ ! " #
"URR MAXꢅ ꢀꢅꢂ ALLOWED
',$ꢀꢇꢀꢂꢈ
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
43
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
8
DDR2 Nomenclature
TABLE 20
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64
0
2
0
0
K
A
M
C
–5
–5
–A
512
16
TABLE 21
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Module Prefix
HYS
64
Constant
Non-ECC
ECC
Module Data Width [bit]
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
5
6
7
8
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
Package,
Lead-Free Status
9
Module Type
D
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
10
Speed Grade
–2.5
–3
–3S
–3.7
–5
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
44
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Field
Description
Values
Coding
11
Die Revision
–A
–B
First
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 22
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Component Prefix
HYB
18
Constant
SSTL_18
DDR2
Interface Voltage [V]
DRAM Technology
T
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package,
C
FBGA,
Lead-Free Status
Lead-containing
F
FBGA, lead-free
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
10
Speed Grade
–2.5
–3
–3S
–3.7
–5
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
45
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B
Fully-Buffered DDR2 SDRAM Modules
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
Basic Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Advanced Memory Buffer Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hot-add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hot-remove. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hot-replace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.6
3.7
4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
5.1
Current Spec. and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ICC/IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
7
8
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DDR2 Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Rev.1.01, 2007-06-20
10062006-RQWY-GI6S
46
Internet Data Sheet
Edition 2007-06-20
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
www.qimonda.com
相关型号：
©2020 ICPDF网 联系我们和版权申明