IMHH4GP12A1F1C-10F [QIMONDA]
DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240;
| 型号： | IMHH4GP12A1F1C-10F |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM Module, 512MX72, CMOS, GREEN, DIMM-240 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总69页 (文件大小：3418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2008
IM[S/H]H1GP03A1F1C
IM[S/H]H2GP[13/02]A1F1C
IM[S/H]H4GP[23/12]A1F1C
240-Pin DDR3 Registered Modules with Parity bit
1-GByte, 2-GByte and 4-GByte
EU RoHS Compliant
Advance
Internet Data Sheet
Rev. 0.63
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
IM[S/H]H1GP03A1F1C, IM[S/H]H2GP[13/02]A1F1C, IM[S/H]H4GP[23/12]A1F1C
Revision History: 2008-11, Rev. 0.63
Page
Subjects (major changes since last revision)
All
Editoral changes and adapted to internet edition.
Previous Revision: 2008-04, Rev. 0.62
All
Updated package outline, SPD codes, and editoral changes.
Previous Revision: 2008-04, Rev. 0.61
43 - 79
Previous Revision: 2008-04, Rev. 0.60
40 - 42 Updated IDD values.
Previous Revision: 2008-01, Rev. 0.51
Updated SPD Codes.
All
Added Product Types and related information for modules with Heat Spreader.
Previous Revision: 2007-12, Rev. 0.5
All
Data sheet for 1GB, 2GB and 4GB Registered Memory Modules with Parity bit Product Family.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_A4, 4.20, 2008-01-25
12122007-WJ2L-RGDP
2
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
1
Overview
This chapter gives an overview of the 240–pin Registered DDR3 Dual-In-Line Memory Modules product family with parity bit
for address and control bus and describes its main characteristics.
1.1
Features
•
•
240-pin 8-Byte DDR3 SDRAM Registered Dual-In-Line
Memory Modules with parity bit for address and control
bus.
Module organization: One rank – 128M × 72, 256M × 72,
two rank – 256M × 72, 512M × 72 , four rank – 512M × 72
Chip organization: 128M × 8, 256M × 4
PC3-10600 and PC3-8500 module speed grades.
4-GB, 2-GB, 1-GB modules built with 1-Gbit DDR3
SDRAMs in packages PG-TFBGA-78
DDR3 SDRAMs with a single 1.5 V (± 0.075 V) power
supply.
Asynchronous Reset.
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
•
On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
•
•
•
Refresh, Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
Serial Presence Detect with EEPROM.
On-DIMM Thermal Sensor.
•
•
•
•
•
•
RDIMM dimensions: 133.35 mm x 30 mm.
Based on standard reference raw cards: 'A', 'B', 'C', 'E' and
'H'
•
•
•
•
RoHS compliant products1).
TABLE 1
Performance Table for DDR3–1600 and DDR3–1333
Qimonda Speed Code
Module Speed Bin
Device Speed Bin
CL-nRCD-nRP
–13G
–13H
Unit
Note2)
PC3
–10600G
–1333G
8-8-8
–10600H
–1333H
9-9-9
DDR3
CL and CWL settings for maximum clock
frequency
CL = 8
CWL = 7
CL = 9
CWL = 7
MHz
Maximum Clock Frequency
and Data Rate
667
1333
667
1333
MHz
Mb/s
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
533
1066
533
1066
MHz
Mb/s
with above CL and CWL settings
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 2
Performance Table for DDR3–1066 and DDR3–800
Qimonda Speed Code
Module Speed Bin
Device Speed Bin
CL-nRCD-nRP
–10F
–10G
Unit
Note2)
PC3
–8500F
–1066F
7-7-7
–8500G
–1066G
8-8-8
DDR3
CL and CWL settings for maximum clock frequency CL = 7
CWL = 6
CL = 8
CWL = 6
MHz
Maximum Clock Frequency
and Data Rate
533
1066
533
1066
MHz
Mb/s
with above CL and CWL settings
Minimum Clock Frequency
and Data Rate
400
800
400
800
MHz
Mb/s
with above CL and CWL settings
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products.
2) The available CL and CWL settings depend on the SDRAM device speed bin. The CL setting and CWL setting result in maximum but also
minimum clock frequency requirements. When making a selection of operating clock frequency, both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting. For details, refer to Chapter 4.1 Speed Bins.
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
1.2
Description
The
Qimonda
IM[S/H]H[1G/2G/4G]PxxA1F1C
are
a PLL for the clock distribution. De-coupling capacitors, stub
resistors, calibration resistors and termination resistors are
mounted on the PCB. The DIMMs feature serial presence
detect based on a 256 byte serial EEPROM device using the
2-pin I2C protocol. The first 176 bytes are programmed with
module specific SPD data.
Registered DIMM (PDIMM) family with parity bit for address
and control bus and 30 mm height based on DDR3 SDRAM
technology. DIMMs are available in 128M × 72 (1-GB),
256M × 72 (2-GB), 512M × 72 (4-GB) organization and
density, intended for mounting into 240-pin connector
sockets.
The memory array is designed with 1-Gbit Double-Data-Rate-
Three (DDR3) Synchronous DRAMs. All control and address
signals are re-driven on the DIMM using register devices and
TABLE 3
Product Information for Modules without Heat Spreader
Qimonda Product Type
Compliance Code
Description
1-GByte Registered DIMM IMSH1GP03A1F1C
IMSH1GP03A1F1C–10F
1GB 1R×8 PC3–8500P–7-10–A0
1GB 1R×8 PC3–8500P–8-10–A0
240-pin 1-GByte DDR3 registered DIMM with one
rank and on-DIMM thermal sensor. The memory
rank consists of nine DDR3 components in x8
organization. Standard reference card A is used on
this assembly
IMSH1GP03A1F1C–10G
IMSH1GP03A1F1C–13G
IMSH1GP03A1F1C–13H
1GB 1R×8 PC3–10600P–8-10–A0
1GB 1R×8 PC3–10600P–9-10–A0
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
2-GByte Registered DIMM IMSH2GP13A1F1C
IMSH2GP13A1F1C–10F
IMSH2GP13A1F1C–10G
IMSH2GP13A1F1C–13G
IMSH2GP13A1F1C–13H
2GB 2R×8 PC3–8500P–7-10–B0
240-pin 2-GByte DDR3 registered DIMM with two
ranks and on-DIMM thermal sensor. Each memory
rank consists of nine DDR3 components in x8
organization. Standard reference card B is used on
this assembly
2GB 2R×8 PC3–8500P–8-10–B0
2GB 2R×8 PC3–10600P–8-10–B0
2GB 2R×8 PC3–10600P–9-10–B0
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
2-GByte Registered DIMM IMSH2GP02A1F1C
IMSH2GP02A1F1C–10F
IMSH2GP02A1F1C–10G
IMSH2GP02A1F1C–13G
IMSH2GP02A1F1C–13H
2GB 1R×4 PC3–8500P–7-10–C0
240-pin 2-GByte DDR3 registered DIMM with one
rank and on-DIMM thermal sensor. The memory
rank consists of eighteen DDR3 components in x4
organization. Standard reference card C is used on
this assembly
2GB 1R×4 PC3–8500P–8-10–C0
2GB 1R×4 PC3–10600P–8-10–C0
2GB 1R×4 PC3–10600P–9-10–C0
Used DDR3 SDRAM Component
Product Type: IDSH1G-02A1F1C
Density: 1-Gbit
Organization: 256Mbit × 4
Address Bits (Row/Column/Bank): 14/11/3
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Qimonda Product Type
Compliance Code
Description
4-GByte Registered DIMM IMSH4GP23A1F1C
IMSH4GP23A1F1C–10F
IMSH4GP23A1F1C–10G
IMSH4GP23A1F1C–13G
IMSH4GP23A1F1C–13H
4GB 4R×8 PC3–8500P–7-10–H0
240-pin 4-GByte DDR3 registered DIMM with four
ranks and on-DIMM thermal sensor. Each memory
rank consists of nine DDR3 components in x4
organization. Standard reference card H is used on
this assembly
4GB 4R×8 PC3–8500P–8-10–H0
4GB 4R×8 PC3–10600P–8-10–H0
4GB 4R×8 PC3–10600P–9-10–H0
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128-Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
4-GByte Registered DIMM IMSH4GP12A1F1C
IMSH4GP12A1F1C–10F
IMSH4GP12A1F1C–10G
IMSH4GP12A1F1C–13G
IMSH4GP12A1F1C–13H
4GB 2R×4 PC3–8500P–7-10–E0
240-pin 4-GByte DDR3 registered DIMM with two
ranks and on-DIMM thermal sensor. Each memory
rank consists of eighteen DDR3 components in x4
organization. Standard reference card E is used on
this assembly
4GB 2R×4 PC3–8500P–8-10–E0
4GB 2R×4 PC3–10600P–8-10–E0
4GB 2R×4 PC3–10600P–9-10–E0
Used DDR3 SDRAM Component
Product Type: IDSH1G-02A1F1C
Density: 1-Gbit
Organization: 256-Mbit × 4
Address Bits (Row/Column/Bank): 14/11/3
TABLE 4
Product Information for Modules with Heat Spreader
Description
Qimonda Product Type
Compliance Code
1-GByte Registered DIMM IMHH1GP03A1F1C
IMHH1GP03A1F1C–10F
1GB 1R×8 PC3–8500P–7-10–A0
1GB 1R×8 PC3–8500P–8-10–A0
240-pin 1-GByte DDR3 registered DIMM with one
rank and on-DIMM thermal sensor. The memory
rank consists of nine DDR3 components in x8
organization. Standard reference card A is used on
this assembly
IMHH1GP03A1F1C–10G
IMHH1GP03A1F1C–13G
IMHH1GP03A1F1C–13H
1GB 1R×8 PC3–10600P–8-10–A0
1GB 1R×8 PC3–10600P–9-10–A0
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128-Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
2-GByte Registered DIMM IMHH2GP13A1F1C
IMHH2GP13A1F1C–10F
IMHH2GP13A1F1C–10G
IMHH2GP13A1F1C–13G
IMHH2GP13A1F1C–13H
2GB 2R×8 PC3–8500P–7-10–B0
240-pin 2-GByte DDR3 registered DIMM with two
ranks and on-DIMM thermal sensor. Each memory
rank consists of nine DDR3 components in x8
organization. Standard reference card B is used on
this assembly
2GB 2R×8 PC3–8500P–8-10–B0
2GB 2R×8 PC3–10600P–8-10–B0
2GB 2R×8 PC3–10600P–9-10–B0
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128-Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
Rev. 0.63, 2008-11
6
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Qimonda Product Type
Compliance Code
Description
2-GByte Registered DIMM IMHH2GP02A1F1C
IMHH2GP02A1F1C–10F
IMHH2GP02A1F1C–10G
IMHH2GP02A1F1C–13G
IMHH2GP02A1F1C–13H
2GB 1R×4 PC3–8500P–7-10–C0
240-pin 2-GByte DDR3 registered DIMM with one
rank and on-DIMM thermal sensor. The memory
rank consists of eighteen DDR3 components in x4
organization. Standard reference card C is used on
this assembly
2GB 1R×4 PC3–8500P–8-10–C0
2GB 1R×4 PC3–10600P–8-10–C0
2GB 1R×4 PC3–10600P–9-10–C0
Used DDR3 SDRAM Component
Product Type: IDSH1G-02A1F1C
Density: 1-Gbit
Organization: 256-Mbit × 4
Address Bits (Row/Column/Bank): 14/11/3
4-GByte Registered DIMM IMHH4GP23A1F1C
IMHH4GP23A1F1C–10F
IMHH4GP23A1F1C–10G
IMHH4GP23A1F1C–13G
IMHH4GP23A1F1C–13H
4GB 4R×8 PC3–8500P–7-10–H0
240-pin 4-GByte DDR3 registered DIMM with four
ranks and on-DIMM thermal sensor. Each memory
rank consists of nine DDR3 components in x4
organization. Standard reference card H is used on
this assembly
4GB 4R×8 PC3–8500P–8-10–H0
4GB 4R×8 PC3–10600P–8-10–H0
4GB 4R×8 PC3–10600P–9-10–H0
Used DDR3 SDRAM Component
Product Type: IDSH1G-03A1F1C
Density: 1-Gbit
Organization: 128-Mbit × 8
Address Bits (Row/Column/Bank): 14/10/3
4-GByte Registered DIMM IMHH4GP12A1F1C
IMHH4GP12A1F1C–10F
IMHH4GP12A1F1C–10G
IMHH4GP12A1F1C–13G
IMHH4GP12A1F1C–13H
4GB 2R×4 PC3–8500P–7-10–E0
240-pin 4-GByte DDR3 registered DIMM with two
ranks and on-DIMM thermal sensor. Each memory
rank consists of eighteen DDR3 components in x4
organization. Standard reference card E is used on
this assembly
4GB 2R×4 PC3–8500P–8-10–E0
4GB 2R×4 PC3–10600P–8-10–E0
4GB 2R×4 PC3–10600P–9-10–E0
Used DDR3 SDRAM Component
Product Type: IDSH1G-02A1F1C
Density: 1-Gbit
Organization: 256-Mbit × 4
Address Bits (Row/Column/Bank): 14/11/3
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
2
Configuration
2.1
Pin Configuration
TABLE 5
Pin Configuration of DDR3 RDIMM - 240 Pins
Pin Name EDA Signal Pin No.
Name1)
Pin
Type Type
Buffer Function
Clock Signals
CK0
CK0
CK1
CK1
ck0_t
ck0_c
ck1_t
ck1_c
184
185
63
I
I
I
I
SSTL Differential Clock Inputs [1:0]
SSTL
SSTL
SSTL
64
Control Signals
CKE0
CKE1
ODT0
ODT1
S0
cke0
cke1
odt0
odt1
s0_n
s1_n
s2_n
s3_n
50
I
I
I
I
I
I
I
I
SSTL Clock Enable [1:0]
169
195
77
SSTL
SSTL On-Die Termination [1:0]
SSTL
193
76
SSTL Chip Select [3:0]
S1
SSTL
SSTL
SSTL
S2
79
S3
198
Command Signals
RAS
CAS
WE
ras_n
cas_n
we_n
192
74
I
I
I
SSTL Row Address Strobe
SSTL Column Address Strobe
SSTL Write Enable
73
Bank Address Signals
BA0
BA1
BA2
ba0
ba1
ba2
71
I
I
I
SSTL Bank Address Bus[2:0]
190
52
SSTL
SSTL
Address Signals
A0
A1
A2
A3
A4
a0
a1
a2
a3
a4
188
181
61
I
I
I
I
I
SSTL Address Bus [15:0]
SSTL
SSTL
SSTL
SSTL
180
59
Rev. 0.63, 2008-11
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Pin Name EDA Signal Pin No.
Name1)
Pin
Type Type
Buffer Function
A5
a5
58
I
I
I
I
I
I
I
I
I
I
I
SSTL Address Bus [15:0]
A6
a6
178
56
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
A7
a7
A8
a8
177
175
70
A9
a9
A10/AP
A11
A12/BC
A13
A14
A15
a10
a11
a12
a13
a14
a15
55
174
196
172
171
Data Signals
DQ0
dq0
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus [63:0]
SSTL
DQ1
dq1
4
DQ2
dq2
9
SSTL
DQ3
dq3
10
SSTL
DQ4
dq4
122
123
128
129
12
SSTL
DQ5
dq5
SSTL
DQ6
dq6
SSTL
DQ7
dq7
SSTL
DQ8
dq8
SSTL
DQ9
dq9
13
SSTL
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
dq10
dq11
dq12
dq13
dq14
dq15
dq16
dq17
dq18
dq19
dq20
dq21
dq22
dq23
dq24
dq25
dq26
dq27
18
SSTL
19
SSTL
131
132
137
138
21
SSTL
SSTL
SSTL
SSTL
SSTL
22
SSTL
27
SSTL
28
SSTL
140
141
146
147
30
SSTL
SSTL
SSTL
SSTL
SSTL
31
SSTL
36
SSTL
37
SSTL
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Pin Name EDA Signal Pin No.
Name1)
Pin
Type Type
Buffer Function
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB0
dq28
dq29
dq30
dq31
dq32
dq33
dq34
dq35
dq36
dq37
dq38
dq39
dq40
dq41
dq42
dq43
dq44
dq45
dq46
dq47
dq48
dq49
dq50
dq51
dq52
dq53
dq54
dq55
dq56
dq57
dq58
dq59
dq60
dq61
dq62
dq63
cb0
149
150
155
156
81
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus [63:0]
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL Check Bit [7:0]
SSTL
SSTL
SSTL
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
39
CB1
cb1
40
CB2
cb2
45
CB3
cb3
46
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Pin Name EDA Signal Pin No.
Name1)
Pin
Type Type
Buffer Function
CB4
cb4
158
159
164
165
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Check Bit [7:0]
CB5
cb5
SSTL
SSTL
SSTL
CB6
cb6
CB7
cb7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
(T)DQS9
(T)DQS9
dqs0_t
dqs0_c
dqs1_t
dqs1_c
dqs2_t
dqs2_c
dqs3_t
dqs3_c
dqs4_t
dqs4_c
dqs5_t
dqs5_c
dqs6_t
dqs6_c
dqs7_t
dqs7_c
dqs8_t
dqs8_c
dqs9_t
dqs9_c
SSTL Data Strobe Signals [17:0] and Completmentary Data Strobe
Signals [17:0]
6
SSTL
16
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
(T)DQS10 dqs10_t
(T)DQS10 dqs10_c
(T)DQS11 dqs11_t
(T)DQS11 dqs11_c
(T)DQS12 dqs12_t
(T)DQS12 dqs12_c
(T)DQS13 dqs13_t
(T)DQS13 dqs13_c
(T)DQS14 dqs14_t
(T)DQS14 dqs14_c
(T)DQS15 dqs15_t
(T)DQS15 dqs15_c
(T)DQS16 dqs16_t
(T)DQS16 dqs16_c
(T)DQS17 dqs17_t
(T)DQS17 dqs17_c
Rev. 0.63, 2008-11
11
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Pin Name EDA Signal Pin No.
Name1)
Pin
Type Type
Buffer Function
EEPROM and Thermal Sensor
SCL
SDA
SA0
SA1
SA2
scl
118
238
117
237
119
I
CMOS Serial Bus Clock
OD Serial Data Bus
sda
sa0
sa1
sa2
I/O
I
I
I
CMOS Serial Address Select Bus [2:0]
CMOS
CMOS
Power Supply
VDD vdd
51, 54,
PWR
-
Power Supply
57, 60,
62, 65,
66, 69,
72, 75,
78, 170,
173, 176,
179, 182,
183, 186,
189, 191,
194, 197
VSS
vss
2, 5, 8,
GND
-
Ground
11, 14,
17, 20,
23, 26,
29, 32,
35, 38,
41, 44,
47, 80,
83, 86,
89,92,95,
98, 101,
104, 107,
110, 113,
116, 121,
124,
127, 130,
133, 136,
139, 142,
145, 148,
151, 154,
157, 160,
163, 166,
199, 202,
205, 208,
211, 214,
217, 220,
223, 226,
229, 232,
235, 239
VREF.DQ
vrefdq
1
AI
-
Reference Voltage
Rev. 0.63, 2008-11
12
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Pin Name EDA Signal Pin No.
Name1)
Pin
Type Type
Buffer Function
VREF.CA
VTT
vrefca
vtt
67
AI
-
-
Reference Voltage
48, 49,
PWR
Termination Voltage
120 , 240
VDDSPD
vddspd
236
-
EEPROM and Thermal Sensor Power Supply
Other Pins
RESET
reset_n
168
53
I
Asynchronous Reset
Err_Out
Err_Out
err_out_n
O
OD
Par_In
EVENT
NC
par_in
event_n
nc
68
I
Par_In
187
O
-
OD
-
EVENT
79, 126,
Not Connected
135, 144,
153, 162,
167, 198,
204, 213,
222, 231,
1) The EDA (Electronic Design Automation) Signal Name is used in Qimonda Simulation Models such as EBD (Electronic Board Description).
TABLE 6
Abbreviations for Pin Type
Abbreviation
Description
I
Standard Input pin only. Digital levels.
Standard Output pin only - Digital levels.
I/O is a bidirectional input/output signal.
Input - Analog levels.
O
I/O
AI
PWR
GND
NC
Power
Ground
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
CMOS
OD
Serial Stub Terminated Logic
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
Rev. 0.63, 2008-11
13
12122007-WJ2L-RGDP
ꢇ
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
FIGURE 1
Pin Configuration RDIMM - 240 Pin
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3LQꢀꢂꢈꢂ ꢇ 966
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ꢇ 3LQꢀꢁꢁꢉ
ꢇ 3LQꢀꢁꢁꢊ
ꢇ 3LQꢀꢁꢁꢋ
ꢇ 3LQꢀꢁꢂꢁ
ꢇ 3LQꢀꢁꢂꢈ
ꢇ 3LQꢀꢁꢂꢉ
ꢇ 3LQꢀꢁꢂꢊ
ꢇ 3LQꢀꢁꢂꢋ
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3LQꢀꢂꢈꢉ ꢇ966
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966
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966
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ꢇ 3LQꢀꢁꢁꢃ
ꢇ 3LQꢀꢁꢁꢄ
ꢇ 3LQꢀꢁꢁꢅ
ꢇ 3LQꢀꢁꢁꢆ
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3LQꢀꢂꢈꢃ ꢇ '4ꢄ
3LQꢀꢂꢈꢄ ꢇ ꢎ7ꢏ'46ꢆ
3LQꢀꢂꢈꢅ ꢇ 966
3LQꢀꢂꢈꢆ ꢇ '4ꢅ
3LQꢀꢂꢃꢂ ꢇ '4ꢂꢈ
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3LQꢀꢂꢃꢄ ꢇ ꢎ7ꢏ'46ꢂꢁ
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3LQꢀꢂꢉꢄ ꢇ 966
3ꢀLQꢀꢂꢉꢅ ꢇ '4ꢈꢃ
3LQꢀꢂꢉꢆ ꢇ '4ꢈꢋ
3LQꢀꢂꢄꢂ ꢇ 966
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3LQꢀꢂꢄꢄ ꢇ '4ꢃꢁ
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3LQꢀꢂꢊꢂ ꢇ ꢎ7ꢏ'46ꢂꢅ
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966
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3LQꢀꢁꢄꢁ
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Rev. 0.63, 2008-11
12122007-WJ2L-RGDP
14
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
3
Operating Conditions
3.1
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Note
Min.
Max.
1)
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
VDD
–0.4
–0.4
–0.4
+1.975
+1.975
+1.975
V
V
V
VDDQ
VIN, VOUT
1)
V
DD and VDDQ must be within 300mV of each other at all times. VREFDQ and VREFCA must not be greater than 0.6 x VDDQ. When VDD and V
DDQ are less than 500 mV, VREFDQ and VREFCA may be equal or less than 300 mV.
TABLE 9
Environmental Parameters
Parameter
Symbol
Rating
Min.
Unit
Note
Max.
1)
2)
3)
Operating Temperature
TOPR
HOPR
TSTG
HSTG
–
–
°C
Operating Humidity (relative)
Storage Temperature
10
–50
5
90
%
+100
95
°C
Storage Humidity (without condensation)
%
Barometric Pressure (Operating and Storage) PBar
69
105
KPascal
1) Device designer must meet the case temperature specification for individual module components.
2) Storage Temperature is the case surface temperature on the center/top side of the SDRAM mentioned in Qimonda component datasheet.
3) Up to 9850 ft.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Rev. 0.63, 2008-11
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 10
DRAM Component Operating Temperature Range
Parameter
Symbol
Rating
Unit
Note
Min.
Max.
1)2)
1)3)
Normal Operating Temperature Range
Extended Temperature Range
TOPER
0
85
95
°C
°C
85
1) Operating Temperature TOPER is the case surface temperature on the center / top side of the SDRAM mentioned..
2) The Normal Temperature Range specifies the temperatures where all SDRAM specification will be supported.
3) Some application require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C operating temperature.
For more details please refer to Qimonda Component datasheet.
3.2
Recommended DC Operating Conditions
TABLE 11
DC Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit Note
1)2)
Supply Voltage
VDD
1.425
3.0
1.5
3.3
1.5
1.575
3.6
V
1)2)
Supply Voltage for EEPROM and Thermal Sensor
Supply Voltage for Output
VDD.SPD
VDDQ
V
1)2)
1.425
1.575
V
3)4)
Reference Voltage for DQ, DM inputs
Reference Voltage for ADD, CMD inputs
Terminal Voltage
VREFDQ.DC 0.49 x VDD 0.5 x VDD 0.51 x VDD
VREFCA.DC 0.49 x VDD 0.5 x VDD 0.51 x VDD
V
3)4)
V
VTT
0.49 x VDD 0.5 x VDD 0.51 x VDD
237.6 240.0 242.4
DDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together
2) Under all conditions VDDQ must be less than or equal to VDD
V
5)
External Calibration Resistor connected from ZQ pin to ground RZQ
Ω
1)
V
.
3) The ac peak noise on VREF may not allow VREF to deviate from VREF.DC by more than ±1% VDD (for reference: approx. ± 15 mV).
4) For reference: approx. VDD/2 ± 15 mV.
5) The external calibration resistor RZQ can be time-shared among DRAMs in multi-rank DIMMs.
Rev. 0.63, 2008-11
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
4
Speed Bins and Timing Parameters
AC timings are provided with CK/CK and DQS/DQS
differential slew rate of 2.0 V/ns. Timings are further provided
for calibrated OCD drive strength. The CK/CK input reference
level (for timing referenced to CK / CK) is the point at which
CK and CK cross.The DQS/DQS reference level (for timing
referenced to DQS/DQS) is the point at which DQS and DQS
cross. Inputs are not recognized as valid until VREF stabilizes.
During the period before VREF.CA and VREFDQ stabilizes, CKE
= 0.2 x VDDQ is recognized as low. The output timing reference
voltage level is VTT. For details of all relevant AC timing
parameters see the QIMONDA DDR3 component datasheet.
4.1
Speed Bins
The following tables show DDR3 speed bins and relevant
timing parameters. Other timing parameters are provided in
the following chapter.
The absolute specification for all speed bins is TOPER and
VDD = VDDQ = 1.5 V +/-0.075 V. In addition the following
general notes apply.
General Notes for Speed Bins:
•
The CL setting and CWL setting result in tCK.AVG.MIN and
in module application, tAA / tRCD / tRP should be
programmed with minimum supported values. For
example, DDR3-1333H supporting down-shift to DDR3-
1066F should program SPD as 13.125ns for tAA.MIN
(Byte16)/tRCD.MIN (Byte18) / tRP (Byte20). DDR3-1600K
supporting down-shift to DDR3-1333H and to DDR3-
1066F should program SPD as 13.125ns for tAA.MIN
(Byte16)/tRCD.MIN (Byte18) / tRP (Byte20)
Any DDR3-1066 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization
Any DDR3-1333 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization
Any DDR3-1600 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization
t
t
CK.AVG.MAX requirements. When making a selection of
CK.AVG, both need to be fulfiled: Requirements from CL
setting as well as requirements from CWL setting
• tCK.AVG.MIN limits: Since CAS Latency is not purely analog -
data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be provided. An
application should use the next smaller standard tCK.AVG
value (2.5, 1.875, 1.5, 1.25 , 1.07, or 0.935 ns) when
calculating CL [nCK] = tAA [ns] / tCK.AVG [ns], rounding up to
the next ‘Supported CL’
•
•
•
• tCK.AVG.MAX limits: Calculate tCK.AVG = tAA.MAX
/
CLSELECTED and round the resulting tCK.AVG down to the
next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns
1.5ns or 1.25ns or 1.07 ns or 0.935ns). This result is
t
CK.AVG.MAX corresponding to CLSELECTED
•
•
‘Reserved’ settings are not allowed. User must program a
different value
Downbinning support for DDR3-1333H and DDR3-1600K
parts: The minimum tAA / tRCD / tRP supported by DDR3-
1333H and DDR3-1600K devices is 13.125ns. Therefore,
Rev. 0.63, 2008-11
17
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 12
DDR3-1333 Speed Bins and Operating Conditions
Speed Bin
DDR3-1333G
DDR3-1333H
Unit Note
CL-nRCD-nRP
8-8-8
9-9-9
QAG Product Type Extension
Parameter
-13G
-13H
Symbol
Min.
Max.
Min.
Max.
1)
Internal read command to first data
tAA
12.0
12.0
12.0
48.0
20.0
—
13.125 20.0
13.125 —
13.125 —
49.125 —
ns
1)
ACT to internal read or write delay time
PRE command period
tRCD
ns
1)
tRP
—
ns
1)
ACT to ACT or REF command period
Supported CL Settings
tRC
—
ns
1)
Sup_CL
5, 6, 7, 8, 9, 10 6,7,8, 9, 10
nCK
1)
Supported CWL Settings
Sup_CWL
5, 6, 7
2.5
5, 6, 7
nCK
1)2)
Average Clock Period with CL = 5; CWL = 5
Average Clock Period with CL = 5; CWL = 6
Average Clock Period with CL = 5; CWL = 7
Average Clock Period with CL = 6; CWL = 5
Average Clock Period with CL = 6; CWL = 6
Average Clock Period with CL = 6; CWL = 7
Average Clock Period with CL = 7; CWL = 5
Average Clock Period with CL = 7; CWL = 6
Average Clock Period with CL = 7; CWL = 7
Average Clock Period with CL = 8; CWL = 5
Average Clock Period with CL = 8; CWL = 6
Average Clock Period with CL = 8; CWL = 7
Average Clock Period with CL = 9; CWL = 5
Average Clock Period with CL = 9; CWL = 6
Average Clock Period with CL = 9; CWL = 7
Average Clock Period with CL = 10; CWL = 5
Average Clock Period with CL = 10; CWL = 6
Average Clock Period with CL = 10; CWL = 7
tCK.AVG.CL05.CWL05
tCK.AVG.CL05.CWL06
tCK.AVG.CL05.CWL07
tCK.AVG.CL06.CWL05
tCK.AVG.CL06.CWL06
tCK.AVG.CL06.CWL07
tCK.AVG.CL07.CWL05
tCK.AVG.CL07.CWL06
tCK.AVG.CL07.CWL07
tCK.AVG.CL08.CWL05
tCK.AVG.CL08.CWL06
tCK.AVG.CL08.CWL07
tCK.AVG.CL09.CWL05
tCK.AVG.CL09.CWL06
tCK.AVG.CL09.CWL07
tCK.AVG.CL10.CWL05
tCK.AVG.CL10.CWL06
tCK.AVG.CL10.CWL07
3.3
RESERVED
RESERVED
RESERVED
ns
1)2)
RESERVED
RESERVED
ns
1)2)
ns
1)2)
2.5
3.3
2.5
3.3
ns
1)2)
RESERVED
RESERVED
RESERVED
1.875 2.5
RESERVED
RESERVED
1.875 2.5
RESERVED
RESERVED
RESERVED
1.875 2.5
RESERVED
RESERVED
1.875 2.5
ns
1)2)
ns
1)2)
ns
1)2)
ns
1)2)
ns
1)2)
ns
1)2)
ns
1)2)
1.5
1.875 RESERVED
ns
1)2)
RESERVED
RESERVED
RESERVED
RESERVED
ns
1)2)
ns
1)2)
1.5
1.875 1.5
1.875 ns
1)2)
1)2)
1)2)
RESERVED
RESERVED
RESERVED
RESERVED
ns
ns
1.5
1.875 1.5
1.875 ns
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.
2) Max. limits are exclusive. E.g. if tCK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 13
DDR3-1066 Speed Bins and Operating Conditions
Speed Bin
DDR3-1066E
DDR3-1066F
DDR3-1066G
Unit Note
CL-nRCD-nRP
6-6-6
7-7-7
8-8-8
QAG Product Type Extension
Parameter
-10E
-10F
-10G
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
1)
Internal read command to first data tAA
11.25 20.0
13.125 20.0
15.0
15.0
20.0
—
ns
1)
ACT to internal read or write delay
time
tRCD
11.25
—
13.125
—
ns
1)
PRE command period
tRP
tRC
11.25
48.75
—
—
13.125
50.625
—
—
15.0
52.5
—
—
ns
1)
ACT to ACT or REF command
period
ns
1)
Supported CL Settings
Supported CWL Settings
Sup_CL
5, 6, 7, 8
5, 6
6, 7, 8
5, 6
6, 8
5, 6
nCK
1)
Sup_CWL
nCK
1)2)
Average Clock Period with CL = 5; tCK.AVG.CL05.CWL05 2.5
3.3
RESERVED
RESERVED
ns
CWL = 5
1)2)
Average Clock Period with CL = 5; tCK.AVG.CL05.CWL06 RESERVED
RESERVED
RESERVED
ns
CWL = 6
1)2)
Average Clock Period with CL = 6; tCK.AVG.CL06.CWL05 2.5
3.3
2.5
3.3
2.5
3.3
ns
CWL = 5
1)2)
Average Clock Period with CL = 6; tCK.AVG.CL06.CWL06 1.875 2.5
CWL = 6
RESERVED
RESERVED
1.875 2.5
RESERVED
1.875 2.5
RESERVED
RESERVED
RESERVED
RESERVED
1.875 2.5
ns
1)2)
Average Clock Period with CL = 7; tCK.AVG.CL07.CWL05 RESERVED
CWL = 5
ns
1)2)
Average Clock Period with CL = 7; tCK.AVG.CL07.CWL06 1.875 2.5
CWL = 6
ns
1)2)
Average Clock Period with CL = 8; tCK.AVG.CL08.CWL05 RESERVED
CWL = 5
ns
1)2)
Average Clock Period with CL = 8; tCK.AVG.CL08.CWL06 1.875 2.5
ns
CWL = 6
1) Please refer to "General Notes for Speed Bins" at beginning of this chapter.
2) Max. limits are exclusive. E.g. if tCK.AVG.MAX value is 2.5 ns, tCK.AVG needs to be < 2.5 ns.
Rev. 0.63, 2008-11
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
5
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
•
•
•
•
Table 14 “IMSH1GP03A1F1C” on Page 20
Table 15 “IMSH2GP02A1F1C” on Page 24
Table 16 “IMSH2GP13A1F1C” on Page 28
Table 17 “IMSH4GP12A1F1C” on Page 32
Table 18 “IMSH4GP23A1F1C” on Page 36
Table 19 “IMHH1GP03A1F1C” on Page 40
Table 20 “IMHH2GP02A1F1C” on Page 44
Table 21 “IMHH2GP13A1F1C” on Page 48
Table 22 “IMHH4GP12A1F1C” on Page 52
Table 23 “IMHH4GP23A1F1C” on Page 56
TABLE 14
IMSH1GP03A1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
×72
1 GByte
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
1
2
3
4
5
6
7
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
11
00
01
92
10
0B
01
02
11
00
01
92
10
0B
01
02
11
00
01
92
10
0B
01
02
11
00
01
SDRAM technology key byte
DIMM module type
SDRAM density and banks
SDRAM addressing
Module Nominal Voltage, VDD
Module organization
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
8
Module memory bus width
0B
52
01
08
0F
00
1C
00
69
78
69
3C
0B
52
01
08
0F
00
14
00
78
78
78
3C
0B
52
01
08
0C
00
7E
00
60
78
60
30
0B
52
01
08
0C
00
7C
00
69
78
69
30
9
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
22
23
24
25
26
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
2C
78
11
2C
A4
70
03
3C
60
11
20
80
70
03
3C
69
11
20
8C
70
03
3C
Minimum Active to Precharge Time (tRAS.MIN), LSB
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
Upper Nibble for tFAW
01
2C
02
81
01
2C
02
81
00
F0
02
81
00
F0
02
81
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Rev. 0.63, 2008-11
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
32
33
Module Thermal Sensor
SDRAM Device Type
80
00
00
10
11
00
05
80
00
00
10
11
00
05
80
00
00
10
11
00
05
80
00
00
10
11
00
05
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
00
00
00
00
Thermal Heat Spreader Solution
65 - 69 Reserved
00
00
00
00
00
00
00
00
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
71
Reserved
00
00
00
00
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
64
58
49
07
AD
49
A0
D7
49
B0
48
49
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
Product Type, Char 2
4D
53
48
31
47
50
30
33
41
31
46
31
43
2D
31
30
46
3x
xx
4D
53
48
31
47
50
30
33
41
31
46
31
43
2D
31
30
47
5x
xx
4D
53
48
31
47
50
30
33
41
31
46
31
43
2D
31
33
47
4x
xx
4D
53
48
31
47
50
30
33
41
31
46
31
43
2D
31
33
48
5x
xx
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
23
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 15
IMSH2GP02A1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
12
00
00
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
12
00
00
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
12
00
00
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
12
00
00
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
24
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
11
02
05
01
2C
02
81
80
00
00
10
11
02
05
00
F0
02
81
80
00
00
10
11
02
05
00
F0
02
81
80
00
00
10
11
02
05
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
00
00
00
00
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
25
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
55
55
55
55
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
20
49
49
4D
53
48
32
47
50
30
32
41
31
46
31
43
43
BC
49
4D
53
48
32
47
50
30
32
41
31
46
31
43
E4
C6
49
4D
53
48
32
47
50
30
32
41
31
46
31
43
F4
59
49
4D
53
48
32
47
50
30
32
41
31
46
31
43
Rev. 0.63, 2008-11
26
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
4x
xx
2D
31
33
47
4x
xx
2D
31
33
48
5x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
27
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 16
IMSH2GP13A1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
11
00
09
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
11
00
09
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
11
00
09
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
11
00
09
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
28
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
11
01
05
01
2C
02
81
80
00
00
10
11
01
05
00
F0
02
81
80
00
00
10
11
01
05
00
F0
02
81
80
00
00
10
11
01
05
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
00
00
00
00
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
29
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
00
00
00
00
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
96
30
49
4D
53
48
32
47
50
31
33
41
31
46
31
43
F5
C5
49
4D
53
48
32
47
50
31
33
41
31
46
31
43
52
BF
49
4D
53
48
32
47
50
31
33
41
31
46
31
43
42
20
49
4D
53
48
32
47
50
31
33
41
31
46
31
43
Rev. 0.63, 2008-11
30
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
4x
xx
2D
31
33
47
4x
xx
2D
31
33
48
5x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
31
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 17
IMSH4GP12A1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
12
00
08
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
12
00
08
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
12
00
08
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
12
00
08
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
32
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
11
04
09
01
2C
02
81
80
00
00
10
11
04
09
00
F0
02
81
80
00
00
10
11
04
09
00
F0
02
81
80
00
00
10
11
04
09
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
00
00
00
00
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
33
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
55
55
55
55
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
27
49
49
4D
53
48
34
47
50
31
32
41
31
46
31
43
44
BC
49
4D
53
48
34
47
50
31
32
41
31
46
31
43
E3
C6
49
4D
53
48
34
47
50
31
32
41
31
46
31
43
F3
59
49
4D
53
48
34
47
50
31
32
41
31
46
31
43
Rev. 0.63, 2008-11
34
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
4x
xx
2D
31
33
47
4x
xx
2D
31
33
48
5x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
35
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 18
IMSH4GP23A1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
11
00
19
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
11
00
19
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
11
00
19
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
11
00
19
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
36
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
11
07
09
01
2C
02
81
80
00
00
10
11
07
09
00
F0
02
81
80
00
00
10
11
07
09
00
F0
02
81
80
00
00
10
11
07
09
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
00
00
00
00
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
37
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
55
55
55
55
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
11
FB
49
4D
53
48
34
47
50
32
33
41
31
46
31
43
72
0E
49
4D
53
48
34
47
50
32
33
41
31
46
31
43
D5
74
49
4D
53
48
34
47
50
32
33
41
31
46
31
43
C5
EB
49
4D
53
48
34
47
50
32
33
41
31
46
31
43
Rev. 0.63, 2008-11
38
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
3x
xx
2D
31
33
47
4x
xx
2D
31
33
48
4x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
39
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 19
IMHH1GP03A1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
11
00
01
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
11
00
01
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
11
00
01
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
11
00
01
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
40
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
33
00
05
01
2C
02
81
80
00
00
10
33
00
05
00
F0
02
81
80
00
00
10
33
00
05
00
F0
02
81
80
00
00
10
33
00
05
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
80
80
80
80
Thermal Heat Spreader Solution
65 - 69 Reserved
00
00
00
00
00
00
00
00
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
41
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
00
00
00
00
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
21
A4
49
4D
48
48
31
47
50
30
33
41
31
46
31
43
42
51
49
4D
48
48
31
47
50
30
33
41
31
46
31
43
E5
2B
49
4D
48
48
31
47
50
30
33
41
31
46
31
43
F5
B4
49
4D
48
48
31
47
50
30
33
41
31
46
31
43
Rev. 0.63, 2008-11
42
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
1 GByte
1 GByte
1 GByte
1 GByte
×72
×72
×72
×72
1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
3x
xx
2D
31
33
47
4x
xx
2D
31
33
48
4x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
43
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 20
IMHH2GP02A1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
12
00
00
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
12
00
00
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
12
00
00
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
12
00
00
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
44
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
33
02
05
01
2C
02
81
80
00
00
10
33
02
05
00
F0
02
81
80
00
00
10
33
02
05
00
F0
02
81
80
00
00
10
33
02
05
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
80
80
80
80
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
45
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
55
55
55
55
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
65
B5
49
4D
48
48
32
47
50
30
32
41
31
46
31
43
06
40
49
4D
48
48
32
47
50
30
32
41
31
46
31
43
A1
3A
49
4D
48
48
32
47
50
30
32
41
31
46
31
43
B1
A5
49
4D
48
48
32
47
50
30
32
41
31
46
31
43
Rev. 0.63, 2008-11
46
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
1 Rank (×4) 1 Rank (×4) 1 Rank (×4) 1 Rank (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
3x
xx
2D
31
33
47
4x
xx
2D
31
33
48
4x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
47
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 21
IMHH2GP13A1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
11
00
09
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
11
00
09
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
11
00
09
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
11
00
09
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
48
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
33
01
05
01
2C
02
81
80
00
00
10
33
01
05
00
F0
02
81
80
00
00
10
33
01
05
00
F0
02
81
80
00
00
10
33
01
05
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
80
80
80
80
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
49
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
00
00
00
00
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
D3
CC
49
4D
48
48
32
47
50
31
33
41
31
46
31
43
B0
39
49
4D
48
48
32
47
50
31
33
41
31
46
31
43
17
43
49
4D
48
48
32
47
50
31
33
41
31
46
31
43
07
DC
49
4D
48
48
32
47
50
31
33
41
31
46
31
43
Rev. 0.63, 2008-11
50
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
2 GByte
2 GByte
2 GByte
2 GByte
×72
×72
×72
×72
2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
3x
xx
2D
31
33
47
4x
xx
2D
31
33
48
4x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
51
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 22
IMHH4GP12A1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
12
00
08
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
12
00
08
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
12
00
08
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
12
00
08
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
Rev. 0.63, 2008-11
52
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
33
04
09
01
2C
02
81
80
00
00
10
33
04
09
00
F0
02
81
80
00
00
10
33
04
09
00
F0
02
81
80
00
00
10
33
04
09
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
80
80
80
80
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
Rev. 0.63, 2008-11
53
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
55
55
55
55
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
62
B5
49
4D
48
48
34
47
50
31
32
41
31
46
31
43
01
40
49
4D
48
48
34
47
50
31
32
41
31
46
31
43
A6
3A
49
4D
48
48
34
47
50
31
32
41
31
46
31
43
B6
A5
49
4D
48
48
34
47
50
31
32
41
31
46
31
43
Rev. 0.63, 2008-11
54
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4) 2 Ranks (×4)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
3x
xx
2D
31
33
47
4x
xx
2D
31
33
48
4x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
Rev. 0.63, 2008-11
55
12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
TABLE 23
IMHH4GP23A1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
# of SPD bytes utilized / # of bytes in SPD / CRC
SPD Revision
92
10
0B
01
02
11
00
19
0B
52
01
08
0F
00
1C
00
69
78
69
3C
92
10
0B
01
02
11
00
19
0B
52
01
08
0F
00
14
00
78
78
78
3C
92
10
0B
01
02
11
00
19
0B
52
01
08
0C
00
7E
00
60
78
60
30
92
10
0B
01
02
11
00
19
0B
52
01
08
0C
00
7C
00
69
78
69
30
1
2
SDRAM technology key byte
DIMM module type
3
4
SDRAM density and banks
SDRAM addressing
5
6
Module Nominal Voltage, VDD
Module organization
7
8
Module memory bus width
Fine time base (FTB) dividend and divisor
Medium time base (MTB) dividend
Medium time base (MTB) divisor
9
10
11
12
13
14
15
16
17
18
19
Minimum SDRAM cycle time (tCK.MIN
Reserved
)
CAS Latencies Supported - LSB
CAS Latencies Supported - MSB
Minimum CAS Latency Time (tCK.MIN
Minimum Write Recovery Time (tWR.MIN
Minimum RAS# toCAS# Delay Time (tRCD.MIN
Minimum Row Active to Row Active Delay Time
(tRRD.MIN
)
)
)
)
20
21
Minimum Row PrechargeTime (tRP.MIN
Upper Nibbles for tRAS and tRC
)
69
11
78
11
60
11
69
11
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
HEX
22
23
24
25
26
Minimum Active to Precharge Time (tRAS.MIN), LSB
2C
2C
A4
70
03
3C
20
80
70
03
3C
20
8C
70
03
3C
Minimum Active to Active/Refresh Time (tRC.MIN), LSB 95
Minimum Refresh Recovery Time (tRFC.MIN), LSB
Minimum Refresh Recovery Time (tRFC.MIN), MSB
70
03
Minimum Internal Write to Read Command Delay Time 3C
(tWTR.MIN
)
27
Minimum Internal Read to Precharge Command Delay 3C
3C
3C
3C
Time (tRTP.MIN), MSB
28
29
30
31
32
33
Upper Nibble for tFAW
01
2C
02
81
80
00
00
10
33
07
09
01
2C
02
81
80
00
00
10
33
07
09
00
F0
02
81
80
00
00
10
33
07
09
00
F0
02
81
80
00
00
10
33
07
09
Minimum Four Activate Window Delay Time (tFAW.MIN
SDRAM Optional Features
)
SDRAM Thermal and Refresh Options
Module Thermal Sensor
SDRAM Device Type
34 - 59 Reserved
60
61
62
63
Module Nominal Height
Module Maximum Thickness
Raw Card used
Address Mapping from Edge Connector to DRAM
DIMM Module Attributes
64
Reserved
80
80
80
80
Thermal Heat Spreader Solution
65 - 69 Reserved
00
50
00
50
00
50
00
50
70
Reserved
RC3 (MS Nibble) / RC2 (LS Nibble) - Drive
Strength,Command/Address
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
HEX
HEX
71
Reserved
55
55
55
55
RC5 (MS Nibble) / RC4 (LS Nibble) - Drive
Strength,Control and Clock
72 - 116 Reserved
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
00
85
51
xx
xx
117
118
119
DIMM Manufacturer’s ID Code LSB
DIMM Manufacturer’s ID Code MSB
Module Manufacturing Location
Module Manufacturing Date
120 -
121
122 -
125
Module Serial Number
xx
xx
xx
xx
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Product Type, Char 1
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
54
07
49
4D
48
48
34
47
50
32
33
41
31
46
31
43
37
F2
49
4D
48
48
34
47
50
32
33
41
31
46
31
43
90
88
49
4D
48
48
34
47
50
32
33
41
31
46
31
43
80
17
49
4D
48
48
34
47
50
32
33
41
31
46
31
43
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Product Type
Organization
4 GByte
4 GByte
4 GByte
4 GByte
×72
×72
×72
×72
4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8) 4 Ranks (×8)
Label Code
PC3–
PC3–
PC3–
PC3–
8500P–7
8500P–8
10600P–8
10600P–9
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
142
143
144
145
146
147
148
149
Product Type, Char 15
2D
31
30
46
3x
xx
2D
31
30
47
3x
xx
2D
31
33
47
4x
xx
2D
31
33
48
4x
xx
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code, LSB
Module Revision Code, MSB
DRAM Manufacturer’s ID Code, LSB
DRAM Manufacturer’s ID Code, MSB
Manufactures’s Specific Data
85
51
00
85
51
00
85
51
00
85
51
00
150 -
175
176 -
255
Blank for Customer Use
FF
FF
FF
FF
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
6
Package Outline Diagrams
FIGURE 2
Package Outline LG-DIM-240-091 R/C A
)32B/*ꢇ',0BBBBꢇꢈꢉꢁꢇꢁꢆꢂ
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details
please refer to SDRAM Component Data Sheet.
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
FIGURE 3
Package Outline LG-DIM-240-092 R/C B
)32B/*ꢇ',0BBBBꢇꢈꢉꢁꢇꢁꢆꢈ
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details
please refer to SDRAM Component Data Sheet.
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
FIGURE 4
Package Outline LG-DIM-240-093 R/C C
)32B/*ꢇ',0BBBBꢇꢈꢉꢁꢇꢁꢆꢃ
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details
please refer to SDRAM Component Data Sheet.
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Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
FIGURE 5
Package Outline LG-DIM-240-097 R/C E
)32B/*ꢇ',0BBBBꢇꢈꢉꢁꢇꢁꢆꢅ
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details
please refer to SDRAM Component Data Sheet.
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
FIGURE 6
Package Outline LG-DIM-240-098 R/C H
)32B/*ꢇ',0BBBBꢇꢈꢉꢁꢇꢁꢆꢋ
Note: SDRAM component outlines are symbolic representation of the device placement. For actual SDRAM outline details
please refer to SDRAM Component Data Sheet.
Rev. 0.63, 2008-11
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12122007-WJ2L-RGDP
Advance Internet Data Sheet
DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
FIGURE 7
Package Outline for Modules with Heat Spreader
)32B/*ꢇ',0B''5ꢃꢇBBBꢇ+6
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
7
Product Type Nomenclature
For reference the applicable Qimonda DDR3 DIMM module nomenclature is listed in this chapter.
TABLE 24
Example: DDR3 1GByte Registered Module
Field Number
1+2
3
4
5+6
7
8
9
10+11
12+13
14
15
16+17
18
Qimonda Product Type
IM
S
H
4G
P
1
2
A1
F2
C
–
08
E
TABLE 25
DDR3 DIMM Nomenclature
Field Description
Value
Coding
1+2
3
Qimonda Identifier
IM
S
Qimonda Memory modules
Standard
Power or Application
H
Heat Spreader
Low Power
L
4
Product Family
Density
H
DDR3
5+6
51
1G
2G
4G
U
512 MBytes
1024 MBytes
2048 MBytes
4096 MBytes
7
Module Type / ECC Support
240 pin unbuffered DIMMs - Non-ECC
240 pin unbuffered DIMMs - ECC
204 pin Small Outline DIMMs - Non-ECC
240 pin Registered DIMMs - ECC
240 pin Registered DIMMs with Parity Bit - ECC
One Rank of SDRAMs
E
S
R
P
8
9
Number of Ranks
0
1
Two Ranks of SDRAMs
2
Four Ranks of SDRAMs
×4 components (22)
DRAM Device Number of IOs
2
3
×8 components (23)
4
×16 components (24)
10+11 Die Revision
12+13 Package
A1
F1
F2
C
First
Planar FBGA, lead- and halogen-free
Dual Die FBGA, lead- and halogen-free
Commercial (0 °C - 95 °C)
Modules with Thermal Sensor
14
15
Temperature Range
Thermal Sensor
T
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DDR3 Registered DIMM
IM[S/H]H[1G/2G/4G]PxxA1F1C
Field Description
Value
Coding
16+17 Band Width
08
10
13
16
D
PC3–6400, 6.4 GB/s, tCK = 2.5 ns, fCK =400 MHz
PC3–8500, 8.5 GB/s, tCK = 1.875 ns, fCK =533 MHz
PC3–10600, 10,66 GB/s, tCK = 1.5 ns, fCK =667 MHz
PC3–12800, 12,8 GB/s, tCK = 1.25 ns, fCK =800 MHz
CL–RCD–RP = 5–5–5
18
Latencies
E
CL–RCD–RP = 6–6–6
F
CL–RCD–RP = 7–7–7
G
H
CL–RCD–RP = 8–8–8
CL–RCD–RP = 9–9–9
J
CL–RCD–RP = 10–10–10
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IM[S/H]H[1G/2G/4G]PxxA1F1C
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Speed Bins and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
6
7
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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Advance Internet Data Sheet
Edition 2008-11
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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